CN216450670U

CN216450670U - Flip chip structure

Info

Publication number: CN216450670U
Application number: CN202123415665.3U
Authority: CN
Inventors: 王思博; 廖汉忠; 芦玲
Original assignee: Huaian Aucksun Optoelectronics Technology Co Ltd
Current assignee: Huaian Aucksun Optoelectronics Technology Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-05-06
Anticipated expiration: 2031-12-31

Abstract

The utility model relates to the field of light emitting diodes, and discloses a flip chip structure which comprises a substrate, an epitaxial layer, a first electrode layer, a first insulating layer and a second electrode layer, wherein the substrate, the epitaxial layer, the first electrode layer, the first insulating layer and the second electrode layer are sequentially arranged from bottom to top; the first electrode layer comprises a plurality of first P-type and second N-type electrodes; the second electrode layer comprises a plurality of second P-type and second N-type electrodes; the first and second P-type electrodes are electrically connected, and the first and second N-type electrodes are electrically connected; the first electrode layer is provided with a plurality of regular hexagon units consisting of a first N-type electrode and four to six first P-type electrodes, the first N-type electrodes are positioned at the centers of the regular hexagon units, and the first P-type electrodes are circumferentially distributed by taking the first N-type electrodes as the centers. This application makes the electric current extension more even through the adjustment to the first P type of product and N type electrode distribution, and luminous distribution area is more even, and luminous distribution area grow improves luminance, and reduce voltage reaches higher product light efficiency ability.

Description

Flip chip structure

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a flip chip structure.

Background

A light emitting diode (LED for short) is a commonly used light emitting device, has the advantages of low voltage, low power consumption, small volume, long service life, and the like, and is widely used in the fields of illumination, display, and the like. LEDs are widely used as a new generation of light source in the fields of illumination, display, backlight, and optical communication. The flip chip has been more and more favored by the market as a product with higher light efficiency, and the flip chip has more process structures and complex process, so that the flip chip has higher requirements and challenges on reliability. The light efficiency becomes an important parameter for measuring the LED product, and how to improve the LOP and reduce the voltage requirement, so that the improvement of the whole light efficiency becomes increasingly important. In view of the above, the present invention is particularly proposed.

SUMMERY OF THE UTILITY MODEL

Utility model purpose: aiming at the problems in the prior art, the utility model provides a flip chip structure, which enables the current expansion to be more uniform, the light emitting distribution area to be enlarged, the brightness to be improved, the voltage to be reduced and the higher light efficiency capability of the product to be achieved by adjusting the distribution of a first P-type electrode and a first N-type electrode of the product.

The technical scheme is as follows: the utility model provides a flip chip structure, which comprises a substrate, an epitaxial layer with a PN step, a first electrode layer, a first insulating layer and a second electrode layer, wherein the substrate, the epitaxial layer with the PN step, the first electrode layer, the first insulating layer and the second electrode layer are sequentially arranged from bottom to top; the first electrode layer comprises a plurality of first P-type electrodes and a plurality of first N-type electrodes; the second electrode layer comprises a plurality of second P-type electrodes and a plurality of second N-type electrodes; the first P-type electrode is electrically connected with the second P-type electrode through a first through hole formed in the first insulating layer, and the first N-type electrode is electrically connected with the second N-type electrode through a second through hole formed in the first insulating layer; the first electrode layer is provided with a plurality of regular hexagon units formed by one first N-type electrode and four to six second P-type electrodes, the first N-type electrode is positioned in the center of each regular hexagon unit, and each first P-type electrode is circumferentially distributed by taking the first N-type electrode as the center.

Preferably, each regular hexagon unit comprises six first P-type electrodes, and the six first P-type electrodes are respectively distributed on six corners of the regular hexagon unit.

Preferably, the first P-type electrodes distributed on six corners of the regular hexagonal cells are circular; the first N-type electrodes distributed in the centers of the regular hexagonal cells are circular.

Preferably, each regular hexagon cell includes five first P-type electrodes, one of the first P-type electrodes is distributed on one edge of the regular hexagon cell and overlaps with the edge, and the remaining four first P-type electrodes are distributed on the remaining four corners of the regular hexagon cell respectively.

Preferably, the first P-type electrodes distributed on one side of the regular hexagonal cell and overlapped with the side are finger-shaped, and the other four first P-type electrodes distributed on the other four corners of the regular hexagonal cell are circular; the first N-type electrodes distributed in the centers of the regular hexagonal cells are circular. When the first P-type electrode is in a finger shape, the VF voltage of the prepared chip is lower, and the brightness is also reduced, so that the finger shape or the circular shape is selected according to actual needs.

Preferably, each of the regular hexagonal cells includes four first P-type electrodes, one of the first P-type electrodes is distributed on two sides of the regular hexagonal cell and overlaps with the two sides, and the remaining three first P-type electrodes are distributed on the remaining three corners of the regular hexagonal cell.

Preferably, the first P-type electrodes distributed on two edges of the regular hexagonal unit and overlapped with the two edges are zigzag-shaped, and the other three first P-type electrodes distributed on the other three corners of the regular hexagonal unit are circular; the first N-type electrodes distributed in the centers of the regular hexagonal cells are circular. The zigzag shape is an extension of a finger shape, that is, the area of the first P-type electrode is changed greatly, and the larger the area ratio of the first P-type electrode is, the more VF decreases, and the more luminance decreases.

Preferably, in each regular hexagon unit, an included angle between a first N-type electrode and a connecting line at two ends of one of the first P-type electrodes is 10-170 degrees;

and/or the included angle between the connecting lines of the first N-type electrode and the two adjacent first P-type electrodes is 10-170 degrees.

Preferably, in each regular hexagon unit, the distance between the first N-type electrode and any one first P-type electrode is 10-300 um.

Preferably, in each regular hexagon cell, the first N-type electrode and any one of the first P-type electrodes have equal or unequal intervals.

Has the advantages that: the utility model of the application is characterized in that the first P-type electrode and the first N-type electrode of the product are distributed, a hexagonal design is adopted, and the mode that P surrounds N and the design of an included angle are adopted, so that the current expansion is more uniform, the light-emitting distribution area is enlarged, the brightness is improved, the voltage is reduced, and the higher light efficiency capability of the product is achieved. The flip LED chip using the design can have better light efficiency and reliability.

Drawings

Fig. 1 is a schematic plan view of a flip LED chip in embodiment 1 of the present application;

fig. 2 is a schematic structural diagram of a flip LED chip in embodiment 1 of the present application;

fig. 3 is a schematic view of a regular hexagonal cell in the first electrode layer in embodiment 1;

fig. 4 is a schematic view of a regular hexagonal cell in the first electrode layer in embodiment 2;

fig. 5 is a schematic view of a regular hexagonal cell in the first electrode layer in embodiment 3;

fig. 6 is a schematic plan view of a flip LED chip in a comparative example;

reference numerals:

100-a substrate;	210-N type semiconductor layer;	211-Mesa step;
			220-multiple quantum well active layer;	a 230-P type semiconductor layer;	300-a current blocking layer;
400-current spreading layer;	510-a first P-type electrode;	511-a first via;
			520-a first N-type electrode;	521-a second through hole;	600-a first insulating layer;
710-a second P-type electrode;	720-a second N-type electrode;	800-a second insulating layer;
			900-support layer;	1000-a third insulating layer;	1100-third via;
1200-a fourth via;	1310-P pad electrode;	1320-N pad electrode;
			1410-ISO holding tank.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings.

Embodiment 1:

as shown in fig. 1 and 2, the flip LED chip provided in the embodiment of the present invention includes a substrate 100, an epitaxial layer, a current blocking layer 300, a current spreading layer 400, a first electrode layer, a first insulating layer 600, a second electrode layer, a second insulating layer 800, and a pad electrode layer, which are sequentially disposed from bottom to top; the first electrode layer comprises a plurality of circular first P-type electrodes 510 and a plurality of circular first N-type electrodes 520; there are several regular hexagonal cells (such as the dotted line regular hexagon shown in fig. 1) composed of one first N-type electrode 520 and six second P-type electrodes 510, the first N-type electrode 520 is located at the center of the regular hexagonal cells, and the six first P-type electrodes 510 are circumferentially distributed with the first N-type electrode 520 as the center, that is, the six first P-type electrodes 510 are respectively distributed on six corners of the regular hexagonal cells. In each regular hexagon cell, the included angle between the connecting lines of two adjacent first P-type electrodes 510 and first N-type electrodes 520 is 60 °, that is, < a, < b, < c, < d, < e, < f in fig. 3 is 60 °. In each regular hexagonal cell, the first N-type electrode 520 is equally spaced from any one of the first P-type electrodes 510, and may be 10-300 um. The second electrode layer comprises a plurality of second P-type electrodes 710 and a plurality of second N-type electrodes 720; the pad electrode layer includes at least one P-type pad 1310 and at least one N-type pad 1320.

Other structures of the flip chip structure in this embodiment mode are provided as conventional light emitting elements. The method comprises the following specific steps:

the epitaxial layer is arranged on the surface of the substrate 100 and comprises an N-type semiconductor layer 210, a light emitting layer 220 and a P-type semiconductor layer 230 which are sequentially stacked on the surface of the substrate 100; the structure further comprises a PN step 211, wherein the upper step surface of the PN step 211 is a P-type semiconductor layer 230, the lower step surface is an N-type semiconductor layer 210, and the upper step surface and the lower step surface are connected to form the side surface of the PN step 211; an N-type semiconductor layer 210 formed on the substrate 100 to cover the substrate; a P-type semiconductor layer 230 formed to cover a region on the N-type semiconductor layer 210 other than the region for the N-electrode on the N-type semiconductor layer 210, for emitting light in cooperation with the N-type semiconductor layer 210; the current blocking layer 300 and the current spreading layer 400 are sequentially disposed on the surface of the P-type semiconductor layer 230;

the first electrode layer includes a first P-type electrode 510 formed on the P-type semiconductor layer 230 and a first N-type electrode 520 for an N-electrode region formed on the N-type semiconductor layer 210; the first P-type electrode 510 is connected to the current spreading layer 400; the first N-type electrode 520 is connected to the lower step surface of the PN step 211; the first P-type electrode 510 and the first N-type electrode 520 are isolated from each other; the first insulating layer 600 covers the first N-type electrode 520, the current spreading layer 400, the side of the PN step 211, the first P-type electrode 510, and the lower step surface between the first N-type electrode 520 and the side of the PN step 211; the first insulating layer 600 is used for insulating the first N electrode from the first P electrode, and a first via 511 penetrating the first P-type electrode 510 and a second via 521 penetrating the first N-type electrode 520 are disposed on the first insulating layer 600;

the second electrode layer comprises a second P-type electrode 710 and a second N-type electrode 720, and the second P-type electrode 710 and the second N-type electrode 720 are insulated and isolated from each other; the second P-type electrode 710 is connected to the first P-type electrode 510 through the first via 511; the second N-type electrode 720 is connected to the first N-type electrode 520 through the second via 521; the second insulating layer 800 is disposed on the surface of the second electrode layer;

the third through hole 1100 and the fourth through hole 1200 penetrate through the second insulating layer 800 and are respectively communicated with the second P-type electrode 710 and the second N-type electrode 720;

the pad electrode layer includes a P pad electrode 1310 and an N pad electrode 1320, the P pad electrode 1310 and the N pad electrode 1320 being isolated from each other; the P-pad electrode 1310 and the second P-type electrode 710 are electrically connected through the third via 1100, and the N-pad electrode 1320 and the second N-type electrode 720 are electrically connected through the fourth via 1200.

The substrate 100 may include, but is not limited to, a sapphire substrate, among others. In addition, a patterned substrate may also be selected.

The material of the N-type semiconductor layer 210 may be N-type doped gan, and the material of the P-type semiconductor layer 230 may be P-type doped gan, but the utility model is not limited to these two semiconductor types.

Here, the light emitting layer 220 includes quantum wells and quantum barriers alternately stacked, but is not limited thereto. The light emitting layer 220 includes, but is not limited to, a red light emitting layer, a yellow light emitting layer, a green light emitting layer, or a blue light emitting layer. Quantum wells include, but are not limited to, InGaN quantum wells or AlInGaN quantum wells.

Wherein the current blocking layer 300 includes, but is not limited to, SiO₂The thickness of the current blocking layer 300 is generally 1500-.

The current spreading layer 400 occupies 70-90% of the area of the light emitting element, and includes but is not limited to one of ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO, and GZO. The thickness of the current spreading layer 400 is 100A-500A, for example, 100A, 150A, 200A, 300A, 500A. The current spreading layer 400 may be deposited by magnetron sputtering or evaporation.

The first through hole 511 and the second through hole 521 are separated from each other, and do not extend and intersect; as shown in fig. 5, the third via 1100 and the fourth via 1200 are separated from each other without any extended intersection, thereby ensuring separation of the upper and lower hetero-electrodes and cutting off a possible leakage path.

Wherein the first insulating layer 600 is a DBR reflective layer, which can be SiO deposited alternately₂And Ti₃O₅And (4) forming. The thickness of the first insulating layer 600 is 2 μm to 6 μm, preferably 3.5 μm to 5.5 μm.

Wherein the second insulating layer 800 and/or the third insulating layer 1000 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. The thickness of the second insulating layer 800 and/or the third insulating layer 1000 is 5-15K A, for example 6K A, 8K A, 13K A, 15K A.

Among the pad electrode layers, the number of the P pad electrodes 1310 may be 1, 2 or more; the N pad electrodes 1320 may be 1, 2, or more. The pad electrode comprises a single metal layer of Cr, Ni, Ti, Pt and Au or a composite layer of several metals and/or alloys. The thickness of Al is 5K-20K A, the thickness of Pt is 0.5K-3K A, the thickness of Ti is 0.5-3K A, the thickness of Ni is 3K-12K A, and the thickness of Au is 1K-5K A. The pad electrodes are Bump electrodes including Sn components, i.e., the P pad electrode 1310 and the N pad electrode 1320 may be Bump electrodes, and the electrode components are Sn. The bump electrode can be made by printing, electroplating or evaporation. The height of the Bump electrode is more than or equal to 5 mu m, and the height of the solder paste is more than or equal to 20 mu m.

The embodiment of the utility model also provides a preparation method of the light-emitting element, which specifically comprises the following steps:

s1, providing a substrate 100, and sequentially depositing an N-type semiconductor layer 210, a light emitting layer 220 and a P-type semiconductor layer 230 on the substrate 100 to form an epitaxial layer;

s2, depositing SiO on the epitaxial layer₂Preparing a CBL current barrier layer 300 by yellow light and etching, removing the photoresist, and ensuring that the etching angle is 20-40 degrees; the current blocking layer 300 is located between the P-type semiconductor layer 230 and the current spreading layer 400 and plays a role in assisting current spreading, and the thickness of the current blocking layer 300 is generally 0.8K a-5K a.

S3, depositing an ITO current expansion layer 400 with a thickness of 150-2000A through magnetron sputtering or evaporation, realizing the photoresist morphology of the ITO current expansion layer 400 through yellow light, etching the current expansion layer 400 once to ensure that a better etching line is formed, wherein the photoresist thickness is about 2-5 μm, and etching the current expansion layer 400 once again through ICP etching to form a Mesa step 211 after one etching, wherein N-GaN is exposed, and the step depth is 1-1.6 um. The ICP etching is followed by a secondary etch of the current spreading layer 400. In order to avoid forming an MESA side wall angle larger than 80 degrees, the line width of the current expansion layer 400 and the photoresist after the first etching is 1-4 μm, and the line width of the current expansion layer 400 and the MESA after the second etching is 2-6 μm. And removing the photoresist. The MESA angle of ICP etching is between 20 DEG and 80 DEG, so that the back film layer has better coverage.

S4, in order to prevent electric leakage of the side wall of the chip package, the N-GAN at the position of a cutting channel is etched cleanly by utilizing a yellow light and ICP etching technology to form an ISO isolation groove with the height of about 3-6.5 microns, photoresist is removed, and the etching angle is required to be 30-80 degrees;

s5, performing photolithography with photoresist, depositing to form a first electrode layer, where the first electrode layer includes a first P-type electrode 510 and a first N-type electrode 520, the first P-type electrode 510 covers the stacked film layer of the current blocking layer 300 and the current spreading layer 400, and then removing the photoresist, and the first electrode layer structure may adopt an electrode structure of Cr/Al/Ti/Ni/PT/Au, where the underlying metal may be Al, Cr Al, Ti Al, Ni Al, etc. And removing the photoresist after deposition, wherein the deposition angle of the first electrode layer is 20-60 degrees.

S6, in order to improve the coverage of the film layer, a plasma enhanced chemical vapor deposition technology is adopted to deposit SiO2 or SixNy with the thickness of about 1K-10K, a DBR Bragg reflection film layer is prepared, namely the first insulation layer 600 is formed by alternately stacking high-refractive-index materials and low-refractive-index materials, the high-refractive-index materials can be TixOy or Nb2O5 or Ta2O5, the single-layer thickness range is 0.2 KA-2 KA, the low-refractive-index materials are SiO2, the single-layer thickness range is 0.2 KA-2 KA, the spectral bandwidth can be 380 nm-900 nm or part of the spectral bandwidth in the range, the high-refractive index is larger than or equal to 90%, the number of layers of the first insulation layer 600 can be 20-60 layers, and the thickness is about 2 μm-6 μm. The first insulating layer 600 may employ an electron-assisted evaporation apparatus or a magnetron sputtering apparatus.

S7, performing photoetching on the first insulating layer 600 by using photoresist, forming a first insulating layer pattern on the photoresist, performing ICP etching, and performing photoetching on the upper parts of the first P-type electrode 510 and the first N-type electrode 520 to obtain a first through hole 511 and a second through hole 521 respectively; the first through hole 511 and the second through hole 521 are required to have an angle of 25 to 70 °. The etching gas comprises CF4, BCl3, Ar, O2 and other gases, and two-section etching processes are adopted, wherein the first-section DBR etching rate is 10A/s-40A/s, the second-section slow etching rate is 5A/s-10A/s, and the two-section etching process technology has higher flexibility and controllability. The residual quantity of the etched glue is 0.5-5 mu m, and the reliability of the P-Finger is fully ensured. A first via 511 and a second via 521 in the present design; the current is uniformly distributed in the whole chip, so that the chip has more uniform injection current.

S8, depositing a second electrode layer and then removing the photoresist; the second P-type electrode 710 is communicated with the first P-type electrode 510 through the first via 511, and the second N-type electrode 720 is communicated with the first N-type electrode 520 through the second via 521; the second electrode layer structure can contain metals such as Cr, Al, Ni, Pt, Ti, Au and the like, wherein the bottom layer metal is Al, Cr Al, Ti Al, Ni Al, Ag, Ni Ag, Cr Ag and the like, so that the electrode reflectivity is 60-95%, and the angle of the second electrode layer is required to be 30-75 degrees to ensure the subsequent film covering.

S9, a second insulating layer 800 is covered on the second P-type electrode 710 and the second N-type electrode 720. Insulating materials such as silicon oxide, silicon nitride or silicon oxynitride are deposited on the layer by PECVD, and the thickness of the insulating material is 1K A-20K A.

S10, etching to obtain a third through hole 1100 and a fourth through hole 1200 which penetrate through the second insulating layer 800; the etching angle is required to be 20-80 degrees.

S11, preparing pad electrodes by yellow light and deposition, forming a P pad electrode 1310 and an N pad electrode 1320; the P-pad electrode 1310 is connected to the second P-type electrode 710 through a third via 1100, and the N-pad electrode 1320 is connected to the second N-type electrode 720 through a fourth via 1200; the bonding pad electrode is made of metal such as Ti, Al, Pt, Ni and Au, wherein the Al thickness is 5K-20K A, the Pt thickness is 0.5 KA-3 KA, the Ti thickness is 0.5-3 KA, the Ni thickness is 3 KA-12 KA, and the Au thickness is 1K-5K A.

S11, grinding and cutting to form core particles, wherein the grinding thickness is in the range of 80-300 μm.

The test results of the light efficiency and reliability of the flip-chip LED chip prepared by the distribution design of the first P-type electrode 510 and the first N-type electrode 520 in this embodiment are shown in table 1 below.

Embodiment 2:

this embodiment is substantially the same as embodiment 1, except that in this embodiment, the first electrode layer includes five first P-type electrodes 510 in each regular hexagonal cell, one of the first P-type electrodes 510 is finger-shaped, is distributed on one of the sides of the regular hexagonal cell and overlaps the one side, and the remaining four first P-type electrodes 510 are circular and are distributed on the remaining four corners of the regular hexagonal cell. As shown in fig. 4. In each regular hexagon cell, the included angle between the first N-type electrode 520 and the connecting line of the two ends of the first P-type electrode in the finger shape is ≦ b =60 °, the included angles between the first N-type electrode 520 and the connecting lines between the other four circular first P-type electrodes adjacent to each other and the first N-type electrode are ≦ d = e = f =60 °, and the included angles between the two ends of the first P-type electrode in the finger shape and the connecting line of the first P-type electrode in the adjacent circular shape and the first N-type electrode are = a = c =60 °. In each regular hexagon cell, the distance between the first N-type electrode 520 and the first P-type electrode is 10-300 μm, and the distance h between the first P-type electrode 510 is 8-260 μm.

Otherwise, this embodiment is identical to embodiment 1, and will not be described herein.

Embodiment 3:

this embodiment is a further improvement of embodiment 1, and the main improvement is that, in the first electrode layer, each regular hexagonal cell includes four first P-type electrodes 510, one of the first P-type electrodes 510 is in a zigzag shape, and is distributed on two adjacent edges of the regular hexagonal cell and overlaps with the two edges, and the remaining three first P-type electrodes 510 are in a circular shape and are respectively distributed on the remaining three corners of the regular hexagonal cell. As shown in fig. 5. In each regular hexagon cell, the included angle between the first N-type electrode 520 and the connecting line of the two ends of the first P-type electrode in a broken line shape is ≦ b + < c =120 °, the included angles between the first N-type electrode 520 and the connecting lines between the first N-type electrode and the other three first P-type electrodes in a circular shape adjacent to each other in pairs are ≦ e = f =60 °, and the included angles between the two ends of the first P-type electrode in a broken line shape and the connecting line of the first P-type electrode in an adjacent circular shape and the first N-type electrode are = a = d =60 °. In each regular hexagon unit, the distance between the first N-type electrode 520 and the first P-type electrode is 10-300 μm, and the distance h between the first N-type electrode and the first P-type electrode 510 is 8-260 μm.

The test results of the luminous efficiency and reliability of the flip-chip LED chip prepared by the distribution design of the first P-type electrode and the first N-type electrode in this embodiment are shown in table 1 below.

Comparative example

The present comparative example is different from embodiments 1 to 3 in that, in the present embodiment, the first P-type electrode 510 and the second N-type electrode 520 are not in a regular hexagonal design in the first electrode layer, as shown in fig. 6.

The test results of the light efficiency and reliability of the flip LED chip in the comparative example are shown in the following table 1.

When the flip LED chips described in embodiments 1, 2, and 3 and the comparative example were subjected to a comparative test under the same test condition with a test current of 65mA, the light efficiency of the flip LED chips provided in embodiments 1, 2, and 3 of the present invention was improved by 3%, 2.2%, and 1.6%, respectively, compared to the comparative example.

TABLE 1

	Voltage (V)	Luminance (lm)	Light efficiency (lm/W)	Light efficiency enhancement
					Embodiment mode 1	2.71	40.5	229.9	3%
Embodiment mode 2	2.69	39.9	228.2	2.2%
					Embodiment 3	2.68	39.5	226.7	1.6%
Comparative example	2.75	39.9	223.2	---

The above embodiments are merely illustrative of the technical concepts and features of the present invention, and the purpose of the embodiments is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims

1. A flip chip structure comprises a substrate (100), an epitaxial layer with a PN step, a first electrode layer, a first insulating layer (600) and a second electrode layer which are arranged from bottom to top in sequence; the first electrode layer comprises a plurality of first P-type electrodes (510) and a plurality of first N-type electrodes (520); the second electrode layer comprises a plurality of second P-type electrodes (710) and a plurality of second N-type electrodes (720); the first P-type electrode (510) is electrically connected with the second P-type electrode (710) through a first through hole (511) formed in the first insulating layer (600), and the first N-type electrode (520) is electrically connected with the second N-type electrode (720) through a second through hole (521) formed in the first insulating layer (600); it is characterized in that the preparation method is characterized in that,

in the first electrode layer, a plurality of regular hexagon units are formed by one first N-type electrode (520) and four to six first P-type electrodes (510), the first N-type electrode (520) is positioned in the center of each regular hexagon unit, and each first P-type electrode (510) is circumferentially distributed by taking the first N-type electrode (520) as the center.

2. The flip-chip structure of claim 1, wherein each of the regular hexagonal cells comprises six of the first P-type electrodes (510), and the six first P-type electrodes (510) are respectively distributed on six corners of the regular hexagonal cell.

3. The flip-chip structure of claim 2, wherein the first P-type electrodes (510) distributed over six corners of the regular hexagonal cells are circular; the first N-type electrodes (520) distributed in the centers of the regular hexagonal cells have a circular shape.

4. The flip-chip structure of claim 1, wherein each of the regular hexagonal cells comprises five of the first P-type electrodes (510), wherein one of the first P-type electrodes (510) is disposed on and overlaps one of the edges of the regular hexagonal cell, and the remaining four of the first P-type electrodes (510) are disposed at the remaining four corners of the regular hexagonal cell.

5. The flip-chip structure of claim 4, wherein the first P-type electrodes (510) distributed on and overlapping one of the sides of the regular hexagonal cells are finger-shaped, and the remaining four first P-type electrodes (510) distributed on the remaining four corners of the regular hexagonal cells are circular; the first N-type electrodes (520) distributed in the centers of the regular hexagonal cells are circular.

6. The flip-chip structure of claim 1, wherein each of the regular hexagonal cells comprises four of the first P-type electrodes (510), wherein one of the first P-type electrodes (510) is disposed on and overlaps two of the sides of the regular hexagonal cell, and the remaining three of the first P-type electrodes (510) are disposed at the remaining three corners of the regular hexagonal cell.

7. The flip-chip structure of claim 6, wherein the first P-type electrodes (510) distributed on and overlapping two sides of the regular hexagonal cells are polygonal-shaped, and the remaining three first P-type electrodes (510) distributed on the remaining three corners of the regular hexagonal cells are circular-shaped; the first N-type electrodes (520) distributed in the centers of the regular hexagonal cells are circular.

8. The flip-chip structure according to any one of claims 1 to 7, wherein in each of the regular hexagonal cells, an angle between a first N-type electrode (520) and a line connecting both ends of one of the first P-type electrodes is 10 to 170 °;

and/or the included angle between the first N-type electrode (520) and the connecting line of two adjacent first P-type electrodes (510) is 10-170 degrees.

9. The flip-chip structure of any of claims 1 to 7, wherein in each of the regular hexagonal cells, a distance between the first N-type electrode (520) and any one of the first P-type electrodes (510) is 10-300 um.

10. The flip-chip structure of any of claims 1 to 7, wherein in each of the regular hexagonal cells, a spacing between a first N-type electrode (520) and any one of the first P-type electrodes (510) is equal or unequal.