CN216213514U

CN216213514U - Light-emitting diode chip, light-emitting module and light-emitting or display device

Info

Publication number: CN216213514U
Application number: CN202122557197.7U
Authority: CN
Inventors: 王绘凝; 夏宏伟; 曹林华; 张丽明; 唐荷映; 杨人龙; 张中英
Original assignee: Xiamen Sanan Optoelectronics Technology Co Ltd
Current assignee: Xiamen Sanan Optoelectronics Technology Co Ltd
Priority date: 2021-10-22
Filing date: 2021-10-22
Publication date: 2022-04-05
Anticipated expiration: 2031-10-22

Abstract

The utility model provides a light-emitting diode chip, at least comprising: epitaxial structure, current blocking layer and current extension layer. The epitaxial structure includes a first conductive type semiconductor layer, a light emitting layer, and a second conductive type semiconductor layer, which are sequentially stacked. The current blocking layer is formed on the second conductive type semiconductor layer. The current spreading layer at least comprises a first sub-current spreading layer and a second sub-current spreading layer which are sequentially stacked on the current blocking layer. The first sub-current spreading layer is formed on the current blocking layer and covers at least an upper surface and a sidewall region of the current blocking layer and a portion of an upper surface of the second conductive type semiconductor layer. The second sub-current spreading layer is formed on the first sub-current spreading layer and covers at least an upper surface and a sidewall region of the first sub-current spreading layer and a portion of an upper surface of the second conductive type semiconductor layer. Therefore, the current spreading effect in the light emitting diode chip is favorably improved, and the ESD resistance is improved.

Description

Light-emitting diode chip, light-emitting module and light-emitting or display device

Technical Field

The utility model relates to the technical field of semiconductor light-emitting devices, in particular to a light-emitting diode chip.

Background

Currently, an LED (light emitting diode) has become an indispensable photoelectric device in daily life due to its multiple comprehensive advantages of high luminous efficiency, low energy consumption, long service life, high environmental protection, and the like. LED light emitting devices have been widely used in the field of lighting in different scenes, such as digital tubes, display screens, backlights, lamps for automobiles, traffic lights, landscape lighting, plant lighting in agriculture, and the like.

The brightness of the LED lighting device is one of the factors that measure the superiority of LED performance. Therefore, it is one of the issues that practitioners in the industry focus on how to improve the antistatic (ESD) capability of LED chips and thus improve the light emitting efficiency.

Chinese patent document CN110957405A (application No. 201911369513.9) discloses an LED chip and a method for manufacturing the same, in which a current blocking layer and a current spreading layer are sequentially disposed above a P-type semiconductor layer, and the current spreading layer is a double-layer current spreading layer, so as to increase the light transmittance of the current spreading layer, reduce the absorption of the current spreading layer on the emergent light, and improve the luminous power of the LED chip. However, the current spreading layer in direct contact with the current blocking layer in such an LED chip only partially covers the sidewalls of the current blocking layer, so that the thickness of the current spreading layer on the sidewalls of the current blocking layer is insufficient, resulting in a low level of ESD resistance of the LED chip.

SUMMERY OF THE UTILITY MODEL

In order to solve the defect of ESD resistance of a plurality of current expansion layers in the conventional LED chip, the utility model provides a light-emitting diode chip for improving the ESD resistance and the light-emitting efficiency.

To achieve at least one of the advantages or other advantages, an embodiment of the utility model provides a light emitting diode chip, including at least: an epitaxial structure including a first conductive type semiconductor layer, a light emitting layer, and a second conductive type semiconductor layer sequentially stacked; a current blocking layer on the second conductive type semiconductor layer; and the current spreading layer at least comprises a first sub-current spreading layer and a second sub-current spreading layer which are sequentially stacked on the current blocking layer. Wherein the first sub-current spreading layer is formed on the current blocking layer and covers at least an upper surface and a sidewall region of the current blocking layer and a portion of an upper surface of the second conductive type semiconductor layer. The second sub-current spreading layer is formed on the first sub-current spreading layer and covers at least an upper surface and a sidewall region of the first sub-current spreading layer and a portion of an upper surface of the second conductive type semiconductor layer.

In some embodiments, the current blocking layer may have a sloped side. The inclination angle of the side surface is greater than or equal to 30 degrees and less than or equal to 60 degrees. This facilitates current spreading or diffusion in the sidewall regions of the current blocking layer.

In some embodiments, the current blocking layer has a thickness between 500 and 5000 a.

In some embodiments, the current blocking layer may be a reflective current blocking layer. The reflection-type current blocking layer can be beneficial to the transverse extension of current, and can reduce light absorption to improve the light emitting efficiency of the light emitting diode chip.

In some embodiments, the current spreading layer has a thickness between 300 and 2500 a. In the current spreading layer, a thickness of the second sub-current spreading layer is equal to or greater than a thickness of the first sub-current spreading layer.

In some embodiments, in the current spreading layer, a refractive index of the first sub-current spreading layer is greater than a refractive index of the second sub-current spreading layer.

In some embodiments, the current spreading layer may form a plurality of current spreading layer coverage regions over the second conductive type semiconductor layer. The current spreading layer coverage areas at least comprise: the first coverage area is an area above the current blocking layer; the second covering area is a side wall area of the current blocking layer; and a third capping region that is a region of the upper surface of the second conductive type semiconductor layer away from the current blocking layer. In the coverage areas, the thickness of the current spreading layer of the first coverage area is larger than or equal to that of the current spreading layer of the second coverage area and is larger than or equal to that of the current spreading layer of the third coverage area.

In some embodiments, the current spreading layer is a transparent conductive layer, and may be made of a transparent conductive oxide containing at least ITO and a complex multi-component compound thereof. In one embodiment, the first sub-current spreading layer in the current spreading layer may be a transparent conductive layer containing at least ITO. In another embodiment, the first sub-current spreading layer and the second sub-current spreading layer may be transparent conductive layers simultaneously containing ITO. The materials of the first sub-current spreading layer and the second sub-current spreading layer can be the same or not completely the same.

In some embodiments, the light emitting diode chip may further include: a first electrode on the upper surface of the first conductive type semiconductor layer and electrically connected to the first conductive type semiconductor layer; the second electrode is positioned on the upper surface of the current expansion layer and is electrically connected with the second conductive type semiconductor layer; and at least one insulating layer formed on the current spreading layer and at least covering the epitaxial structure, the second sub-current spreading layer, the upper surfaces and the side wall regions of the first electrode and the second electrode.

In some embodiments, a projection of the second electrode towards the epitaxial structure is located within the current blocking layer. It is understood that the area of the second electrode is smaller than the area of the current blocking layer when projected towards the epitaxial structure.

In some embodiments, the thickness of the second sub-current spreading layer gradually increases in a step shape from the center of the second electrode to the outside. Therefore, current can be favorably expanded to the edge of the epitaxial structure and the edge of the second conductive type semiconductor layer, and the light emitting efficiency of the edge of the chip is improved.

In some embodiments, the current spreading layer may be a single layer structure or a multi-layer structure. The current spreading layer covers the current blocking layer and at least a portion of the second conductive type semiconductor layer, and a plurality of current spreading layer covering regions are formed over the second conductive type semiconductor layer. The current spreading layer coverage areas at least comprise: the first coverage area is an area above the current blocking layer; the second covering area is a side wall area of the current blocking layer; and a third capping region that is a region of the upper surface of the second conductive type semiconductor layer away from the current blocking layer. In the coverage areas, the thickness of the current spreading layer of the second coverage area is greater than or equal to 80% of the thickness of the current spreading layer of the third coverage area. Further, in some embodiments, the current blocking layer may have a sloped side. The inclination angle of the side face is more than or equal to 30 degrees and less than or equal to 40 degrees. This allows the sidewall region of the current blocking layer to have a current spreading layer of sufficient thickness to facilitate current spreading or diffusion in that region.

To achieve at least one of the advantages or other advantages, an embodiment of the utility model provides a light emitting module, which is made of the light emitting diode chip.

To achieve at least one of the above advantages or other advantages, an embodiment of the present invention provides a light emitting or display device, which is manufactured by using the light emitting diode chip as described above.

Compared with the prior art, the light-emitting diode chip provided by the utility model at least has the following advantages:

1. the first sub-current expansion layer at least containing ITO forms complete cladding on the surface and the side wall of the current blocking layer, so that the current expansion layer with enough thickness is ensured in the side wall area of the current blocking layer, the expansion effect of current in the side wall area of the current blocking layer is favorably improved, and the probability of ESD failure is reduced.

2. The current spreading layer is structurally arranged, so that current is more effectively and uniformly distributed in the second conductive type semiconductor layer, and the requirements of high light transmittance and high stability are met, so that the luminous efficiency and the service life of the light-emitting diode chip are improved, and the performance of a device is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

Fig. 1A is a schematic cross-sectional view of a light emitting diode chip according to a first embodiment of the utility model;

FIG. 1B is an enlarged view of area A of FIG. 1A;

FIG. 2 is a schematic cross-sectional view of a first variant embodiment of the LED chip shown in FIG. 1;

FIG. 3 is a schematic cross-sectional view of a second variant embodiment of the LED chip shown in FIG. 1;

fig. 4 is a schematic cross-sectional view of a light emitting diode chip according to a second embodiment of the present invention;

fig. 5 is a schematic top view of an led chip according to an embodiment of the utility model; and

fig. 6 is a schematic top view of a light emitting diode chip according to another embodiment of the utility model.

Reference numerals:

1-light emitting diode chip 10-substrate 20-epitaxial structure

21-first conductivity type semiconductor layer 22-active layer 23-first conductivity type semiconductor layer

30-current blocking layer 31-side 40-current spreading layer

41-first sub-current spreading layer 42-second sub-current spreading layer 50-first electrode

60-second electrode 70-insulating layer a 1-angle

M1-first coverage area M2-second coverage area M3-third coverage area

H. H1, H2, H3-thickness 411-protrusions

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations and positional relationships based on those shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or component in question must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be taken as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. In addition, the term "comprises" and any variations thereof mean "including at least".

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integrally formed connection; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Referring to fig. 1A, fig. 1A is a schematic cross-sectional view of a light emitting diode chip according to a first embodiment of the utility model. To achieve at least one of the advantages or other advantages, an embodiment of the utility model provides a light emitting diode chip 1, which may include at least a substrate 10, an epitaxial structure 20, a current blocking layer 30, and a current spreading layer 40. The epitaxial structure 20 includes a first conductive type semiconductor layer 21, a light emitting layer 22 (or an active layer 22, an active layer 22), and a second conductive type semiconductor layer 23 sequentially stacked on the substrate 10 along a stacking direction. The current blocking layer 30 is positioned on the second conductive type semiconductor layer 23, and the current spreading layer 40 is formed over the current blocking layer 30 and wraps the current blocking layer 30.

The substrate 10 may be an insulating substrate, and preferably may be made of a transparent material or a translucent material or a non-transparent material. In the illustrated embodiment, the substrate 10 is sapphire (Al)₂O₃) A substrate. In some embodiments, the substrate 10 may be a patterned sapphire substrate, but is not limited thereto. The substrate 10 may also be made of a conductive or semiconductor material. For example, the substrate 10 may be silicon carbide (SiC), silicon (Si), magnesium aluminum oxide (MgAl)₂O₄) Magnesium oxide (MgO), lithium aluminum oxide (LiAlO)₂) Aluminum gallium oxide (LiGaO)₂) And gallium nitride (GaN). In some embodiments, the substrate 10 may be thinned or removed to form a thin film type LED chip.

In some embodiments, the upper surface of the substrate 10 may have a patterned structure (not shown in the drawings), which may improve external light extraction efficiency and crystallinity of the epitaxial structure 20. Alternatively, the upper surface patterning structure of the substrate 10 may be formed in various shapes, such as a mesa, a cone, a triangular pyramid, a hexagonal pyramid, a cone-like, a triangular pyramid-like, or a hexagonal pyramid-like, etc. In addition, the patterned structure of the upper surface of the substrate 10 may be selectively formed at the respective regions or may be omitted. The material of the patterned structure may be the same as the material of the substrate 10 or may be different from the material of the substrate 10. For example, the material of the patterned structure is selected to have a refractive index lower than that of the substrate 10 to facilitate light extraction, and may be SiO₂And the like.

In this specification, the upper and lower positions are defined by the position of the substrate 10. It is assumed that the direction close to the substrate 10 is downward and the direction away from the substrate 10 is upward. The upper and lower position settings in this specification are only for describing the positional relationship of the respective members in the illustrated embodiments, and do not represent an indication or suggestion that they must have a specific orientation.

The epitaxial structure 20 may be formed on the substrate 10 by Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), hydride vapor deposition (HVPE), Physical Vapor Deposition (PVD), ion plating, or the like. Specifically, the substrate 10 has opposite upper and lower surfaces, and the epitaxial structure 20 is formed on the upper surface of the substrate 10. The first conductive type semiconductor layer 21 may be grown from the upper surface of the substrate 10, and the light emitting layer 22 (or the active layer 22 and the active layer 22) and the second conductive type semiconductor layer 23 are sequentially stacked and grown on the upper surface of the first conductive type semiconductor layer 21. In other embodiments, the epitaxial structure 20 may also be formed on the substrate 10 by a bonding layer, which is preferably a light-transmissive material.

The epitaxial structure 20 may provide light of a particular central emission wavelength, such as blue, green or red light or violet or ultraviolet light. The example of the epitaxial structure 20 providing blue light is illustrated in the illustrated embodiment. In the illustrated embodiment, the first conductive type semiconductor layer 21 in the epitaxial structure 20 is an N-type semiconductor layer, and can supply electrons to the light emitting layer 22 under the power supply. In some embodiments, the N-type semiconductor layer in the first conductive type semiconductor layer 21 includes an N-type doped nitride layer. The N-type doped nitride layer may include one or more N-type impurities of a group IV element. The N-type impurity may be one of Si, Ge, Sn, or a combination thereof.

In some embodiments, the light emitting layer 22 (or the active layer 22, the active layer 22) may be a multi-quantum well (MQWs) structure in which quantum well layers and quantum barrier layers are alternately stacked. The light emitting layer 22 may be a single quantum well structure or a multiple quantum well structure. The quantum barrier layer may be a GaN layer or an AlGaN layer. In some embodiments, the light emitting layer 22 may include a multi-quantum well structure of GaN/AlGaN, InAlGaN/InAlGaN, or InGaN/AlGaN. To improve the light emitting efficiency of the light emitting layer 22, this may be accomplished by varying the depth of the quantum wells, the number of layers, the thickness, and/or other characteristics of the pairs of quantum wells and quantum barriers in the light emitting layer 22.

In the illustrated embodiment, the second conductive type semiconductor layer 23 in the epitaxial structure 20 is a P-type semiconductor layer, and holes can be provided to the light emitting layer 22 by a power supply. In some embodiments, the P-type semiconductor layer in the second conductive type semiconductor layer 23 includes a P-type doped nitride layer. The P-type doped nitride layer may include one or more P-type impurities of a group II element. The P-type impurity can Be one of Mg, Zn, Be or their combination. The second conductive type semiconductor layer 23 may have a single-layer structure or a multi-layer structure having different compositions. The arrangement of the epitaxial structure 20 is not limited thereto, and other kinds of epitaxial structures 20 may be selected according to actual requirements.

In some embodiments, the light emitting diode chip 1 may have a buffer layer (not shown) between the substrate 10 and the epitaxial structure 20 to reduce lattice mismatch between the substrate 10 and the first conductive type semiconductor layer 21. In some embodiments, the buffer layer may include an unintentionally doped GaN layer (u-GaN) or an unintentionally doped AlGaN layer (u-AlGaN).

The buffer layer may be a single layer or a plurality of layers. The buffer layer may be formed by metal organic chemical vapor Deposition, molecular beam epitaxy, or Physical Vapor Deposition (PVD). The physical vapor deposition may include sputtering (sputter) method, such as reactive sputtering, or evaporation; such as electron beam evaporation or thermal evaporation. In one embodiment, the buffer layer may include an aluminum nitride (AlN) buffer layer formed on the substrate 10 having the patterned structure surface, and be formed by a sputtering method. The sputtering method can form a dense buffer layer with high uniformity, so that an aluminum nitride buffer layer can be deposited on the surface of the patterned structure of the substrate 10.

The light emitting diode chip 1 may further include a first electrode 50 and a second electrode 60, which are separated from each other. As shown in fig. 1A, the first electrode 50 is an N electrode, and the second electrode 60 is a P electrode. In some embodiments, the P-electrode may be formed of one or more electrode layer stacks of chromium, nickel, aluminum, titanium, platinum, gold, palladium, silver, and the like. The N-electrode may be formed by stacking one or more electrode layers of chromium, nickel, aluminum, titanium, platinum, gold, palladium, silver, and the like. The first electrode 50 is disposed on the upper surface of the first conductive type semiconductor layer 21 and electrically connected to the first conductive type semiconductor layer 21. The second electrode 60 is disposed on the upper surface of the current spreading layer 40 and electrically connected to the second conductive type semiconductor layer 23. As will be understood in conjunction with the drawings, the current blocking layer 30 and the current spreading layer 40 are interposed between the second conductive type semiconductor layer 23 and the second electrode 60.

Referring again to FIG. 1A, the LEDThe current blocking layer 30 in the chip 1 is formed on a portion of the upper surface of the second conductivity-type semiconductor layer 23 of the epitaxial structure 20, and is located right below the second electrode 60(P electrode in the figure). The current blocking layer 30 is an insulating material layer, and may be SiO₂、SiC、Si₃N₄、AbO_3、TiO₂Etc. or a different combination thereof. The current blocking layer 30 may be used to block a current injected from the P electrode 60 into the light emitting diode chip 1 from directly and vertically entering the second conductive type semiconductor layer 23, so as to avoid a crowding or aggregation phenomenon of the current below the P electrode 60, promote the current to spread in the second conductive type semiconductor layer 23, and achieve uniform distribution of the current.

The bottom (or lower surface) of the current blocking layer 30 needs to have high adhesion to form good adhesion or adhesion with the upper surface of the second conductive type semiconductor layer 23. For example, if a portion of the current blocking layer 30 between the current blocking layer 30 and the second conductive type semiconductor layer 23 falls off before the current spreading layer 40 is plated, the current spreading layer 40 at the fall-off portion directly contacts the second conductive type semiconductor layer 23, which affects the spreading of current to a region away from the second electrode 60(P electrode), so that the current spreading effect of the region of the second conductive type semiconductor layer 23 is not good, and the light emitting efficiency is reduced. In order to enhance adhesion between the bottom (or lower surface) of the current blocking layer 30 and the upper surface of the second conductive type semiconductor layer 23, the material of the current blocking layer 30 may be Al₂O₃. In some embodiments, the bottom (or lower surface) of the current blocking layer 30 may be coated with an adhesion promoter to improve adhesion between the current blocking layer 30 and the second conductive type semiconductor layer 23.

In some embodiments, the current blocking layer 30 may be formed of SiO₂And Ti₃O₅Alternatively grown Distributed Bragg Reflector (DBR) structures, and a trench structure is formed at the current blocking layer 30 using an Inductively Coupled Plasma (ICP) etching technique. At this time, the current blocking layer 30 is a reflective current blocking layer structure, which can improve the current diffusion of the large-sized led chip 1, and the DBR can reduce the absorption of light to effectively increase the light emissionThe light extraction efficiency of the photodiode chip 1.

In a preferred embodiment, the current blocking layer 30 may have a slanted side 31. The angle a1 formed by the inclined side surface 31 facing the current blocking layer 30 is 30 ° or more and 60 ° or less. The current blocking layer 30 is designed to have a small inclination angle structure, so that the current design of the light emitting diode chip 1 can be improved, the light loss caused by light absorption and light blocking of the metal of the P electrode 60 is reduced, the light emitting angle and the light emitting efficiency of light rays in the light emitting diode chip 1 are favorably improved, and the brightness of the light emitting diode chip 1 is improved. In addition, the current blocking layer 30 is designed to have a small inclination angle, which is beneficial to improving the ESD resistance of the led chip 1, and further improving the reliability of the led chip 1.

When the angle a1 is greater than 60 °, if the current spreading layer 40 is a single-layer structure, the ratio of the thickness of the current spreading layer 40 covered by the sidewall region of the current blocking layer 30 to the thickness of the current spreading layer 40 directly covered by the upper surface of the second conductive type semiconductor layer 23 (the region without the current blocking layer 30) is less than 60%, which is not favorable for the coverage of the current spreading layer 40 on the sidewall of the current blocking layer 30, and is liable to cause EOS (electrical overstress or electrical overstress) or ESD (electrostatic discharge or electrostatic discharge) failure.

When the angle a1 is 30 ° to 40 °, if the current spreading layer 40 is a single-layer structure, the ratio of the thickness of the current spreading layer 40 (H2 in the figure) covered on the sidewall of the current blocking layer 30 to the thickness of the current spreading layer 40 (H3 in the figure) directly covered on the upper surface (the region without the current blocking layer 30) of the second conductive type semiconductor layer 23 is about 80% to 90%, which can prevent ESD pop.

The thickness H of the current blocking layer 30 is between 500 and 5000. The main function of the current blocking layer 30 is to make the carriers (current carriers) injected from the second electrode 60(P electrode in the figure) and the current spreading layer 40 have better lateral diffusion effect, and avoid current congestion caused by direct injection of the carriers into the second conductivity type semiconductor layer 23. On the other hand, the current blocking layer 30 may be formed like an ODR reflective structure (an omnidirectional mirror structure) with a metal so that light generated from the quantum well layer (the light emitting layer 22) and directed to the metal has a high reflectance and the light may be emitted from the other surface after being reflected from the side surface or multiple times. When the thickness of the current blocking layer 30 is too thin, the ODR formed with the metal has a low reflectivity, and has a high reflectivity when it reaches a certain thickness. When the thickness of the current blocking layer 30 exceeds a certain value, the reflectivity remains almost unchanged. In addition, the effect of transferring carriers at the sidewall of the current blocking layer 30 is less than that at the upper surface of the second conductive type semiconductor layer 23. When the thickness of the current blocking layer 30 is too thick, the area ratio of the sidewall region of the current blocking layer 30 becomes large, which is disadvantageous to the transmission of current, and is liable to cause deterioration of EOS or ESD.

In some embodiments, the current blocking layer 30 may also be disposed on the upper surface of the first conductive type semiconductor layer 21 and the first electrode 50 (in the figure, the N electrode) in the epitaxial structure 20, so as to facilitate the current spreading and uniform distribution in the area of the first electrode 50.

The current spreading layer 40 may be a single-layer structure or a multi-layer structure. In one embodiment, the current spreading layer 40 includes at least a first sub-current spreading layer 41 and a second sub-current spreading layer 42, which are sequentially stacked on the current blocking layer 30. Specifically, the first sub-current spreading layer 41 is formed on the current blocking layer 30, and covers at least the upper surface and the sidewall region of the current blocking layer 30 and a portion of the upper surface of the second conductive type semiconductor layer 23. The second sub-current spreading layer 42 is formed on the first sub-current spreading layer 41, and covers at least an upper surface and a sidewall region of the first sub-current spreading layer 41 and a portion of an upper surface of the second conductive type semiconductor layer 23. The current spreading layer 40 is mainly used for current spreading or diffusion, and prevents a phenomenon in which current injected from the P-electrode 60 into the light emitting diode chip 1 is concentrated in one region or a plurality of regions of the second conductive type semiconductor layer 23, so that current can be effectively and uniformly distributed in the second conductive type semiconductor layer 23.

It is further noted that the first sub-current spreading layer 41 at least covers the upper surface of the second conductivity type semiconductor layer 23 adjacent to two sides of the current blocking layer 30 to directly form a tight and effective cladding on the current blocking layer 30, so that the sidewall area of the current blocking layer 30 can cover the current spreading layer with a sufficient thickness, which is beneficial for the current spreading of the sidewall area of the current blocking layer 30.

Further, the current blocking layer 30 is covered with the first sub-current spreading layer 41 of the current spreading layer 40 except for a region in contact with the second conductive type semiconductor layer 23. In this way, when the current or carriers (current carriers) injected into the light emitting diode chip 1 from the second electrode 60(P electrode in the figure) are located in the upper surface region of the second conductivity-type semiconductor layer 23, the current or carriers are spread or diffused to the edge of the upper surface of the second conductivity-type semiconductor layer 23 as much as possible under the combined action of the current blocking layer 30 and the first sub-current spreading layer 41, so that the current is more uniformly distributed in the second conductivity-type semiconductor layer 23, and the risk of electrostatic discharge (ESD) caused by the current collection effect is reduced.

The current spreading layer 40 may be a transparent conductive film containing a transparent conductive oxide and a complex multi-component compound thereof. The transparent conductive oxide and its compound multi-component compound may be ITO, ZnO, ZITO, ZIO, GIO, ZTO, FTO, AZO, GZO, ATO, GaO, IZO, GTO, In₄Sn₃O₁₂One or a different combination of NiAu, etc. The current spreading layer 40 may be a transparent conductive layer containing ITO (indium tin oxide semiconductor transparent conductive film) formed by evaporation or sputtering, or may be selected or contain other materials, such as ZnO, graphene, and the like. The deposition method of the current spreading layer 40 may be sputtering, evaporation, spray pyrolysis or chemical vapor deposition. The material of the first sub-current spreading layer 41 and the second sub-current spreading layer 42 may be the same or not completely the same.

In addition, in some embodiments, a step of forming a patterned rough structure on the surface of the current spreading layer 40 may be further included, and the patterned rough structure may reduce the amount of light absorbed by the current spreading layer 40, so as to further improve the light extraction efficiency of the current spreading layer 40.

In some embodiments, the current spreading layer 40 is a transparent conductive layer and contains at least ITO. For example, the first sub-current spreading layer 41 of the current spreading layer 40 includes at least ITO to facilitate the transparent conductive layer to spread or diffuse the current injected into the second conductive type semiconductor layer 23 while having high light transmittance. At this time, the first sub-current spreading layer 41 has better thermal stability and can form a good contact with the second conductive type semiconductor layer 23. The second sub-current spreading layer 42 may be a transparent layer containing metal, or a doped ZnO, AZO transparent thin film layer, which has good chemical stability, high light transmittance, etc. The second sub-current spreading layer 42 can protect the first sub-current spreading layer 41 and realize current spreading, and can also improve the light penetration rate of the light emitting diode chip 1 and improve the light emitting performance. In another embodiment, the first sub-current spreading layer 41 and the second sub-current spreading layer 42 in the current spreading layer 40 may simultaneously contain ITO, so that the current injected into the second conductive type semiconductor layer 23 is spread more uniformly and spread more widely. In other words, the current spreading layer 40 is disposed to spread the current toward the edge or the periphery of the chip, thereby improving the light emitting efficiency of the chip.

In some embodiments, the thickness of the second sub current spreading layer 42 is equal to or greater than the thickness of the first sub current spreading layer 41. With such an arrangement, after the current spreading layer 40 is subjected to processes such as etching, the second sub-current spreading layer 42 can be ensured to have a sufficient thickness to cover and protect the first sub-current spreading layer 41, and the region of the upper surface of the second conductive type semiconductor layer 23 away from the current blocking layer 30 can be covered with the second sub-current spreading layer 42 having a certain thickness to realize current spreading in these regions.

The current spreading layer 40 is too thin to affect the current spreading effect, and too thick to affect the light transmission performance. In view of this, in a preferred embodiment, the thickness of the current spreading layer 40 is between 300 and 2500 a. In the illustrated example, the thickness of the current spreading layer 40 mainly refers to the total thickness of the first sub-current spreading layer 41 and the second sub-current spreading layer 42 interposed between the current blocking layer 30 and the second electrode 60. In this way, the first sub-current spreading layer 41 may form a complete cladding on the upper surface and the sidewall region of the current blocking layer 30, so that the sidewall region of the current blocking layer 30 has a current spreading layer with a sufficient thickness to enhance the spreading effect or diffusion uniformity of the current at the sidewall region of the current blocking layer 30, and reduce the current concentration at the region. Meanwhile, the second sub-current spreading layer 42 may not only protect the first sub-current spreading layer 41 but also spread and uniformly distribute current in other regions of the upper surface of the second conductive type semiconductor layer 23.

The thickness of the current spreading layer 40 can be varied according to different conditions, such as the voltage and brightness requirements of the product, to form chips with different brightness and performance. The thicker the thickness of the current spreading layer 40, the lower the forward voltage of the chip, and the more obvious the light absorption effect of the current spreading layer 40 at this time, the lower the brightness of the chip. The thinner the thickness of the current spreading layer 40 is, the higher the forward voltage of the chip is, and at this time, the smaller the light absorption effect of the current spreading layer 40 is, the higher the brightness of the chip is.

In some embodiments, the current spreading layer 40 is a composite structure formed by an upper layer and a lower layer, the first sub-current spreading layer 41 is located below the second sub-current spreading layer 42, and the refractive index of the first sub-current spreading layer 41 is greater than the refractive index of the second sub-current spreading layer 42. Thus, the light escaping efficiency can be improved, and the light extracting effect of the light emitting diode chip 1 is increased. Specifically, the first sub-current spreading layer 41 mainly plays a role of current spreading, and the second sub-current spreading layer 42 can cancel interference of two rows of reflected light, so that the whole reflected light is weakened or disappeared, and transmitted light is enhanced to play an anti-reflection effect. The arrangement of the gradient change of the refractive index in the current spreading layer 40 can ensure the electrical conductivity, and can also reduce the refractive index difference between the interface in the light emitting diode chip 1 and the air, thereby increasing the critical angle of the light emitted from the light emitting layer 22 and emitted from the inside of the light emitting diode chip 1 to the air, improving the light extraction efficiency of the light emitting diode chip 1, and improving the brightness of the light emitting diode chip 1.

Referring to fig. 1B in conjunction with fig. 1A, fig. 1B is an enlarged schematic view of a region a in fig. 1A. As shown in fig. 1B, the current spreading layer 40 forms a plurality of current spreading layer coverage areas over the second conductive type semiconductor layer 23 in the epitaxial structure 20. The current spreading layer coverage areas may be divided into at least a first coverage area M1, a second coverage area M2, and a third coverage area M3. The first coverage area M1 is an upper area of the current blocking layer 30. As will be understood in conjunction with the illustration of the drawing, the first coverage area M1 is an area between the upper surface of the current blocking layer 30 to the lower surface of the second electrode 60. The second coverage area M2 is a sidewall area of the current blocking layer 30. As will be understood in conjunction with the illustrated example, the second coverage area M2 refers to an area where the inclined side surfaces 31 on both sides of the current blocking layer 30 face the current spreading layer 40. The third cap region M3 is a region of the upper surface of the second conductive type semiconductor layer 23 in the epitaxial structure 20 away from the current blocking layer 30. As will be understood in conjunction with the illustration of the drawing, the third coverage area M3 refers to an area of the epitaxial structure 20 where the upper surface of the second conductive type semiconductor layer 23 is mainly covered by the second sub-current spreading layer 42, except for the other area covered by the current blocking layer 30.

In the plurality of current spreading layer coverage areas formed by the current spreading layer 40, the current spreading layer thickness H1 in the first coverage area M1 is equal to or greater than the current spreading layer thickness H2 in the second coverage area M2 is equal to or greater than the current spreading layer thickness H3 in the third coverage area M3. When the current spreading layer 40 is formed on the entire region of the upper surface of the second conductive type semiconductor layer 23, it exhibits different thickness distributions such that the thickness of the current spreading layer on the sidewall of the current blocking layer 30 on the second conductive type semiconductor layer 23 is equal to or greater than the thickness of the current spreading layer 40 at the other upper surface of the second conductive type semiconductor layer 23 (H2 ≧ H3 in the drawing). Thus, the current spreading layer 40 formed finally and covering the sidewall of the current blocking layer 30 after the current blocking layer 30 is subjected to processes such as etching and the like has a sufficient thickness, so that the current spreading or diffusion in the sidewall area of the current blocking layer 30 is promoted, and the probability of ESD failure is reduced.

Further explaining, as understood in connection with the illustration of the drawing, the thickness H1 of the current spreading layer in the first coverage area M1 is the total thickness of the first sub-current spreading layer 41 and the second sub-current spreading layer 42 between the upper surface of the current blocking layer 30 to the lower surface of the second electrode 60. The current spreading layer thickness H2 in the second coverage area M2 is the vertical distance of the inclined side face 31 of the current blocking layer 30 toward the surface of the sidewall of the second sub-current spreading layer 42 in the direction perpendicular to the side face 31. In the second coverage area M2, the sidewall of the current blocking layer 30 is completely covered by the first sub-current spreading layer 41, and then the first sub-current spreading layer 41 is covered and protected by the second sub-current spreading layer 42. In the illustrated preferred embodiment, the current spreading layer thickness H3 in the third coverage area M3 is the thickness of the second sub-current spreading layer 42 directly formed and covered on the upper surface of the second conductive type semiconductor layer 23. Namely, H1 ≧ H2 ≧ H3 in the illustrated example.

In some embodiments, when a ratio of a thickness (e.g., H2) of the current spreading layer 40 covered by the sidewall region of the current blocking layer 30 to a thickness (e.g., H3) of the current spreading layer 40 directly covered by the upper surface (the region without the current blocking layer 30) of the second conductive type semiconductor layer 23 is greater than or equal to 80% (e.g., H2 ≧ H3 × 80%), after the process, the current spreading layer 40 covered by the sidewall region of the current blocking layer 30 has a sufficient thickness to facilitate spreading or diffusion of current or carriers.

When the light emitting diode chip 1 is subjected to electrostatic discharge, more carriers with higher concentration are collected at the position with the weakest electric conduction capability in the whole structure, and a large amount of heat is generated to cause the failure of the light emitting diode chip 1. In the vicinity of the current blocking layer 30, when the current spreading layer thickness (H2 at M2 in the drawing) of the side wall region of the current blocking layer 30 is smaller than the current spreading layer thickness (H3 at M3 in the drawing) of the upper surface of the second conductivity-type semiconductor layer 23, the problem of failure of the light emitting diode chip 1 is easily caused. In view of this, the arrangement of H2 ≧ H3 in the illustrated example can increase the thickness of the current spreading layer in the sidewall region of the current blocking layer 30, and improve the carrier transport capability in this region, thereby improving the ESD resistance of the entire light emitting diode chip 1.

In some embodiments, the current spreading layer 40 may be a three-layer structure and more. When the current spreading layer 40 is formed on the entire upper surface of the second conductive type semiconductor layer 23, the current spreading layer may have different thickness distributions such that the thickness of the current spreading layer on the sidewall of the current blocking layer 30 on the second conductive type semiconductor layer 23 is equal to or greater than the thickness of the current spreading layer 40 on the other upper surface of the second conductive type semiconductor layer 23 (H2 ≧ H3 in the drawing). After the current blocking layer 30 is manufactured, the current spreading layer finally covering the side wall of the current blocking layer 30 has enough thickness, so that current spreading or diffusion of the side wall area of the current blocking layer 30 is facilitated, and the probability of ESD failure is reduced.

Referring to fig. 2 in conjunction with fig. 1A, fig. 2 is a schematic cross-sectional view of a first variant embodiment of the led chip shown in fig. 1A. As shown in fig. 2, in some embodiments, the first sub-current spreading layer 41 may directly cover other regions of the upper surface of the second conductive type semiconductor layer 23 in addition to the upper surface and the sidewall region of the current blocking layer 30. As such, the current distribution in second conductivity-type semiconductor layer 23 can be made more uniform. At this time, the current spreading layer thickness H3 in the third coverage area M3 refers to the thickness of the first sub-current spreading layer 41 and the second sub-current spreading layer 42 directly formed to cover the upper surface of the second conductive type semiconductor layer 23. It is understood that in the modification of fig. 2, the first coverage area M1, the second coverage area M2 and the third coverage area M3 all include the first sub-current spreading layer 41 and the second sub-current spreading layer 42, but the thickness of the current spreading layer is different in different coverage areas.

Referring to fig. 3 in conjunction with fig. 2, fig. 3 is a schematic cross-sectional view of a second variation embodiment of the light emitting diode chip shown in fig. 1A. The first sub-current spreading layer 41 of the current spreading layer 40 on the upper surface of the second conductive type semiconductor layer 23 may have a plurality of protrusions 411. The protrusions 411 may be arranged periodically at equal intervals or continuously at unequal intervals. The surface of the first sub-current spreading layer 41 is exposed between the adjacent protrusions 411. The top view shape of the protrusion 411 may be a regular shape or an irregular pattern such as a circle, a square, or the like. The current entering the first sub-current spreading layer 41 can be diffused toward the sidewall of the protrusion 411, so that the direct linear movement of the current injected from the second electrode 60 toward the first electrode 50 is slowed, and the current spreading effect of the current spreading layer 40 is improved.

In some embodiments, as shown in fig. 1A, a projection of the second electrode 60 (in the figure, the P electrode) toward the epitaxial structure 20 is located within the current blocking layer 30. As will be understood from the drawings, the edge line of the second electrode 60 is located inside the edge line of the current blocking layer 30 when projected toward the epitaxial structure 20. It can be understood that the edge of the lower surface of the second electrode 60 has a certain distance from the edge of the lower surface of the current blocking layer 30. The current injected from the second electrode 60 into the light emitting diode chip 1 can be rapidly dispersed and spread to the periphery when proceeding to the upper side of the current blocking layer 30, and is prevented from being concentrated right below the second electrode 60, so that the current is more uniformly and reasonably distributed in the second conductive type semiconductor layer 23.

In some embodiments, the thickness of the second sub-current spreading layer 42 in the current spreading layer 40 gradually increases in a step shape toward the outside with the second electrode 60 as the center. Carriers (current carriers) are injected from the second electrode 60, and the distribution of carriers is reduced by the influence of mobility and the mobility effect in a region farther from the second electrode 60. The current spreading layer 4 is arranged in a structure that the current spreading layer gradually increases in a step shape towards the outside by taking the second electrode 60 as the center, so that the edge position of the chip far away from the second electrode 60 has more carrier distribution, the injection effect of carriers of quantum well layers (active layer 22/light emitting layer 22) at the edge of the chip is increased, and the light emitting efficiency of the edge region of the chip is improved.

Referring to fig. 4 in conjunction with fig. 1A, fig. 4 is a schematic cross-sectional view of a light emitting diode chip according to a second embodiment of the utility model. In some embodiments, the led chip 1 may further include at least one insulating layer 70 formed on the current spreading layer 40 to enhance the overall insulating performance of the led chip 1. The insulating layer 70 covers at least a portion of the upper surface and sidewall region of the epitaxial structure 20, the upper surface and sidewall region of the second sub-current spreading layer 42, a portion of the upper surface and sidewall region of the first electrode 50, and a portion of the upper surface and sidewall region of the second electrode 60, so as to cover and insulate these regions.

The material of the insulating layer 70 includes but is not limited to SiO₂、SiN、Al₂O₃And the like. In one embodiment, the insulating layer 70 is SiO₂，SiO₂Has better physical property and chemical stability, and can protect structures such as the current expansion layer 40 and the like. In some embodiments, the insulating layer 70 may be a multilayer film structure in which high-refractive-index dielectric films and low-refractive-index dielectric films are alternately stacked, such as a bragg reflector (DBR). Wherein, the material of the dielectric film with high refractive index can be TiO₂、NB₂O₅、TA₂O₅、HfO₂、ZrO₂Etc.; the material of the low-refractive dielectric film may be SiO₂、MgF₂、Al₂O₅SiON, etc. So configured, the insulating layer 70 may have better photoelectric properties.

Referring to fig. 5 in conjunction with fig. 1A and fig. 4, fig. 5 is a schematic top view of an embodiment of a light emitting diode chip in the present invention. In the example of fig. 5, a current blocking layer 30 is provided in the light emitting diode chip 1 below the first electrode 50 (N electrode in the drawing). In some embodiments, as shown in fig. 5, the light emitting diode chip 1 has several current blocking layers 30 arranged at intervals under the N electrode 50. This arrangement ensures good electrical contact between the N-electrode 50 and the first conductive type semiconductor layer 21 (e.g., N-GaN). On the other hand, the stacked design of the N electrode 50 and the current blocking layer 30 can improve the reflectivity of the light emitting diode chip 1, thereby improving the light emitting efficiency of the light emitting diode chip 1.

As shown in fig. 5, the edge line of the P-electrode 60 (second electrode) is located inside the edge line of the current blocking layer 30. I.e., the area of the P-electrode 60 is smaller than the area of the current blocking layer 30. As will be understood from the drawings, a certain distance is provided between the edge of the farthest end of the P electrode 60 and the edge of the farthest end of the current blocking layer 30, so that carriers injected into the light emitting diode chip 1 from the P electrode 60 can be rapidly dispersed and expanded around when moving to the upper side of the current blocking layer 30, and the carriers are prevented from being concentrated under the P electrode 60, so that the carriers are more uniformly and reasonably distributed in the region of the epitaxial structure 20, and the light emitting efficiency of the light emitting diode chip 1 is improved.

In the example of fig. 5, the first electrode 50 (N electrode in the drawing) or the second electrode 60(P electrode in the drawing) includes a pad electrode and an extension electrode. The pad electrode can be used for electrode wire bonding, and the extension electrode has the function of current spreading or diffusion, so that the current can be more uniformly diffused in the electrode area. In fig. 5, the pad electrode is a block-shaped portion and is substantially circular, and the extension electrode is a strip-shaped portion.

The led chip 1 of fig. 5 is a front-mounted chip. However, without being limited thereto, the light emitting diode chip 1 provided with the current spreading layer 40 may be used for a flip chip, as shown in fig. 6. Therefore, the current spreading effect in the flip chip can be improved, and the overall luminous efficiency of the chip is improved.

To achieve at least one of the advantages or other advantages, an embodiment of the utility model provides a light emitting module, which is manufactured by using the light emitting diode chip 1.

To achieve at least one of the advantages or other advantages, an embodiment of the utility model provides a light emitting or display device, which is manufactured by using the light emitting diode chip 1.

Although terms such as light emitting diode chip, substrate, epitaxial structure, current blocking layer, current spreading layer, transparent conductive layer, insulating layer, etc. are used more often herein, the possibility of using other terms is not excluded. These terms are used merely to more conveniently describe and explain the nature of the present invention; they are to be construed as being without limitation to any additional limitations that may be imposed by the spirit of the present invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the utility model has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A light emitting diode chip, comprising at least:

an epitaxial structure including a first conductive type semiconductor layer, a light emitting layer, and a second conductive type semiconductor layer sequentially stacked;

a current blocking layer on the second conductive type semiconductor layer;

the current spreading layer at least comprises a first sub-current spreading layer and a second sub-current spreading layer which are sequentially stacked on the current blocking layer;

wherein the first sub-current spreading layer is formed on the current blocking layer and covers at least an upper surface and a sidewall region of the current blocking layer and a portion of an upper surface of the second conductive type semiconductor layer; the second sub-current spreading layer is formed on the first sub-current spreading layer and covers at least an upper surface and a sidewall region of the first sub-current spreading layer and a portion of an upper surface of the second conductive type semiconductor layer.

2. The light-emitting diode chip of claim 1, wherein: the current blocking layer is provided with an inclined side face, and the inclination angle of the side face is greater than or equal to 30 degrees and less than or equal to 60 degrees.

3. The light-emitting diode chip of claim 1, wherein: the current blocking layer has a thickness between 500 and 5000 a.

4. The light-emitting diode chip of claim 1, wherein: in the current spreading layer, a thickness of the second sub-current spreading layer is equal to or greater than a thickness of the first sub-current spreading layer.

5. The light-emitting diode chip of claim 1, wherein: the current spreading layer has a thickness between 300 and 2500 a.

6. The light-emitting diode chip of claim 1, wherein: in the current spreading layer, a refractive index of the first sub-current spreading layer is greater than a refractive index of the second sub-current spreading layer.

7. The light-emitting diode chip of claim 1, wherein: the current spreading layer forms a plurality of current spreading layer covering regions over the second conductive type semiconductor layer, including at least:

the first coverage area is an area above the current blocking layer;

the second covering area is a side wall area of the current blocking layer; and

a third coverage area, which is an area where the upper surface of the second conductive type semiconductor layer is far away from the current blocking layer;

wherein a thickness of a current spreading layer of the first coverage area of the plurality of coverage areas is greater than or equal to a thickness of a current spreading layer of the second coverage area and is greater than or equal to a thickness of a current spreading layer of the third coverage area.

8. The light-emitting diode chip of claim 1, wherein: the current spreading layer is a transparent conductive layer and at least contains ITO.

9. The light-emitting diode chip of claim 1, wherein: the light emitting diode chip further includes:

a first electrode on the upper surface of the first conductive type semiconductor layer and electrically connected to the first conductive type semiconductor layer;

the second electrode is positioned on the upper surface of the current expansion layer and is electrically connected with the second conductive type semiconductor layer; and

and the at least one insulating layer is formed on the current expansion layer and at least covers the epitaxial structure, the second sub-current expansion layer, the upper surfaces and the side wall regions of the first electrode and the second electrode.

10. The light-emitting diode chip of claim 9, wherein: the thickness of the second sub-current expansion layer gradually increases in a step shape towards the outside by taking the second electrode as a center.

11. The light-emitting diode chip of claim 1, wherein: the current blocking layer is a reflection-type current blocking layer.

12. A light emitting diode chip, comprising at least:

a current blocking layer on the second conductive type semiconductor layer;

a current spreading layer covering the current blocking layer and at least a portion of the second conductive type semiconductor layer, and forming a plurality of current spreading layer covering regions over the second conductive type semiconductor layer, including at least:

the first coverage area is an area above the current blocking layer;

the second covering area is a side wall area of the current blocking layer; and

wherein a thickness of a current spreading layer of the second coverage area of the plurality of coverage areas is 80% or more of a thickness of a current spreading layer of the third coverage area.

13. The light-emitting diode chip of claim 12, wherein: the current blocking layer is provided with an inclined side face, and the inclination angle of the side face is greater than or equal to 30 degrees and less than or equal to 40 degrees.

14. A light emitting module, characterized in that: use of a light-emitting diode chip as claimed in any of claims 1 to 13.

15. A lighting or display device, characterized by: use of a light-emitting diode chip as claimed in any of claims 1 to 13.