CN114695588A - High-efficiency heterojunction battery structure and preparation method thereof - Google Patents
High-efficiency heterojunction battery structure and preparation method thereof Download PDFInfo
- Publication number
- CN114695588A CN114695588A CN202011643595.4A CN202011643595A CN114695588A CN 114695588 A CN114695588 A CN 114695588A CN 202011643595 A CN202011643595 A CN 202011643595A CN 114695588 A CN114695588 A CN 114695588A
- Authority
- CN
- China
- Prior art keywords
- type doped
- amorphous silicon
- layer
- silicon layer
- cell structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 157
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims abstract description 78
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims description 40
- 230000008021 deposition Effects 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 27
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 21
- 229910052739 hydrogen Inorganic materials 0.000 claims description 21
- 239000001257 hydrogen Substances 0.000 claims description 21
- 238000009832 plasma treatment Methods 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000007650 screen-printing Methods 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- 229910001930 tungsten oxide Inorganic materials 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 230000008094 contradictory effect Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 209
- 230000000694 effects Effects 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 238000010521 absorption reaction Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 description 1
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 description 1
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0725—Multiple junction or tandem solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/074—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a heterojunction with an element of Group IV of the Periodic Table, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Energy (AREA)
- Sustainable Development (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention relates to a high-efficiency heterojunction battery structure and a preparation method thereof, wherein the high-efficiency heterojunction battery structure comprises: an intermediate cell structure provided with an n-type single crystal silicon layer; the positive cell structure comprises a positive intrinsic amorphous silicon layer, a p-type doped hydrogenated silicon oxide layer and a p-type doped amorphous silicon layer which are sequentially stacked; the back cell structure comprises a back intrinsic amorphous silicon layer, an n-type doped hydrogenated silicon oxide layer and an n-type doped amorphous silicon layer which are sequentially stacked in the opposite direction; wherein the thickness ranges of the p-type doped amorphous silicon layer and the n-type doped amorphous silicon layer are both 1-5 nm, and the thickness ranges of the p-type doped hydrogenated silicon oxide layer and the n-type doped hydrogenated silicon oxide layer are both 10-20 nm. Through the arrangement, the problem of low battery conversion efficiency caused by contradictory contradiction between the thickness and the performance of the doped amorphous silicon layer in the existing heterojunction battery structure can be solved.
Description
Technical Field
The invention relates to the technical field of laminated solar cells, in particular to a high-efficiency heterojunction cell structure and a preparation method thereof.
Background
In the current industry, the mass production efficiency of the PERC battery is continuously improved and gradually approaches the limit of the conversion efficiency. Mass production cell conversion efficiency is based on current solar cells with heterojunction structures.
In the existing heterojunction cell structure, the light-facing surface is generally a laminated structure of doped amorphous silicon/intrinsic amorphous silicon layer/silicon substrate, wherein the doped amorphous silicon layer needs to ensure sufficient conductivity and passivation effect. Therefore, the thickness of the doped amorphous silicon layer cannot be too thin, and is generally not less than 20nm, but the parasitic absorption of the doped amorphous silicon layer to light is very large due to the large thickness, that is, the doped amorphous silicon layer can absorb a large part of incident light and cannot be converted into photogenerated current, so that the heterojunction cell produced in mass production in the industry usually shows high open-circuit voltage and low current characteristics.
On the contrary, when the thickness of the amorphous silicon is reduced, the passivation effect of the heterojunction characteristics is greatly reduced, and the resistance is greatly increased, thereby greatly reducing the fill factor and the open circuit voltage of the heterojunction battery.
Therefore, there is a need to improve the structure of the heterojunction cell in the prior art to solve the contradictory problem of the doped amorphous silicon layer, so as to improve the cell conversion efficiency.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a high efficiency heterojunction cell structure and a method for manufacturing the same, which is used to solve the problem of low cell conversion efficiency caused by contradictory properties between the thickness and the performance of an amorphous silicon doped layer in the existing heterojunction cell structure.
In order to achieve one of the above objects, an embodiment of the present invention provides a high-efficiency heterojunction battery structure, including:
the middle battery structure comprises a first surface and a second surface which are oppositely arranged up and down, and an n-type monocrystalline silicon layer is arranged in the middle battery structure;
the front cell structure is stacked on the first surface and comprises a front intrinsic amorphous silicon layer, a p-type doped hydrogenated silicon oxide layer and a p-type doped amorphous silicon layer which are sequentially stacked along the direction far away from the first surface;
the middle cell structure is stacked on the back cell structure, the second surface is attached to the back cell structure, and the back cell structure comprises a back intrinsic amorphous silicon layer, an n-type doped hydrogenated silicon oxide layer and an n-type doped amorphous silicon layer which are sequentially stacked along the direction far away from the second surface;
the thickness ranges of the p-type doped amorphous silicon layer and the n-type doped amorphous silicon layer are both 1-5 nm, and the thickness ranges of the p-type doped hydrogenated silicon oxide layer and the n-type doped hydrogenated silicon oxide layer are both 10-20 nm.
As a further improvement of an embodiment of the present invention, the thickness of each of the p-type doped amorphous silicon layer and the n-type doped amorphous silicon layer is 3nm, and the thickness of each of the p-type doped hydrogenated silicon oxide layer and the n-type doped hydrogenated silicon oxide layer is 12 nm.
As a further improvement of one embodiment of the present invention, the front cell structure further includes a front TCO layer stacked on the p-type doped amorphous silicon layer along a direction away from the first surface; the back cell structure further comprises a back TCO layer stacked on the n-type doped amorphous silicon layer along a direction far away from the second surface.
As a further improvement of an embodiment of the present invention, the front cell structure further includes a front electrode disposed on the front TCO layer; the back cell structure further includes a back electrode disposed on the back TCO layer.
As a further improvement of an embodiment of the present invention, the doping elements of both the p-type doped hydrogenated silicon oxide layer and the p-type doped amorphous silicon layer are one or more of boron, aluminum and gallium; and the doping elements of the n-type doped hydrogenated silicon oxide layer and the n-type doped amorphous silicon layer are phosphorus.
As a further improvement of an embodiment of the present invention, both the front TCO layer and the back TCO layer are metal oxide layers and/or doped composition layers with metal oxide as a main component, and the oxide is one or more of zinc oxide, indium oxide, titanium oxide, and tungsten oxide; the front electrode and the back electrode are made of one or more of gold, silver, copper and aluminum.
An embodiment of the present invention further provides a method for manufacturing a high-efficiency heterojunction battery structure, including the steps of:
step A: texturing is carried out on the silicon wafer, a textured structure with the side length of the pyramid base being 1-10 mu m is prepared, and an n-type monocrystalline silicon layer is formed;
and B: intrinsic amorphous silicon deposition is carried out on the first surface of the n-type monocrystalline silicon layer to form a front intrinsic amorphous silicon layer;
step D: carrying out p-type doped hydrogenated silicon oxide deposition on the front intrinsic amorphous silicon layer to form a p-type doped hydrogenated silicon oxide layer;
step F: depositing p-type doped hydrogenated amorphous silicon on the p-type doped hydrogenated silicon oxide layer to form a p-type doped hydrogenated amorphous silicon layer;
step G: after the heterojunction cell structure is turned over, intrinsic amorphous silicon deposition is carried out on the second surface of the n-type monocrystalline silicon layer to form a back intrinsic amorphous silicon layer; the first surface and the second surface are two surfaces which are arranged oppositely up and down of the n-type monocrystalline silicon layer;
step I: carrying out n-type doped hydrogenated silicon oxide deposition on the back intrinsic amorphous silicon layer to form an n-type doped hydrogenated silicon oxide layer;
step K: and depositing n-type doped hydrogenated amorphous silicon on the n-type doped hydrogenated silicon oxide layer to form an n-type doped hydrogenated amorphous silicon layer.
As a further improvement of an embodiment of the present invention,
prior to step D, the method further comprises:
and C: carrying out first hydrogen plasma treatment on the front intrinsic amorphous silicon layer;
after step D, the method further comprises:
step E: carrying out second hydrogen plasma treatment on the p-type doped hydrogenated silicon oxide layer;
prior to step I, the method further comprises:
step H: carrying out third hydrogen plasma treatment on the back intrinsic amorphous silicon layer;
after step I, the method further comprises:
step J: and performing fourth hydrogen plasma treatment on the n-type doped hydrogenated silicon oxide layer.
As a further improvement of an embodiment of the present invention, after step K, the method further comprises:
step L: and depositing TCO layers on two sides of the heterojunction cell structure to respectively form a front TCO layer and a back TCO layer.
As a further refinement of an embodiment of the present invention, after step L, the method further comprises:
step M: screen printing is carried out on the two sides of the heterojunction battery structure to form a front electrode and a back electrode;
and step N: and curing the heterojunction cell structure.
Compared with the prior art, the invention has the beneficial effects that:
arranging the heterojunction cell structure into a front cell structure, an intermediate cell structure and a back cell structure; the structure of the intermediate cell is kept unchanged from the prior structure, and an n-type monocrystalline silicon layer is still arranged as a substrate;
the front cell structure is stacked on the middle cell structure, and is set to be a laminated structure comprising a front intrinsic amorphous silicon layer, a p-type doped hydrogenated silicon oxide layer and a p-type doped amorphous silicon layer, wherein the thickness of the p-type doped hydrogenated silicon oxide layer is 10-20 nm, and the thickness of the p-type doped amorphous silicon layer is 1-5 nm, so that the p-type doped amorphous silicon layer (the thickness is about 20nm) in the prior art is replaced by a combined structure of the p-type doped hydrogenated silicon oxide layer and the p-type doped amorphous silicon layer;
similarly, the back cell structure is stacked below the middle cell structure, and sequentially stacked with a back intrinsic amorphous silicon layer, an n-type doped hydrogenated silicon oxide layer and an n-type doped amorphous silicon layer along the opposite direction, wherein the thickness of the n-type doped hydrogenated silicon oxide layer is 10-20 nm, and the thickness of the n-type doped amorphous silicon layer is 1-5 nm, so that the combined structure of the n-type doped hydrogenated silicon oxide layer and the n-type doped amorphous silicon layer replaces the n-type doped amorphous silicon layer (the thickness is about 20nm) in the prior art;
through the arrangement, the doped amorphous silicon layer in the existing battery structure is replaced by two layers, wherein one layer is composed of doped hydrogenated silicon oxide; on the premise of ensuring the open-circuit voltage and the fill factor of the heterojunction cell structure, the thickness of the doped amorphous silicon layer is greatly reduced, the parasitic absorption of the doped amorphous silicon layer to light can be greatly reduced, and the short-circuit current of the cell is further improved; therefore, the contradictory problem of the thickness and the performance of the amorphous silicon layer doped in the whole cell structure is solved, and the cell conversion efficiency is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the embodiments or the description of the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic structural diagram of a high efficiency heterojunction cell structure in an embodiment of the invention.
Wherein the reference numbers referred to in the figures are as follows:
the solar cell comprises a front electrode 1, a front TCO layer 2, a p-type doped amorphous silicon layer 3, a p-type doped hydrogenated silicon oxide layer 4, a front intrinsic amorphous silicon layer 5, an n-type monocrystalline silicon layer 6, a first surface 61, a second surface 62, a back intrinsic amorphous silicon layer 7, an n-type doped hydrogenated silicon oxide layer 8, an n-type doped amorphous silicon layer 9, a back TCO layer 10 and a back electrode 11.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail and completely with reference to the following detailed description of the invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments of the present invention, belong to the protection scope of the present invention.
The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
As shown in fig. 1, an embodiment of the present invention provides a high-efficiency heterojunction cell structure, including:
the middle cell structure comprises a first surface 61 and a second surface 62 which are oppositely arranged up and down, and an n-type monocrystalline silicon layer 6 is arranged in the middle cell structure;
the front cell structure is stacked on the first surface 61 and comprises a front intrinsic amorphous silicon layer 5, a p-type doped hydrogenated silicon oxide layer 4 and a p-type doped amorphous silicon layer 3 which are sequentially stacked along the direction far away from the first surface 61;
the middle cell structure is stacked on the back cell structure, the second surface 62 is attached to the back cell structure, and the back cell structure comprises a back intrinsic amorphous silicon layer 7, an n-type doped hydrogenated silicon oxide layer 8 and an n-type doped amorphous silicon layer 9 which are sequentially stacked along the direction far away from the second surface 62;
wherein the thickness ranges of the p-type doped amorphous silicon layer 3 and the n-type doped amorphous silicon layer 9 are both 1-5 nm, and the thickness ranges of the p-type doped hydrogenated silicon oxide layer 4 and the n-type doped hydrogenated silicon oxide layer 8 are both 10-20 nm.
Specifically, the heterojunction cell structure is set into a front cell structure, a middle cell structure and a back cell structure; the structure of the intermediate cell is kept unchanged, and an n-type monocrystalline silicon layer 6 is still arranged as a substrate;
the front cell structure is stacked on the middle cell structure, the front cell structure is set to be a laminated structure comprising a front intrinsic amorphous silicon layer 5, a p-type doped hydrogenated silicon oxide layer 4 and a p-type doped amorphous silicon layer 3, wherein the thickness of the p-type doped hydrogenated silicon oxide layer 4 ranges from 10nm to 20nm, the thickness of the p-type doped amorphous silicon layer 3 ranges from 1 nm to 5nm, and therefore the combined structure of the p-type doped hydrogenated silicon oxide layer 4 and the p-type doped amorphous silicon layer 3 is used for replacing the p-type doped amorphous silicon layer 3 (the thickness is about 20nm) in the prior art;
similarly, the back cell structure is stacked below the middle cell structure, and sequentially stacked with a back intrinsic amorphous silicon layer 7, an n-type doped hydrogenated silicon oxide layer 8 and an n-type doped amorphous silicon layer 9 along the opposite direction, wherein the thickness of the n-type doped hydrogenated silicon oxide layer 8 is 10-20 nm, and the thickness of the n-type doped amorphous silicon layer 9 is 1-5 nm, so that the n-type doped hydrogenated silicon oxide layer 8 and the n-type doped amorphous silicon layer 9 are combined to replace the n-type doped amorphous silicon layer 9 (with the thickness of about 20nm) in the prior art;
through the arrangement, the doped amorphous silicon layer in the existing battery structure is replaced by two layers, wherein one layer is composed of doped hydrogenated silicon oxide; on the premise of ensuring the open-circuit voltage and the fill factor of the heterojunction cell structure, the thickness of the doped amorphous silicon layer is greatly reduced, the parasitic absorption of the doped amorphous silicon layer to light can be greatly reduced, and the short-circuit current of the cell is further improved; therefore, the contradictory problem of the thickness and the performance of the amorphous silicon layer doped in the whole cell structure is solved, and the cell conversion efficiency is greatly improved.
The existing heterojunction cell structure is formed by doping amorphous silicon/intrinsic amorphous silicon/silicon wafers to form carrier selective contact, so that the heterojunction cell has good passivation effect on one hand and can also provide carrier transportation on the other hand. Therefore, the thickness of the doped amorphous silicon layer in the structure has a large requirement, the current mass production of the doped amorphous silicon layer is generally about 20nm, the parasitic absorption of the doped amorphous silicon layer with the thickness to light is very large, and the short-circuit current of the battery can be greatly reduced. Although the industry has tried thinner doped amorphous silicon layers, when their thickness is reduced, on the one hand, the deposition quality is deteriorated and on the other hand, the passivation effect and the carrier transport effect are also deteriorated, i.e. there is an contradictory problem that this trade-off between performance and thickness is difficult to balance.
In practical use, in the heterojunction cell structure of the present embodiment, carriers composed of the impurity amorphous silicon layer/doped hydrogenated silicon oxide layer/intrinsic amorphous silicon layer/silicon wafer are selectively contacted, that is, the impurity amorphous silicon layer in the original structure is replaced by two layers, wherein one layer is composed of doped hydrogenated silicon oxide. Therefore, the thickness of the doped amorphous silicon layer can be greatly reduced to about 3nm, and the absorption of light is also greatly reduced. Therefore, on the premise of ensuring the open-circuit voltage and the fill factor of the heterojunction battery, the short-circuit current density of the battery can be greatly improved, so that the heterojunction battery structure has higher efficiency advantage.
Further, the thickness of both the p-type doped amorphous silicon layer 3 and the n-type doped amorphous silicon layer 9 was 3nm, and the thickness of both the p-type doped hydrogenated silicon oxide layer 4 and the n-type doped hydrogenated silicon oxide layer 8 was 12 nm.
Further, the front cell structure further includes a front TCO layer 2 stacked on the p-type doped amorphous silicon layer 3 along a direction away from the first surface 61; the back cell structure further comprises a back TCO layer 10 stacked on the n-doped amorphous silicon layer 9 in a direction away from the second surface 62.
In practical use, the heterojunction cell structure of this embodiment divides the conventional doped amorphous silicon layer into two layers, one layer is a doped amorphous silicon layer and the other layer is a doped silicon oxide layer. That is, the original battery structure is composed of:
TCO/p-type doped amorphous silicon layer (about 20 nm)/intrinsic amorphous silicon layer/n-type single crystal silicon substrate/intrinsic amorphous silicon layer/n-type doped amorphous silicon layer 9 (about 20nm)/TCO structure
(or an inverted structure/mirror structure: TCO/n-type doped amorphous silicon layer (about 20 nm)/intrinsic amorphous silicon layer/n-type single crystal silicon substrate/intrinsic amorphous silicon layer/p-type doped amorphous silicon layer (about 20nm)/TCO structure) ",
the changes are as follows:
TCO/p-type doped amorphous silicon layer (about 3 nm)/p-type doped hydrogenated silicon oxide layer (about 12 nm)/intrinsic amorphous silicon layer/n-type single crystal silicon substrate/intrinsic amorphous silicon layer/n-type doped hydrogenated silicon oxide layer (about 12 nm)/n-type doped amorphous silicon layer (about 3nm)/TCO structure
(or an inverted structure/mirror structure: TCO/n-type doped amorphous silicon layer (about 3 nm)/n-type doped hydrogenated silicon oxide layer (about 12 nm)/intrinsic amorphous silicon layer/n-type single crystal silicon substrate/intrinsic amorphous silicon layer/p-type doped hydrogenated silicon oxide layer (about 12 nm)/p-type doped amorphous silicon layer (about 3nm)/TCO structure) ".
Therefore, the thickness of the doped amorphous silicon layer with the thickness of about 20nm in the original structure is reduced to about 3nm, the parasitic absorption of the doped amorphous silicon layer to light is greatly reduced, and the short-circuit current of the battery is further improved.
Further, the front cell structure further comprises a front electrode 1 arranged on the front TCO layer 2; the back cell structure further comprises a back electrode 11, which is arranged on the back TCO layer 10.
In practical use, the front surface and the back surface of the heterojunction cell structure are also respectively provided with electrodes for leading out current.
Further, the front TCO layer 2 and the back TCO layer 10 are both metal oxide layers and/or doped composition layers with metal oxides as main components, and the oxides are one or more of zinc oxide, indium oxide, titanium oxide and tungsten oxide; the materials of the front electrode 1 and the back electrode 11 are one or more of gold, silver, copper and aluminum.
In practical use, the TCO layer is a metal oxide layer, or a component layer formed by a combination of a metal oxide and a remainder doping thereof. Among them, the material of the metal oxide is not limited to the above.
In a similar way, the materials of the two electrodes are not limited, and a good conductive effect can be ensured.
Further, the doping elements of the p-type doped hydrogenated silicon oxide layer 4 and the p-type doped amorphous silicon layer 3 are one or more of boron, aluminum and gallium; the doping elements of the n-type doped hydrogenated silicon oxide layer 8 and the n-type doped amorphous silicon layer 9 are phosphorus.
Similarly, the doping elements of the doped hydrogenated silicon oxide layer and the doped amorphous silicon layer are not limited to the above types, and the corresponding functional effects of the functional layers can be ensured.
An embodiment of the present invention further provides a method for manufacturing a high-efficiency heterojunction battery structure, including the steps of:
step A: texturing is carried out on the silicon wafer, a textured structure with the side length of the pyramid base being 1-10 mu m is prepared, and an n-type monocrystalline silicon layer 6 is formed;
and B: intrinsic amorphous silicon deposition is carried out on the first surface 61 of the n-type monocrystalline silicon layer 6 to form a front intrinsic amorphous silicon layer 5;
step D: carrying out p-type doped hydrogenated silicon oxide deposition on the front intrinsic amorphous silicon layer 5 to form a p-type doped hydrogenated silicon oxide layer 4;
step F: depositing p-type doped hydrogenated amorphous silicon on the p-type doped hydrogenated silicon oxide layer 4 to form a p-type doped hydrogenated amorphous silicon layer;
step G: after the heterojunction cell structure is turned over, intrinsic amorphous silicon deposition is carried out on the second surface 62 of the n-type monocrystalline silicon layer 6 to form a back intrinsic amorphous silicon layer 7; wherein, the first surface 61 and the second surface 62 are two surfaces of the n-type monocrystalline silicon layer 6 which are arranged oppositely up and down;
step I: depositing n-type doped hydrogenated silicon oxide on the back intrinsic amorphous silicon layer 7 to form an n-type doped hydrogenated silicon oxide layer 8;
step K: n-type doped hydrogenated amorphous silicon deposition is performed on the n-type doped hydrogenated silicon oxide layer 8 to form an n-type doped hydrogenated amorphous silicon layer.
The preparation method provided by the embodiment of the invention is used for preparing the high-efficiency heterojunction battery structure, and the process implementation steps are as follows:
texturing → front intrinsic amorphous silicon deposition → first hydrogen plasma treatment → p-type hydrogenated silicon oxide deposition → second hydrogen plasma treatment → p-type hydrogenated amorphous silicon deposition → back intrinsic amorphous silicon deposition → third hydrogen plasma treatment → n-type hydrogenated silicon oxide deposition → fourth hydrogen plasma treatment → n-type hydrogenated amorphous silicon deposition.
Further, before step D, the method further comprises:
and C: performing first hydrogen plasma treatment on the front intrinsic amorphous silicon layer 5;
after step D, the method further comprises:
and E, step E: performing second hydrogen plasma treatment on the p-type doped hydrogenated silicon oxide layer 4;
prior to step I, the method further comprises:
step H: performing third hydrogen plasma treatment on the back intrinsic amorphous silicon layer 7;
after step I, the method further comprises:
step J: the fourth hydrogen plasma treatment is performed on the n-type doped hydrogenated silicon oxide layer 8.
In practice, furthermore, the key point of the preparation process is that the hydrogenation treatment is carried out both before and after the step of depositing the doped hydrogenated silicon oxide layer. Namely, the hydrogen plasma treatment is carried out on the intrinsic amorphous silicon layer at the bottom layer before deposition, and the hydrogen plasma treatment is carried out after deposition, wherein the two treatment processes are slightly different, thereby being beneficial to realizing better passivation effect.
Further, after step K, the method further comprises:
step L: TCO layer deposition is carried out on two sides of the heterojunction cell structure, and a front TCO layer 2 and a back TCO layer 10 are respectively formed.
Further, after step L, the method further comprises:
step M: and (3) screen printing the two sides of the heterojunction battery structure to form a front electrode 1 and a back electrode 11:
and step N: and curing the heterojunction cell structure.
In practical operation, after the above process steps, the process further comprises the process steps of: front side TCO deposition → back side TCO deposition → front and back side screen printing metallization pattern (making electrodes) → curing. Thus, a bulk heterojunction cell structure was prepared.
In actual practice, the specific embodiment of the overall manufacturing process comprises the following steps:
step A, texturing: and (3) texturing the n-type silicon wafer by using a KOH solution to prepare a textured structure with the side length of the pyramid base of 1-10 mu m.
Step B, depositing intrinsic amorphous silicon on the front surface: depositing by a PECVD mode, wherein the plasma frequency is 40.68MHz, the temperature is 100-250 ℃, the deposition pressure is 2.8-5.5 mbar, and the deposition power density is 40-80 mW/cm2The silane flow rate is 0.4-1.0 sccm, the hydrogen flow rate is 80-160 sccm, and the deposition thickness is 1-10 nm.
Step C, first hydrogen plasma treatment: adopting a PECVD mode, wherein the plasma frequency is 13.56MHz, the temperature is 100-250 ℃, the deposition pressure is 1.8-3.5 mbar, and the deposition power density is 40-80 mW/cm2The hydrogen flow is 100-300 sccm, and the treatment time is 20-600 s.
Step D, p type doped hydrogenated silicon oxide deposition: adopting a PECVD mode, wherein the plasma frequency is 13.56MHz, the temperature is 100-250 ℃, the deposition pressure is 1.8-5.5 mbar, and the deposition power density is 40-100 mW/cm2The flow rate of silane is 0.5-1.5 sccm, the flow rate of hydrogen is 50-300 sccm, the flow rate of carbon dioxide is 0-5 sccm, the flow rate of borane (hydrogen carrying source) is 5-30 sccm, and the deposition thickness is 10-20 nm.
Step E, second hydrogen plasma treatment: adopting a PECVD mode, wherein the plasma frequency is 13.56MHz, the temperature is 100-250 ℃, the deposition pressure is 1.8-3.5 mbar, and the deposition power density is 40-80 mW/cm2(the power is less than the first hydrogen plasma treatment), the hydrogen flow is 100-300 sccm.
Step F, p type doped hydrogenated amorphous silicon deposition: adopting a PECVD mode, wherein the plasma frequency is 13.56MHz, the temperature is 100-250 ℃, the deposition pressure is 1.8-5.5 mbar, and the deposition power density is 40-100 mW/cm2The flow rate of silane is 0.5-1.5 sccm, the flow rate of hydrogen is 50-300 sccm, the flow rate of borane (hydrogen carrying source) is 5-30 sccm, and the deposition thickness is 1-5 nm.
G, depositing intrinsic amorphous silicon on the back surface: depositing by a PECVD mode, wherein the plasma frequency is 40.68MHz, the temperature is 100-250 ℃, and the deposition pressure is 2.8-5.5 mbarThe deposition power density is 40-80 mW/cm2The silane flow rate is 0.4-1.0 sccm, the hydrogen flow rate is 80-160 sccm, and the deposition thickness is 1-10 nm.
Step H, third hydrogen plasma treatment: adopting a PECVD mode, wherein the plasma frequency is 13.56MHz, the temperature is 100-250 ℃, the deposition pressure is 1.8-3.5 mbar, and the deposition power density is 40-80 mW/cm2(the power is less than the first hydrogen plasma treatment), the hydrogen flow is 100-300 sccm.
Step I, n type doped hydrogenated silicon oxide deposition: adopting a PECVD mode, wherein the plasma frequency is 13.56MHz, the temperature is 100-250 ℃, the deposition pressure is 1.8-5.5 mbar, and the deposition power density is 40-100 mW/cm2The flow rate of silane is 0.5-1.5 sccm, the flow rate of hydrogen is 50-300 sccm, the flow rate of carbon dioxide is 0-5 sccm, the flow rate of phosphine (hydrogen carrying source) is 0.5-4 sccm, and the deposition thickness is 10-20 nm.
Step J, fourth hydrogen plasma treatment: adopting a PECVD mode, wherein the plasma frequency is 13.56MHz, the temperature is 100-250 ℃, the deposition pressure is 1.8-3.5 mbar, and the deposition power density is 40-80 mW/cm2(the power is less than the third hydrogen plasma treatment), the hydrogen flow is 100-300 sccm.
Step K, n type doped hydrogenated amorphous silicon deposition.
Step L, TCO layer deposition: and depositing transparent conductive film layers on two sides by adopting a PVD (physical vapor deposition) or RPD (reverse plasma deposition) mode.
Step M, step N, screen printing: the front and back cells were screen printed and cured.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention and is not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention are included in the scope of the present invention.
Claims (10)
1. A high efficiency heterojunction cell structure, comprising:
the middle battery structure comprises a first surface and a second surface which are oppositely arranged up and down, and an n-type monocrystalline silicon layer is arranged in the middle battery structure;
the front cell structure is stacked on the first surface and comprises a front intrinsic amorphous silicon layer, a p-type doped hydrogenated silicon oxide layer and a p-type doped amorphous silicon layer which are sequentially stacked along the direction far away from the first surface;
the middle cell structure is stacked on the back cell structure, the second surface is attached to the back cell structure, and the back cell structure comprises a back intrinsic amorphous silicon layer, an n-type doped hydrogenated silicon oxide layer and an n-type doped amorphous silicon layer which are sequentially stacked along the direction far away from the second surface;
the thickness ranges of the p-type doped amorphous silicon layer and the n-type doped amorphous silicon layer are both 1-5 nm, and the thickness ranges of the p-type doped hydrogenated silicon oxide layer and the n-type doped hydrogenated silicon oxide layer are both 10-20 nm.
2. A high efficiency heterojunction cell structure according to claim 1, wherein the thickness of both said p-type doped amorphous silicon layer and said n-type doped amorphous silicon layer is 3nm, and the thickness of both said p-type doped hydrogenated silicon oxide layer and said n-type doped hydrogenated silicon oxide layer is 12 nm.
3. The high efficiency heterojunction cell structure of claim 1 or 2, wherein the front cell structure further comprises a front TCO layer stacked on the p-doped amorphous silicon layer in a direction away from the first surface; the back cell structure further comprises a back TCO layer stacked on the n-type doped amorphous silicon layer along a direction far away from the second surface.
4. The high efficiency heterojunction cell structure of claim 3, wherein said front cell structure further comprises a front electrode disposed on said front TCO layer; the back cell structure further includes a back electrode disposed on the back TCO layer.
5. The high efficiency heterojunction cell structure of claim 4, wherein the doping elements of both the p-type doped hydrogenated silicon oxide layer and the p-type doped amorphous silicon layer are one or more of boron, aluminum and gallium; and the doping elements of the n-type doped hydrogenated silicon oxide layer and the n-type doped amorphous silicon layer are phosphorus.
6. The high-efficiency heterojunction cell structure of claim 5, wherein both the front-side TCO layer and the back-side TCO layer are metal oxide layers and/or doped composition layers with metal oxide as a main component, wherein the oxide is one or more of zinc oxide, indium oxide, titanium oxide and tungsten oxide; the front electrode and the back electrode are made of one or more of gold, silver, copper and aluminum.
7. A method for preparing a high-efficiency heterojunction battery structure is characterized by comprising the following steps:
step A: texturing is carried out on the silicon wafer, a textured structure with the side length of the pyramid base being 1-10 mu m is prepared, and an n-type monocrystalline silicon layer is formed;
and B: intrinsic amorphous silicon deposition is carried out on the first surface of the n-type monocrystalline silicon layer to form a front intrinsic amorphous silicon layer;
step D: carrying out p-type doped hydrogenated silicon oxide deposition on the front intrinsic amorphous silicon layer to form a p-type doped hydrogenated silicon oxide layer;
step F: depositing p-type doped hydrogenated amorphous silicon on the p-type doped hydrogenated silicon oxide layer to form a p-type doped hydrogenated amorphous silicon layer;
step G: after the heterojunction cell structure is turned over, intrinsic amorphous silicon deposition is carried out on the second surface of the n-type monocrystalline silicon layer to form a back intrinsic amorphous silicon layer; the first surface and the second surface are two surfaces which are arranged oppositely up and down of the n-type monocrystalline silicon layer;
step I: carrying out n-type doped hydrogenated silicon oxide deposition on the back intrinsic amorphous silicon layer to form an n-type doped hydrogenated silicon oxide layer;
step K: and depositing n-type doped hydrogenated amorphous silicon on the n-type doped hydrogenated silicon oxide layer to form an n-type doped hydrogenated amorphous silicon layer.
8. The method of manufacturing a high efficiency heterojunction cell structure of claim 7,
prior to step D, the method further comprises:
and C: carrying out first hydrogen plasma treatment on the front intrinsic amorphous silicon layer;
after step D, the method further comprises:
step E: carrying out second hydrogen plasma treatment on the p-type doped hydrogenated silicon oxide layer;
prior to step I, the method further comprises:
step H: carrying out third hydrogen plasma treatment on the back intrinsic amorphous silicon layer;
after step I, the method further comprises:
step J: and performing fourth hydrogen plasma treatment on the n-type doped hydrogenated silicon oxide layer.
9. The method of making a high efficiency heterojunction cell structure of claim 8, wherein after step K, the method further comprises:
step L: and depositing TCO layers on two sides of the heterojunction cell structure to respectively form a front TCO layer and a back TCO layer.
10. The method of making a high efficiency heterojunction cell structure of claim 9, wherein after step L, the method further comprises:
step M: screen printing is carried out on the two sides of the heterojunction battery structure to form a front electrode and a back electrode;
and step N: and curing the heterojunction cell structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011643595.4A CN114695588A (en) | 2020-12-30 | 2020-12-30 | High-efficiency heterojunction battery structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011643595.4A CN114695588A (en) | 2020-12-30 | 2020-12-30 | High-efficiency heterojunction battery structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114695588A true CN114695588A (en) | 2022-07-01 |
Family
ID=82136264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011643595.4A Pending CN114695588A (en) | 2020-12-30 | 2020-12-30 | High-efficiency heterojunction battery structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114695588A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140115435A (en) * | 2013-03-19 | 2014-10-01 | 엘지전자 주식회사 | Solar cell |
| CN104167472A (en) * | 2014-07-29 | 2014-11-26 | 河北汉盛光电科技有限公司 | Heterojunction solar energy battery and preparation method thereof |
| WO2016079123A1 (en) * | 2014-11-17 | 2016-05-26 | Total Marketing Services | Solar cell and method of manufacturing thereof |
| US20170222074A1 (en) * | 2016-02-01 | 2017-08-03 | Panasonic Intellectual Property Management Co., Ltd. | Solar cell and solar cell module |
| WO2019216545A1 (en) * | 2018-05-10 | 2019-11-14 | 엘지전자 주식회사 | Tandem solar cell and manufacturing method therefor |
| KR20200058735A (en) * | 2018-11-20 | 2020-05-28 | 성균관대학교산학협력단 | Method of fabricating backside emitter crystalline silicon solarcell capable of controlling optical property |
| CN111697110A (en) * | 2020-06-12 | 2020-09-22 | 上海理想万里晖薄膜设备有限公司 | Heterojunction solar cell and manufacturing method thereof |
-
2020
- 2020-12-30 CN CN202011643595.4A patent/CN114695588A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140115435A (en) * | 2013-03-19 | 2014-10-01 | 엘지전자 주식회사 | Solar cell |
| CN104167472A (en) * | 2014-07-29 | 2014-11-26 | 河北汉盛光电科技有限公司 | Heterojunction solar energy battery and preparation method thereof |
| WO2016079123A1 (en) * | 2014-11-17 | 2016-05-26 | Total Marketing Services | Solar cell and method of manufacturing thereof |
| US20170222074A1 (en) * | 2016-02-01 | 2017-08-03 | Panasonic Intellectual Property Management Co., Ltd. | Solar cell and solar cell module |
| WO2019216545A1 (en) * | 2018-05-10 | 2019-11-14 | 엘지전자 주식회사 | Tandem solar cell and manufacturing method therefor |
| KR20200058735A (en) * | 2018-11-20 | 2020-05-28 | 성균관대학교산학협력단 | Method of fabricating backside emitter crystalline silicon solarcell capable of controlling optical property |
| CN111697110A (en) * | 2020-06-12 | 2020-09-22 | 上海理想万里晖薄膜设备有限公司 | Heterojunction solar cell and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109411551B (en) | Electrode structure of high-efficiency crystalline silicon heterojunction solar cell deposited in multiple steps and preparation method thereof | |
| CN112802910A (en) | High-efficiency silicon heterojunction solar cell and preparation method thereof | |
| CN109449227B (en) | Crystalline silicon heterojunction solar cell electrode structure with laminated intrinsic layer and preparation method thereof | |
| CN112531052B (en) | Heterojunction battery structure and preparation method thereof | |
| KR101886818B1 (en) | Method for manufacturing of heterojunction silicon solar cell | |
| CN218788382U (en) | High-efficiency heterojunction solar cell | |
| CN114823935B (en) | Heterojunction battery and preparation method thereof | |
| CN217280794U (en) | Photovoltaic cell | |
| WO2022170872A1 (en) | Hjt cell having high photoelectric conversion efficiency and preparation method therefor | |
| CN215220730U (en) | High-efficiency silicon heterojunction solar cell | |
| KR20100119292A (en) | Buried contact type solar cell and method for manufacturing thereof | |
| CN108615775A (en) | Interdigital back contact heterojunction monocrystalline silicon battery | |
| CN211238272U (en) | Crystalline silicon/amorphous silicon heterojunction battery | |
| CN111463306A (en) | Novel heterojunction battery and preparation method thereof | |
| CN111564505A (en) | Heterojunction solar cell with passivated double intrinsic layers and preparation method thereof | |
| CN212783486U (en) | Double-sided heterojunction solar cell and photovoltaic module | |
| CN215220744U (en) | HJT battery with high photoelectric conversion efficiency | |
| CN110212060B (en) | Battery preparation method, battery assembly and solar power supply station | |
| CN114695588A (en) | High-efficiency heterojunction battery structure and preparation method thereof | |
| CN114361281A (en) | Double-sided heterojunction solar cell and photovoltaic module | |
| CN210156405U (en) | Heterojunction cell structure with hydrogen annealed TCO conductive film | |
| CN113451446A (en) | Sliced silicon heterojunction solar cell, preparation method and solar cell module | |
| CN114171631A (en) | Heterojunction solar cell and photovoltaic module | |
| CN114171633A (en) | Heterojunction solar cell and manufacturing method thereof | |
| CN217606831U (en) | High-efficiency heterojunction solar cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |