KR20140115435A - Solar cell - Google Patents

Abstract

A solar cell according to the present invention comprises a semiconductor substrate containing first conductive type impurities; and a passivation layer located on at least one side among the front side and the back side of the substrate, wherein the passivation layer comprises a first layer including amorphous silicon hydride (a-Si:H) and a second layer including amorphous silicon oxide hydride (a-SiOx:H). At the same time, the first layer is connected to the back side of the substrate and formed with intrinsic amorphous silicon hydride (i a-Si:H).

Description

Solar cell {SOLAR CELL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell, and more particularly, to a heterojunction solar cell.

With the recent depletion of existing energy resources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells produce electric energy from solar energy, and they are attracting attention because they have abundant energy resources and there is no problem about environmental pollution.

A typical solar cell includes a substrate and an emitter portion that forms a p-n junction with the substrate, and generates a current by using light incident through one side of the substrate.

In recent years, a solar cell having a heterojunction structure constituting an electric field portion using an amorphous silicon (a-Si) layer has been developed.

SUMMARY OF THE INVENTION The present invention provides a solar cell with improved efficiency.

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate containing an impurity of a first conductivity type; And a passivation layer located on at least one of the front and back sides of the substrate, wherein the passivation layer comprises a first layer comprising hydrogenated amorphous silicon (a-Si: H) and a first layer comprising hydrogenated amorphous silicon oxide (a- H). ≪ / RTI >

At this time, the first layer contacts the rear surface of the substrate and may be formed of hydrogenated intrinsic amorphous silicon (i a-Si: H).

And a second layer in contact with the backside of the first layer and comprising a hydrogenated amorphous silicon oxide (a-SiOx: H) or a hydrogenated amorphous silicon oxide (a-SiOx: H) comprising an impurity of the first conductivity type, As shown in FIG.

When the second layer is formed of hydrogenated intrinsic amorphous silicon oxide (i a -SiO x: H), the second layer may further comprise a Group 4 element such as germanium or carbon.

The solar cell includes a rear electric field portion containing impurities of the first conductive type at a higher concentration than the substrate, an emitter portion containing an impurity of the second conductive type opposite to the first conductive type, a first electrode connected to the emitter portion, And a second electrode connected to the step.

For example, the emitter portion and the first electrode may be located on the front side of the substrate, and the rear electric field portion and the second electrode may be located on the rear side of the substrate.

The rear electric field portion is in contact with the rear surface of the second layer, and the entire front surface of the second electrode is in direct contact with the rear electric portion.

The passivation layer and the rear surface electric field portion may be located on the entire rear surface of the substrate.

In another example, the emitter portion, the back electroluminescent portion, the first electrode, and the second electrode may be located on the back surface of the substrate.

The passivation layer is located over the entire rear surface of the substrate, and the emitter portion and the back surface electric portion may alternately be alternately arranged on the rear surface of the passivation layer.

In the conventional heterojunction solar cell, the intrinsic thin film constituting the passivation layer is formed as a single film of an amorphous silicon layer (i a-Si) or thermally grown silicon oxide (i SiOx).

In the case of the thermally grown silicon oxide, the thickness of the silicon oxide must be increased to completely block the minority carriers. However, as the thickness of the silicon oxide increases, the fill factor decreases So that the thickness of the silicon oxide is usually 5 nm or less.

However, since silicon oxide has a fixed charge close to neutral, silicon oxide formed to a thickness of 5 nm or less hardly causes a passivation effect due to the electric field effect.

Therefore, reflection of the minority carriers is primarily caused by the doping layer (electric field portion) formed in the passivation layer, but a part thereof proceeds to a doping layer having a relatively high defect density, so that a considerable amount of minority carriers There is a problem that this is recombined.

However, the passivation layer according to the embodiment of the present invention is composed of a first layer formed of hydrogenated amorphous silicon and a second layer formed of hydrogenated amorphous silicon oxide.

The hydrogenated amorphous silicon constituting the first layer has a very low defect density as compared with silicon oxide and can obtain a high open-circuit voltage (Voc) due to a high band gap. In addition, There is a merit that can be formed.

Further, the hydrogenated amorphous silicon oxide constituting the second layer has a positive charge of positive (+), so that a passivation action is caused by the field effect.

Therefore, the reflection function of the minority carriers moving to the doping layer is primarily performed by the second layer, and the doping layer is secondarily formed, so that the passivation property is improved.

In addition, the hydrogenated amorphous silicon oxide acts to hinder hydrogen effusion, so that the thermal stability of the passivation layer is maintained.

1 is a partial perspective view of a solar cell according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the solar cell shown in FIG. 1 cut along the line II-II.
3 is a graph comparing the thermal stability of a passivation layer according to an embodiment of the present invention and a conventional passivation layer.
4 to 7 are views for explaining an example of a method of manufacturing a solar cell according to the present invention.
8 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It is to be understood that the present invention is not intended to be limited to the specific embodiments but includes all changes, equivalents, and alternatives falling within the spirit and scope of the present invention.

In describing the present invention, the terms first, second, etc. may be used to describe various components, but the components may not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another.

For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The term "and / or" may include any combination of a plurality of related listed items or any of a plurality of related listed items.

Where an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, but other elements may be present in between Can be understood.

On the other hand, when it is mentioned that an element is "directly connected" or "directly coupled" to another element, it can be understood that no other element exists in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions may include plural expressions unless the context clearly dictates otherwise.

In the present application, the terms "comprises", "having", and the like are used interchangeably to designate one or more of the features, numbers, steps, operations, elements, components, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, or combinations thereof.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Terms such as those defined in commonly used dictionaries can be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are, unless expressly defined in the present application, interpreted in an ideal or overly formal sense .

In addition, the following embodiments are provided to explain more fully to the average person skilled in the art. The shapes and sizes of the elements in the drawings and the like can be exaggerated for clarity.

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a partial perspective view of a solar cell according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along a line II-II of FIG. 1, And the thermal stability of the conventional passivation layer.

As shown in the figure, a solar cell according to an embodiment of the present invention includes a substrate 110, an emitter section 120, a first dielectric layer 130 located on a front surface of the substrate 110, A passivation layer 160 located on the back surface of the passivation layer 160, a back surface field 170 located on the backside of the passivation layer 160, A first electrode 140 connected to the emitter section 120 and a second electrode 150 connected to the rear electric section 170. The first electrode 140 is connected to the emitter section 120,

Hereinafter, "front surface" refers to a surface facing upward in the accompanying drawings, and "rear surface " refers to a surface facing downward in the accompanying drawings.

The substrate 110 is a semiconductor substrate 110 made of a crystalline silicon containing an impurity of a first conductivity type, for example, an n-type conductivity type. At this time, the silicon may be single crystal silicon or polycrystalline silicon.

Since the substrate 110 has an n-type conductivity type, the substrate 110 contains impurities of pentavalent elements such as phosphorus (P), arsenic (As), antimony (Sb), and the like.

Alternatively, however, the substrate 110 may be of the p-type conductivity type and may be made of a semiconductor material other than silicon. When the substrate 110 has a p-type conductivity type, the substrate 110 may contain an impurity of a trivalent element such as boron (B), gallium, indium, or the like.

Hereinafter, a case where the substrate 110 has an n-type conductivity type will be described as an example.

Such a substrate 110 has a texturing surface whose surface is textured. More specifically, the substrate 110 is formed with a textured surface having a front surface on which the emitter section 120 is located and a back surface located on the opposite side of the front surface.

The emitter portion 120 located on the front surface of the substrate 110 is an impurity portion having a second conductivity type opposite to the conductivity type of the substrate 110, for example, a p-type conductivity type, Lt; RTI ID = 0.0 > 110 < / RTI >

Due to the built-in potential difference due to the pn junction, the electron-hole pairs, which are charges generated by the light incident on the substrate 110, are separated into electrons and holes, electrons move toward the n- Moves toward the p-type.

Therefore, the separated electrons move toward the substrate 110 and the separated holes move toward the emitter part 120 because the substrate 110 is n-type and the emitter part 120 is p-type.

Since the emitter section 120 has a p-type conductivity type, the emitter section 120 is formed by doping an impurity of a trivalent element such as boron (B), gallium (Ga), indium (In) .

Unlike the present embodiment, when the substrate 110 has a p-type conductivity type, the emitter portion 120 has an n-type conductivity type. In this case, the separated holes move toward the substrate 110, and the separated electrons move toward the emitter section 120.

When the emitter section 120 has an n-type conductivity type, the emitter section 120 dopes impurities of pentavalent elements such as phosphorus (P), arsenic (As), antimony (Sb) .

A first region of the emitter section 120 in contact with the first electrode 140 in the emitter section 120 and a second region of the emitter section 120 that is not in contact with or overlapped with the first electrode 140 The impurity doping concentrations may be different.

For example, the first region of the emitter section 120, which overlaps and contacts the first electrode 140 among the emitter sections 120 formed on the front surface of the substrate 110, may have a relatively high doping concentration of the impurity, And the second region of the emitter section 120 which is not in contact with or overlapped with the first electrode 140 may be formed as a low concentration emitter section having a lower doping concentration than that of the high concentration emitter section.

The first dielectric layer 130 formed on the emitter portion 120 may be formed of a material having a negative fixed charge such as aluminum oxide (AlO _x ) or yttrium oxide (Y ₂ O ₃ ) Lt; RTI ID = 0.0 > 130a < / RTI >

The aluminum oxide (AlO _x ) or the trisium oxide (Y ₂ O ₃ ) forming the first front dielectric layer 130a has a chemical passivation property due to the low interface trap density and a negative charge The field-effect passivation characteristics are excellent. It also has excellent stability, moisture permeability and abrasion resistance.

Therefore, the recombination speed of the charges on the surface of the emitter section 120 can be reduced to improve the efficiency of the solar cell and improve the long-term reliability.

The first dielectric layer 130 may further include a second front dielectric layer 130b and a third front dielectric layer 130c located on the first front dielectric layer 130a.

The second front dielectric layer 130b may be formed on the front surface of the first front dielectric layer 130a and may be formed of silicon nitride (SiN _x ) having a positive positive charge.

The third front dielectric layer 130c is formed on the front surface of the second front dielectric layer 130b and may be formed of silicon oxide (SiOx) having a positive positive charge.

The first dielectric layer 130 reduces the reflectivity of light incident through the front surface of the substrate 110 and increases the selectivity of a specific wavelength region to increase the efficiency of the solar cell.

The first dielectric layer 130 may include a plurality of openings OP1 that are formed in a line type or a spot type and expose a portion of the emitter layer 120. The first dielectric layer 130 may include an emitter The first electrode 140 is formed on the terminal portion 120.

The first electrode 140 is located on the emitter section 120 on the front surface of the substrate and is electrically and physically connected to the emitter section 120.

The first electrode 140 may include a plurality of first finger electrodes 141 and a plurality of first bus bar electrodes 143.

At this time, the plurality of first finger electrodes 141 extend in the first direction shown in FIG. 1, that is, in the X-X 'direction, and extend parallel to the adjacent first finger electrodes 141 at regular intervals.

The plurality of first finger electrodes 141 collects charges, for example, holes, which have migrated toward the emitter section 120.

The plurality of first finger electrodes 141 may be formed of Ni, Cu, Sn, Zn, In, Ti, Au, or combinations thereof. And at least one conductive material selected from the group consisting of

The plurality of first finger electrodes 141 may be formed by a screen printing method for printing and firing a conductive paste containing a conductive material, or may be formed using a plating process using a seed layer. The first finger electrode 141 formed by the plating process includes a plating layer 141a.

The plurality of first bus bar electrodes 143 are located on the same layer as the plurality of first finger electrodes 141 on the emitter section 120 and electrically connect the plurality of first finger electrodes 141 to each other.

At this time, the plurality of first bus bar electrodes 143 are elongated in a second direction orthogonal to the first direction, that is, in the second direction (YY 'direction) shown in FIG. 1, and the adjacent solar cells are electrically connected And collects the charges collected and moved by the plurality of first finger electrodes 141 and outputs the collected charges to an external device.

The first bus bar electrode 143 may be formed using the same material as the first finger electrode 141 according to the same method.

The entire surface of the first electrode 140 having such a configuration is in direct contact with the emitter section 120.

The passivation layer 160 located on the backside of the substrate 110 includes a first layer 160a contacting the backside of the substrate and a second layer 160b contacting the backside of the first layer 160a, And is located on the entire rear surface of the substrate 110.

The first layer 160a is formed of hydrogenated intrinsic amorphous silicon (i a-Si: H) containing no impurities.

The hydrogenated intrinsic amorphous silicon (i a-Si: H) constituting the first layer 160a has a very low defect density as compared with a material forming a conventional passivation layer, such as silicon oxide, ), A high open-circuit voltage (Voc) can be obtained, and a film can be formed at a temperature lower than 250 ° C.

The second layer 160b serves as a capping layer for suppressing the effusion of hydrogen contained in the first layer 160a and is a hydrogenated intrinsic amorphous silicon oxide (i a-SiOx: H) Or a hydrogenated amorphous silicon oxide (a-SiOx: H) comprising an impurity of the first conductivity type.

When the second layer 160b is formed of hydrogenated intrinsic amorphous silicon oxide (i a -SiO x: H), the second layer 160b may be doped with germanium (Ge) or carbon (C) 4 group elements.

The first layer 160a may be formed on the entire rear surface of the substrate 110 by Plasma-enhanced chemical vapor deposition (PECVD), and the second layer 160b may be formed by a Plasma- may be formed on the entire rear surface of the first layer 160a by enhanced chemical vapor deposition (PECVD).

The hydrogenated amorphous silicon oxide constituting the second layer 160b has a positive charge (+). Therefore, since the reflection action of the minority carriers moving to the doping layer, for example, the back surface front layer, is primarily performed by the second layer 160b and is made secondary by the doping layer, passivation characteristics are improved .

In addition, as described above, the hydrogenated amorphous silicon oxide acts as a capping film that hinders the effusion of hydrogen, so that the thermal stability of the passivation layer 160 is maintained.

That is, according to FIG. 3, in the case of the conventional passivation layer, the surface recombination speed rapidly increases when exposed to a temperature of 350 ° C or higher. However, in the case of the passivation layer 160 of the present embodiment, It can be seen that it is maintained almost constant.

The surface recombination rate increases when the hydrogen contained in the passivation layer is released and the passivation layer deteriorates.

Therefore, it can be seen from FIG. 3 that the release of hydrogen is suppressed in the passivation layer 160 of the present embodiment in which the second layer 160b acts as a capping layer.

According to the experiment of the present invention, after the conventional passivation layer is subjected to the high-temperature heat treatment, the n-type impurity contained in the rear electric field portion 170 is diffused into the substrate. However, even after the passivation layer of the present invention is heat- It was found that the n-type impurity contained in the semiconductor substrate 170 did not diffuse into the substrate.

When the n-type impurity contained in the rear electric field 170 is diffused into the substrate, a change in electrical characteristics of the solar cell occurs, and the defect density of the passivation layer is increased to decrease the open circuit voltage.

However, the passivation layer 160 of the present invention can maintain the characteristics of the solar cell because the second layer 160b formed of the hydrogenated amorphous silicon oxide has diffusion preventing action to prevent diffusion of impurities.

As such, the second layer 160b functions as a capping layer for preventing the hydrogen contained in the first layer 160a from being released, and diffuses into the substrate the impurities contained in the rear electric section 170 As a diffusion preventive film.

Therefore, the solar cell of this embodiment having the passivation layer 160 composed of the first layer 160a and the second layer 160b can maintain good thermal stability, and thus various choices can be made for the process of forming the rear electric field portion And the electrical characteristics can be kept good.

The rear electric field portion 170, which is in contact with the rear surface of the second layer 160b, contains impurities of a first conductivity type, for example, n-type, at a higher concentration than the substrate 110. [

Although this backside electrical section 170 can be formed of amorphous silicon carbide (a-SixCy), the material forming the backside electrical section 170 is not limited.

The backside electrical section 170 may be formed on the entire backside of the second layer 160b by plasma enhanced chemical vapor deposition (PECVD), but may be formed on a portion of the passivation layer 160, Or may be locally formed only in the region where the electrode 150 is located.

Since the rear electric field portion 170 having such a configuration performs a back electric field function, a potential barrier that generates a potential difference with the substrate 110 can be formed due to a difference in impurity concentration from the substrate 110.

Accordingly, when the substrate 110 has the n-type conductivity type and the emitter section 120 has the p-type conductivity type, the rear electric section 170 forms an n-type electric field higher than the substrate 110, Electrons that are the majority carriers of the substrate 110 can be moved more easily to the second electrode 150 through the rear electric section 170 and holes that are the majority carriers of the emitter section 120 move toward the second electrode 150 As shown in Fig.

The second dielectric layer 180 located on the rear surface of the rear electric 170 includes a first rear dielectric layer 180a and a second rear dielectric layer 180a having a positive positive charge opposite to that of the rear electric conductor 170, 180b.

More specifically, the first rear dielectric layer 180a is formed of the same material as the second front dielectric layer 130b, e.g., silicon nitride (SiNx), and the second rear dielectric layer 180b is formed of the same material as the third front dielectric layer 130c For example, silicon oxide (SiOx).

The silicon nitride film forming the first rear dielectric layer 180a can be formed at a lower processing temperature (between 300 DEG C and 400 DEG C) than the silicon oxide. Therefore, when the second dielectric layer 180 is formed, Is minimized.

The first and second rear dielectric layers 180a and 180b reduce the reflectivity of light incident through the back surface of the substrate 110 and increase the selectivity of a specific wavelength region to increase the efficiency of the solar cell.

The second dielectric layer 180 includes a plurality of openings OP2 formed in a line-type or spot-type planar shape to expose a part of the rear electric section 170. [

At this time, the interval between the plurality of openings OP2 is formed to be 100 mu m to 500 mu m.

The reason for defining the interval D1 between the plurality of openings OP2 is that when the laser beam is irradiated on the substrate 110 to form the opening OP2, the interval D1 between the openings becomes excessively narrow The area of the substrate 110 irradiated with the laser beam is excessively increased to deteriorate the characteristics of the substrate 110. If the space D1 between the openings is excessively large, ) Is lowered.

The second electrode 150 is formed on the rear surface of the rear electric part 170 exposed through the opening OP2.

The second electrode 150 is entirely in contact with the rear electric part 170 and includes a plurality of second finger electrodes 151 and a plurality of second bus bar electrodes 153.

The plurality of second finger electrodes 151 extend in the same first direction X-X 'as the plurality of first finger electrodes 141 and the second bus bar electrode 153 extends to the first bus bar electrode 143 And the second bus bar electrode 153 is located at a position facing the first bus bar electrode 143. The second bus bar electrode 153 extends in the second direction Y-Y '

The second bus bar electrode 153 is connected to the interconnector in the same manner as the first bus bar electrode 143. The second bus bar electrode 153 outputs a carrier collected from the rear electric section 170 to the second finger electrode 151 to an external device do.

The spacing between the second finger electrodes 151 may be greater than the spacing between the first finger electrodes 141.

The second electrode 150 may be formed using a plating method having a relatively low process temperature as compared with the screen printing method, like the first electrode 140. In this case, thermal damage to the film of the rear electric section 170 is minimized.

Since the second finger electrode 151 and the second bus bar electrode 153 directly contact the rear electric part 170, the contact resistance of the second electrode is reduced, thereby increasing the fill factor.

When a solar cell having such a configuration is irradiated with light and is incident on the semiconductor substrate 110 through the first dielectric layer 130 and the emitter section 120, electron-hole pairs are generated in the semiconductor substrate 110 by light energy .

At this time, since the reflection loss of light incident on the substrate 110 is reduced by the first dielectric layer 130, the amount of light incident on the substrate 110 increases.

The electron-hole pairs are separated from each other by the pn junction of the substrate 110 and the emitter section 120, and the separated holes move toward the emitter section 120 having the p-type conductivity type, To the substrate 110 having the conductive type.

The electrons that have moved toward the emitter section 120 are collected in the first bus bar electrode 143 through the first finger electrode 141 and electrons moved toward the substrate 110 pass through the rear electric section 170 2 finger electrodes 151 and then transferred to the second bus bar electrode 153. [

Accordingly, when the first bus bar electrode 143 of one of two neighboring solar cells and the second bus bar electrode 153 of another solar cell are connected by an inter-connector, a current flows, Power.

Since the second electrode 150 located on the rear surface of the substrate 110 is formed in the same or similar structure as the first electrode 140 located on the front surface of the substrate 110, The light can be incident on the rear surface of the light source. Therefore, the solar cell having the above-described structure can be used as a double-sided light receiving type solar cell.

A method of manufacturing a solar cell having such a structure will be described with reference to Figs. 4 to 7. Fig.

First, as shown in Fig. 4, an emitter section 120 containing a p-type impurity is formed on the entire surface of a substrate 110 containing an n-type impurity.

Next, as shown in FIG. 5, a first layer 160a formed of hydrogenated intrinsic amorphous silicon and a second layer 160b formed of hydrogenated intrinsic amorphous silicon oxide are sequentially formed on the back surface of the substrate 110 The passivation layer 160 is formed and the rear electric section 170 is formed on the rear surface of the second layer 160b.

6, aluminum oxide is deposited on the entire surface of the emitter layer 120 to form a first front dielectric layer 130a, and silicon nitride, which can be deposited at a lower process temperature than silicon oxide, A second front dielectric layer 130b is deposited over the front dielectric layer 130a and a silicon oxide is deposited over the second front dielectric layer 130b to enable deposition at a higher process temperature than silicon nitride, 130c.

The first rear dielectric layer 180a of the second dielectric layer 180 located on the rear surface of the rear electric field 170 is formed simultaneously with the second front dielectric layer 130b and the second rear dielectric layer 180b is formed simultaneously with the third dielectric layer 180b. And simultaneously with the front dielectric layer 130c.

7, a plurality of openings OP1 are formed in the first dielectric layer 130 located on the front surface of the substrate 110 by using laser ablation, A plurality of openings OP2 are formed in the second dielectric layer 180 located on the rear side using laser ablation.

A first electrode 130 is formed on the emitter section 120 exposed by the opening OP1 by using a plating process and a second electrode 130 is formed on the rear surface electric section 170 exposed by the opening section OP2. Thereby forming a solar cell 140 shown in FIG.

Hereinafter, a solar cell according to another embodiment of the present invention will be described with reference to FIG. The solar cell described in this embodiment relates to a rear-surface solar cell having a heterojunction structure.

As shown in the figure, the solar cell according to the present embodiment includes a substrate 210, a front passivation layer 260 'located on the front surface of the substrate 210, a first dielectric layer (not shown) disposed on the front passivation layer 260' A rear passivation layer 260 located on the rear surface of the substrate 210, a plurality of emitter regions 220 located on the rear surface of the rear passivation layer 260, a plurality of emitter regions 220 located on the rear surface of the rear passivation layer 260, A plurality of emitter sections 220 and a plurality of first subassemblies 270 located on the rear surfaces of the plurality of emitter sections 220, A plurality of first main electrodes 242 and a plurality of second main electrodes 242 located on the electrodes 241 and the second auxiliary electrodes 251 and a plurality of the first auxiliary electrodes 241 and the second auxiliary electrodes 251, 252).

The first auxiliary electrode 241 and the first main electrode 242 formed on the first auxiliary electrode 241 form the first electrode 240 and the second auxiliary electrode 251 and the second main electrode 252 ) Forms the second electrode 250.

The substrate 210 may be a semiconductor substrate of a first conductivity type, for example, a semiconductor such as silicon of n-type conductivity type.

However, the substrate 210 may be of the p-type conductivity type and may be made of a semiconductor material other than silicon.

In the solar cell of this embodiment, the rear surface of the substrate 210 has a flat surface instead of the textured surface. Here, the flat surface refers to a surface on which a plurality of convex portions or concave portions are not formed.

As a result, the components located on the rear surface of the substrate 210 are more uniformly and stably formed in close contact with the rear surface of the substrate 210, The contact resistance is reduced. Alternatively, however, the rear surface of the substrate 210 may also have a textured surface, such as a front surface, which is an uneven surface.

The rear passivation layer 260 located on the rear surface of the substrate 210 is configured in the same manner as in the embodiment of FIG. 1 described above, and the front passivation layer 260 'located on the front surface of the substrate 210 includes a rear passivation layer 260, And two layers arranged in the reverse order of FIG.

For example, although not specifically shown, the front passivation layer 260 'contacts the front surface of the substrate 210 and includes a first layer formed of hydrogenated intrinsic amorphous silicon, and a first layer contacting the front surface of the first layer, And a second layer formed of amorphous silicon oxide.

At this time, the front passivation layer 260 'may be located on the entire front surface of the substrate 210 or may be located on the front surface of the substrate 210 except for the edge portion of the front surface of the substrate 210.

The first dielectric layer 230 located on the front passivation layer 260 'may have the same structure as the first dielectric layer 130 according to the embodiment of FIG.

The rear electric field portions 270 are spaced apart from each other in a predetermined direction in the rear surface of the substrate 210.

The plurality of emitter portions 220 are spaced apart from each other in a predetermined direction in the rear surface of the substrate 210 and are located in a space between the rear electric portions 270.

Accordingly, the plurality of emitter portions 220 and the plurality of rear electric fields 270 are alternately arranged on the rear surface of the substrate 210.

Each emitter portion 220 is an impurity portion having a second conductivity type opposite to the conductivity type of the substrate 210, for example, a p-type conductivity type, and is formed of a semiconductor different from the substrate 210, for example, amorphous And may be made of amorphous silicon, which is a semiconductor. Accordingly, the plurality of emitter portions 220 form a hetero junction as well as a p-n junction with the substrate 210. [

The width of the rear electric section 270 and the width of the emitter section 220 may be the same or different from each other.

The width of the rear electric section 270 is increased to increase the rear electric field effect due to the rear electric section 270 when the width of the rear electric section 270 is different from the width of the emitter section 220, As shown in FIG.

Alternatively, the width of the emitter portion 220 may be formed to be larger than the width of the rear electric field portion 270 in order to increase the pn junction region and to improve the collection of holes having a lower mobility than the electrons It is possible.

A plurality of first auxiliary electrodes 241 located on the rear surface of the plurality of emitter portions 220 and a plurality of second auxiliary electrodes 251 disposed on the rear surfaces of the plurality of rear electric portions 270 are formed on the rear surface of the emitter portion 220, Respectively, along the electrical path 270.

At this time, each of the plurality of first auxiliary electrodes 241 is made of the same material and has the same structure, and each of the plurality of second auxiliary electrodes 251 is made of the same material and has the same structure.

The first auxiliary electrode 241 and the second auxiliary electrode 251 are formed of a transparent conductive oxide such as a transparent conductive oxide (TCO) and a transparent conductive film doped with a conductive material such as aluminum (Al) .

For example, the first auxiliary electrode 241 and the second auxiliary electrode 251 may be formed of Al-doped ZnO.

Accordingly, the plurality of first auxiliary electrodes 241 are electrically connected to the plurality of emitter portions 220, respectively, and the plurality of second auxiliary electrodes 251 are electrically connected to the plurality of rear front layers 270c, respectively .

The plurality of first main electrodes 242 located on the plurality of first auxiliary electrodes 241 are elongated along a plurality of the first auxiliary electrodes 241 and electrically connected to the plurality of first auxiliary electrodes 241, It is physically connected.

A plurality of second main electrodes 252 located on the plurality of second auxiliary electrodes 251 are elongated along the plurality of second auxiliary electrodes 251 and electrically connected to the plurality of second auxiliary electrodes 251 electrically, And physically connected.

The first main electrode 242 may have the same planar shape as the first auxiliary electrode 241 located below the first main electrode 242, but may have another planar shape.

Likewise, the second main electrode 252 may have the same planar shape as the second auxiliary electrode 251 located below the second main electrode 252, but may have another planar shape.

The first main electrode 242 moves toward the emitter portion 220 and collects an electric charge, for example, electrons, transmitted through the first auxiliary electrode 241.

The second main electrode 252 moves toward the rear electric field portion 270 and collects electric charges, for example, holes, which are transmitted through the second auxiliary electrode 251.

The plurality of first main electrodes 242 and the plurality of second main electrodes 252 may be made of silver (Ag) or silver-aluminum alloy (Al-Ag).

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Claims (12)

A semiconductor substrate containing an impurity of a first conductivity type; And
A passivation layer disposed on at least one of a front surface of the substrate and a rear surface opposite to the front surface,
/ RTI >
Wherein the passivation layer comprises a first layer comprising hydrogenated amorphous silicon (a-Si: H) and a second layer comprising hydrogenated amorphous silicon oxide (a-SiOx: H). The method of claim 1,
Wherein the first layer contacts the backside of the substrate, and the second layer contacts the backside of the first layer. 3. The method of claim 2,
Wherein the first layer is formed of hydrogenated intrinsic amorphous silicon (i a-Si: H). 4. The method of claim 3,
Wherein the second layer is formed of hydrogenated intrinsic amorphous silicon oxide (i a-SiO x: H). 5. The method of claim 4,
Wherein the second layer further comprises a Group 4 element such as germanium or carbon. 4. The method of claim 3,
Wherein the second layer is formed of a hydrogenated amorphous silicon oxide (a-SiOx: H) containing an impurity of the first conductivity type. 7. The method according to any one of claims 2 to 6,
An emitter section including an impurity of a second conductivity type opposite to the first conductivity type; a first electrode connected to the emitter section; and a second electrode connected to the emitter section, And a second electrode connected to the rear electric field portion. 8. The method of claim 7,
Wherein the emitter portion and the first electrode are located on a front surface side of the substrate, and the rear electric portion and the second electrode are located on a rear surface side of the substrate. 9. The method of claim 8,
Wherein the rear surface electric field portion is in contact with the rear surface of the second layer, and the entire front surface of the second electrode is in direct contact with the rear electric field portion. The method of claim 9,
Wherein the passivation layer and the rear electric field portion are located on the entire rear surface of the substrate. 8. The method of claim 7,
Wherein the emitter portion, the rear electric field portion, the first electrode, and the second electrode are located on a rear surface of the substrate. 12. The method of claim 11,
Wherein the passivation layer is disposed on the entire rear surface of the substrate, and the emitter portion and the rear surface electric portion are alternately disposed on the rear surface of the passivation layer.

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