CN114467175B - 半导体集成电路装置及半导体集成电路装置的制造方法 - Google Patents
半导体集成电路装置及半导体集成电路装置的制造方法 Download PDFInfo
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- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
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- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
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- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
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- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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- H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019-182406 | 2019-10-02 | ||
| JP2019182406 | 2019-10-02 | ||
| PCT/JP2020/035675 WO2021065590A1 (ja) | 2019-10-02 | 2020-09-23 | 半導体集積回路装置および半導体集積回路装置の製造方法 |
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| Publication Number | Publication Date |
|---|---|
| CN114467175A CN114467175A (zh) | 2022-05-10 |
| CN114467175B true CN114467175B (zh) | 2025-04-29 |
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| CN202080069062.1A Active CN114467175B (zh) | 2019-10-02 | 2020-09-23 | 半导体集成电路装置及半导体集成电路装置的制造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US12142606B2 (https=) |
| JP (1) | JP7598029B2 (https=) |
| CN (1) | CN114467175B (https=) |
| WO (1) | WO2021065590A1 (https=) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7640861B2 (ja) * | 2019-10-18 | 2025-03-06 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2025158980A1 (ja) * | 2024-01-24 | 2025-07-31 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2025158979A1 (ja) * | 2024-01-24 | 2025-07-31 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311305A (zh) * | 2013-06-13 | 2013-09-18 | 中国科学院半导体研究所 | 硅基横向纳米线多面栅晶体管及其制备方法 |
| CN104282655A (zh) * | 2013-07-12 | 2015-01-14 | 三星电子株式会社 | 半导体器件及其制造方法 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101937851B1 (ko) * | 2012-06-27 | 2019-04-10 | 삼성전자 주식회사 | 반도체 집적 회로, 그 설계 방법 및 제조방법 |
| US8836040B2 (en) | 2012-11-07 | 2014-09-16 | Qualcomm Incorporated | Shared-diffusion standard cell architecture |
| WO2017191799A1 (ja) * | 2016-05-06 | 2017-11-09 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| CN109314080B (zh) * | 2016-07-01 | 2022-09-30 | 株式会社索思未来 | 半导体集成电路装置 |
| US10453850B2 (en) | 2016-07-19 | 2019-10-22 | Tokyo Electron Limited | Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabrication |
| JP6974743B2 (ja) | 2016-08-01 | 2021-12-01 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| TWI739879B (zh) * | 2016-08-10 | 2021-09-21 | 日商東京威力科創股份有限公司 | 用於半導體裝置的延伸區域 |
| EP3404707A1 (en) * | 2017-05-15 | 2018-11-21 | IMEC vzw | Method for forming interconnected vertical channel devices and semiconductor structure |
| US10985161B2 (en) * | 2019-05-31 | 2021-04-20 | International Business Machines Corporation | Single diffusion break isolation for gate-all-around field-effect transistor devices |
| US11393815B2 (en) * | 2019-08-30 | 2022-07-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistors with varying width nanosheet |
-
2020
- 2020-09-23 CN CN202080069062.1A patent/CN114467175B/zh active Active
- 2020-09-23 WO PCT/JP2020/035675 patent/WO2021065590A1/ja not_active Ceased
- 2020-09-23 JP JP2021550640A patent/JP7598029B2/ja active Active
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2022
- 2022-03-28 US US17/706,117 patent/US12142606B2/en active Active
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2024
- 2024-10-10 US US18/911,967 patent/US20250040236A1/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311305A (zh) * | 2013-06-13 | 2013-09-18 | 中国科学院半导体研究所 | 硅基横向纳米线多面栅晶体管及其制备方法 |
| CN104282655A (zh) * | 2013-07-12 | 2015-01-14 | 三星电子株式会社 | 半导体器件及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US12142606B2 (en) | 2024-11-12 |
| CN114467175A (zh) | 2022-05-10 |
| WO2021065590A1 (ja) | 2021-04-08 |
| US20220223588A1 (en) | 2022-07-14 |
| JPWO2021065590A1 (https=) | 2021-04-08 |
| JP7598029B2 (ja) | 2024-12-11 |
| US20250040236A1 (en) | 2025-01-30 |
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