CN114341658A - 导线接合状态判定方法及导线接合状态判定装置 - Google Patents
导线接合状态判定方法及导线接合状态判定装置 Download PDFInfo
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- CN114341658A CN114341658A CN202080014962.6A CN202080014962A CN114341658A CN 114341658 A CN114341658 A CN 114341658A CN 202080014962 A CN202080014962 A CN 202080014962A CN 114341658 A CN114341658 A CN 114341658A
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- 238000000034 method Methods 0.000 title claims description 30
- 230000005540 biological transmission Effects 0.000 claims abstract description 32
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 26
- 238000001514 detection method Methods 0.000 claims description 25
- 238000002788 crimping Methods 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 description 22
- 239000000758 substrate Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 230000010365 information processing Effects 0.000 description 2
- 230000001902 propagating effect Effects 0.000 description 2
- 241000309551 Arthraxon hispidus Species 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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Abstract
一种导线接合状态判定装置(60),在将导线(16)接合在焊盘(36)上之后判定焊盘(36)与导线(16)的接合状态,且所述导线接合状态判定装置(60)包括:波形检测器(61),向导线(16)入射入射波(71),检测导线(16)的传输波形(73a)、及自焊盘(36)与导线(16)的第一接合面(23a)的反射波形(73b);以及接合判定器(62),基于由波形检测器(61)检测出的传输波形(73a)及反射波形(73b),判定焊盘(36)与导线(16)的接合状态。
Description
技术领域
本发明涉及一种在对电极接合导线之后,判定电极与导线的接合状态的导线接合状态判定方法及导线接合状态判定装置。
背景技术
在用于电子零件的组装工序的打线接合装置中,例如在半导体芯片的电极上接合细金线等导线。接合的导线延伸并在电路基板等电极处接合,从而进行半导体芯片的电极与电路基板的电极之间的连接。如果电极间的接合不顺利,就会发生所谓的连接不良。为了检测无法目视判别的连接不良,提出了从导线对半导体芯片入射适当的电流,测定流动的电流值来判定电连接不良。
例如,在专利文献1中,公开了经由导线施加高频信号,根据与流通过导线的电流对应的输出电平来进行接合的失败检测。另外,在专利文献2中公开了对导线施加矩形波,根据对穿过导线流入的电流的微分输出进行积分而获得的输出电平来进行导线的接合失败检测。
现有技术文献
专利文献
专利文献1:日本专利特开平9-64116号公报
专利文献2:日本专利特开平8-236587号公报
发明内容
发明所要解决的问题
但是,近年来,要求更准确地进行接合失败检测。然而,在专利文献1、专利文献2所记载的现有技术中,有时检测精度由于信号中包含的噪声而变差。
因此,本发明的目的是高精度地检测电极与导线的接合状态。
解决问题的技术手段
本发明的导线接合状态判定方法在对电极接合导线之后,判定电极与导线的接合状态,且所述导线接合状态判定方法的特征在于包括:波形检测工序,向导线入射规定的电力波形,检测导线的传输波形、及自电极与导线的接合面的反射波形;以及接合判定工序,基于在波形检测工序中检测出的传输波形及反射波形,判定电极与导线的接合状态。
由此,可高精度地检测电极与导线的接合状态。
在本发明的导线接合状态判定方法中,接合判定工序也可基于在波形检测工序中检测出的传输波形及反射波形来判定接合面的接合面积的大小。
由此,不仅可判定接合不良,还可判定接合面积是否良好。
在本发明的导线接合状态判定方法中,可为:接合判定工序在波形检测工序中检测出的反射波形的大小比传输波形的大小大的情况下,判定为接合面的接合面积比规定面积小,在反射波形的大小小于或等于传输波形的大小的情况下,判定为接合面的接合面积大于或等于规定面积。
由此,可利用简便的方法判定接合面积是否比导线的剖面面积大。
在本发明的导线连接状态判定方法中,可包括基准波形检测工序,向与电极的接合状态良好的导线入射规定的电力波形,将导线的传输波形及自接合面的反射波形作为基准波形进行检测,且接合判定工序在波形检测工序中检测出的反射波形的大小大于基准波形中包含的反射波形的大小的情况下,可判定为接合不良,在波形检测工序中检测出的反射波形的大小小于或等于基准波形中包含的反射波形的大小的情况下,可判定为接合良好。
由此,可利用简便的方法检测电极与导线的接合面积是否大于基准面积。
在本发明的导线接合状态判定方法中,可为:导线与电极的接合通过将形成于导线的前端的无空气球压接接合在电极上而形成压接球的球形接合来进行,接合面作为压接球与电极的第一接合面。
由此,可检测压接球与电极的第一接合面的接合面积的大小,且可判定接合状态。
在本发明的导线连接状态判定方法中,可为:导线与电极的接合包括将形成于导线的前端的无空气球压接接合在电极上的球形接合、及在球形接合之后将导线的侧面压接接合在另一电极上的针脚接合,接合面设为通过针脚接合形成的导线的侧面与另一电极的第二接合面。
由此,可检测在球形接合之后进行针脚接合时的针脚接合部位的接合状态。
本发明的导线连接状态判定装置是在电极上接合导线之后判定电极与导线的接合状态的导线接合状态判定装置,其特征在于包括:波形检测器,向导线入射规定的电力波形,检测导线的传输波形、及自电极与导线的接合面的反射波形;以及接合判定器,基于由波形检测器检测出的传输波形及反射波形,判定电极与导线的接合状态。
在本发明的导线接合状态判定装置中,接合判定器可基于由波形检测器检测出的传输波形及反射波形来判定接合面的接合面积的大小。
在本发明的导线接合状态判定装置中,可为:接合判定器在由波形检测器检测出的反射波形的大小比传输波形的大小大的情况下,判定为接合面的接合面积小于规定面积,在反射波形的大小小于或等于传输波形的情况下,判定为接合面的接合面积大于或等于规定面积。
在本发明的导线接合状态判定装置中,可为:接合判定器包括基准波形数据库,所述基准波形数据库将从波形检测器向与电极的接合状态良好的导线入射规定的电力波形时的导线的传输波形及自接合面的反射波形保存为基准波形,且参照基准波形数据库,在由波形检测器检测出的反射波形的大小大于基准波形中包含的反射波形的大小的情况下,判定为接合不良,在由波形检测器检测出的反射波形的大小小于或等于基准波形中包含的反射波形的大小的情况下,判定为接合良好。发明的效果
本发明可高精度地检测电极与导线的接合状态。
附图说明
图1是安装有实施方式的导线接合状态判定装置的打线接合装置的结构图。
图2是表示通过图1所示的打线接合装置利用导线连接半导体芯片的电极与基板的电极之间的半导体装置的立面图。
图3A是表示利用图1所示的打线接合装置进行的打线接合工序的立面图,是表示形成无空气球的状态的图。
图3B是表示利用图1所示的打线接合装置进行的打线接合工序的立面图,且是表示将无空气球压接到电极上而形成压接球的状态的图。
图3C是表示利用图1所示的打线接合装置进行的打线接合工序的立面图,且是表示从毛细管的前端延伸出导线尾端的状态的图。
图3D是表示利用图1所示的打线接合装置进行的打线接合工序的立面图,且是表示使毛细管的前端环形化而对基板的电极进行针脚接合的状态的图。
图4是表示实施方式的导线接合状态判定装置中的波形检测工序的说明图。
图5是表示反射波的电压相对于压接球与电极的接合面积的变化的图表。
图6是表示压接球与电极的接合面积大于导线的剖面面积的情况下的波形检测器所检测出的波形的图。
图7是表示压接球与电极的接合面积小于导线的剖面面积的情况下的波形检测器所检测出的波形的图。
图8是表示在压接球与电极的接合状态良好的情况下,使规定的电力波形入射到导线而利用波形检测器检测出的基准波形的图。
图9是表示在通过针脚接合进行接合的第二接合部的接合状态良好的情况下,使规定的电力波形入射到导线而利用波形检测器检测出的基准波形的图。
图10是表示通过链接合形成的导线环的图。
图11是用实线表示在形成图10所示的导线环之后,使规定的电力波形入射到导线而利用波形检测器检测出的基准波形,用虚线表示在第二接合部的接合不良的情况下检测出的传输波形及反射波形的图。
具体实施方式
以下,参照附图对实施方式的导线接合状态判定装置60进行说明。首先,对安装有实施方式的导线接合状态判定装置60的打线接合装置100进行说明。如图1所示那样,打线接合装置100包括:基座10、XY平台11、接合头12、Z方向马达13、接合臂14、超声波喇叭15、毛细管20、夹持器17、放电电极18、接合载台19、及控制部50。再者,在以下的说明中,将接合臂14或超声波喇叭15的延伸方向作为X方向,将在水平面上与X方向成直角的方向作为Y方向,将上下方向作为Z方向进行说明。
XY平台11安装在基座10上,使搭载在上侧的部件沿XY方向移动。
接合头12安装在XY平台11上并通过XY平台11向XY方向移动。在接合头12中收纳有Z方向马达13、及由Z方向马达13驱动的接合臂14。Z方向马达13具有定子13b。接合臂14成为根部14a与Z方向马达13的定子13b相向,并绕Z方向马达13的轴13a旋转自如地安装的转子。
在接合臂14的X方向的前端安装有超声波喇叭15,在超声波喇叭15的前端安装有毛细管20。超声波喇叭15通过未图示的超声波振子的振动对安装于前端的毛细管20进行超声波励振。毛细管20如后面说明的那样,在内部设置有沿上下方向贯通的贯通孔21,在贯通孔21中插通有导线16。
另外,在超声波喇叭15的前端的上侧设有夹持器17。夹持器17开闭来进行导线16的握持、放开。
在接合载台19的上侧设置有放电电极18。放电电极18在与插通毛细管20并从毛细管20的前端延伸出的导线16之间进行放电,使导线16熔融而形成无空气球22。
接合载台19吸附固定上表面安装有半导体芯片34的基板30,并且利用未图示的加热器加热基板30及半导体芯片34。
构成转子的接合臂14的根部14a利用接合头12的Z方向马达13的定子13b的电磁力而如图1中的箭头91所示那样旋转时,安装在超声波喇叭15前端的毛细管20如箭头91a所示那样向Z方向移动。另外,接合载台19通过XY平台11而在XY方向上移动。因此,毛细管20通过XY平台11及Z方向马达13而在XYZ方向上移动。
XY平台11、Z方向马达13、夹持器17、放电电极18、及接合载台19连接于控制部50,基于控制部50的指令而驱动。控制部50利用XY平台11及Z方向马达13调整毛细管20的XYZ方向的位置,并且控制夹持器17的开闭、放电电极18的驱动、接合载台19的加热。
控制部50是包括作为在内部进行信息处理的处理器的中央处理器(centralprocessing unit,CPU)51、及存储运行程序或运行数据等的存储器52的计算机。
如图2所示那样,打线接合装置100是利用环形导线26连接作为半导体芯片34的电极的焊盘36与作为基板30的另一电极的引线32之间来制造半导体装置的装置。
以下,参照图3A至图3D简单说明利用打线接合装置100进行的打线接合的各工序。
如图3A所示那样,在毛细管20的贯通孔21中插通有导线16。打线接合装置100的控制部50使图1所示的放电电极18与从毛细管20的前端延伸出的导线16之间产生放电,而将导线16成形为球状的无空气球22。
接着,如图3B的箭头92所示那样,控制部50进行使毛细管20下降,而利用毛细管20的前端以载荷F1将无空气球22按压在半导体芯片34的焊盘36上的球形接合。于是,无空气球22被压接在焊盘36上而成形为圆板状的压接球23。在压接球23的下表面与焊盘36的上表面之间,形成将形成压接球23的金属与焊盘36的金属接合而成的第一接合面23a。第一接合面23a是压接球23与焊盘36的压接面,构成第一接合点P1。
接着,如图3C的箭头93所示那样,控制部50使毛细管20上升而使导线尾端24从毛细管20的前端延伸出来。
之后,如图3D的箭头94所示那样,控制部50使毛细管20的前端从半导体芯片34的焊盘36向基板30的引线32环形化,利用毛细管20的前端以载荷F2将导线16的侧面按压在基板30的引线32上来进行针脚接合,而将导线16的侧面压接在引线32上。导线16的侧面如果被压接,则形成第二接合部25。第二接合部25的下表面与引线32接合,从而形成第二接合面25a。第二接合面25a是导线16的侧面与引线32的压接面,构成第二接合点P2。
其后,控制部50关闭夹持器17,使毛细管20上升,并利用第二接合部25切断导线16。由此,如图2所示那样,构成利用环形导线26连接第一接合点P1与第二接合点P2的半导体装置。
接着,参照图1、图4,说明实施方式的导线接合状态判定装置60。
如图1所示那样,实施方式的导线接合状态判定装置60包括波形检测器61及接合判定器62。波形检测器61包括第一端子66及第二端子67。第一端子66连接于夹持器17。另外,第二端子67连接于接合载台19并且接地。
如图4所示那样,波形检测器61使规定的电力波形的入射波71从第一端子66入射至导线16,并且检测包括导线16的传输波形73a、及自焊盘36与导线16的第一接合面23a的反射波形73b的检测波形73,并输出到接合判定器62。再者,波形检测器61可使用市售的网络分析器来构成。
接合判定器62基于从波形检测器61输入的、包括导线16的传输波形73a、及自第一接合面23a的反射波形73b的检测波形73来判定导线16与焊盘36的接合状态。
如图1所示那样,接合判定器62是包括作为在内部进行信息处理的处理器的CPU63、及存储有运行程序或数据的存储器64的计算机。存储器64中存储有后面说明的基准波形数据库65。
如图1所示那样,导线接合状态判定装置60与打线接合装置100的控制部50连接,与控制部50之间进行信息的收发。
接着,参照图4~图8,说明实施方式的导线接合状态判定装置60的运行。在以下的说明中,对如图4所示那样将在时刻t0电压从0步进变化为Ein的电压波形作为规定的电力波形入射到导线16的情况进行说明。也可使除此之外的形状的电力波形作为规定的电力波形入射。
如先前参照图3A~图3B所说明的那样,控制部50使毛细管20下降,将无空气球22压接在焊盘36上而形成压接球23,将压接球23与焊盘36接合。由此,在压接球23与焊盘36之间,形成将形成压接球23的金属与焊盘36的金属接合的第一接合面23a。
控制部50释放在成形压接球23时施加的载荷F1,使毛细管20的前端从压接球23的上表面略微上升。另外,控制部50输出将夹持器17关闭的指令。夹持器17根据此指令而关闭,夹持器17与导线16电连接,导线16与波形检测器61的第一端子66连接。
如图4所示那样,波形检测器61从第一端子66输出在时刻t0电压从0步进变化为Ein的入射波71。如图4中的箭头97a所示那样,从第一端子66输出的入射波71进入夹持器17,并从夹持器17向导线16传输。然后,如图4中的箭头97b所示那样,入射波71在导线16内朝向压接球23传播。然后,如图4中的箭头97c所示那样,当入射波71到达第一接合面23a时,在第一接合面23a反射而成为反射波72,且如图4中的箭头98a所示那样,从第一接合面23a朝向导线16传播,如图4中的箭头98b所示那样,在导线16中朝向夹持器17传播。然后,反射波72从夹持器17朝向波形检测器61的第一端子66传播。如图4所示那样,反射波72具有电压从0步进变化为Eout的波形。反射波72在从输出入射波71的时刻t0起经过时间Δt后的时刻t1返回到波形检测器61。在时刻t1返回到波形检测器61的反射波72是电压在时刻t1从0步进变化为Eout的电压波形。
如图4所示那样,在从输出入射波71的时刻t0起到反射波72返回的时刻t1之间,波形检测器61检测与通过导线传输的入射波71同样地电压从0步进变化为Ein的传输波形73a(波形检测工序)。然后,在反射波72返回的时刻t1以后,检测电压为Eout的反射波形73b。此处,对于从输出入射波71的时刻t0到反射波72返回波形检测器61的时刻t1为止的时间Δt,将夹持器17与压接球23的第一接合面23a的距离设为L,则
Δt=2*L/(导线中的电力波形的传播速度)----(式1)
导线16中的电力波形的传播速度为接近光速的速度,因此时间Δt非常短,为几psec(微微秒)左右。再者,在式1中忽略波形检测器61的第一端子66与夹持器17之间的连接线的长度,但是也可考虑此连接线的长度来计算时间Δt。后面说明的时间Δt2、Δt83、Δt82、Δt81的情况也一样。
图4所示的反射波72或反射波形73b的电压Eout根据压接球23与焊盘36的第一接合面23a的接合面积Ab而变化。如图5所示那样,在第一接合面23a的接合面积Ab与作为规定面积的导线16的剖面面积Aw相同的情况下,第一接合面23a的阻抗与导线16的阻抗变得相同,因此反射波72、或者反射波形73b的电压Eout与在导线16中传输的入射波71的电压Ein变得相同。
如果第一接合面23a的接合面积Ab大于作为规定面积的导线16的剖面面积Aw,则第一接合面23a的阻抗变小,因此反射波72或反射波形73b的电压Eout变得比Ein小。相反,如果第一接合面23a的接合面积Ab小于作为规定面积的导线16的剖面面积Aw,则第一接合面23a的阻抗变得大于导线16的阻抗,因此反射波72或反射波形73b的电压Eout变得比Ein大。
因此,如图6所示那样,在第一接合面23a的接合面积Ab大于作为规定面积的导线16的剖面面积Aw的情况下,检测波形73中包含的反射波形73b的电压Eout变得比检测波形73中包含的传输波形73a的电压Ein小。
相反,如图7所示那样,在第一接合面23a的接合面积Ab小于导线16的剖面面积Aw的情况下,检测波形73中包含的反射波形73b的电压Eout变得比检测波形73中包含的传输波形73a的电压Ein大。
因此,接合判定器62的CPU 63获取紧接在开始输出入射波71的时刻t0之后的传输波形73a的电压值作为传输波形73a的电压Ein,获取紧接在时刻t1之后的反射波形73b的电压值作为反射波形73b的电压Eout。然后,接合判定器62的CPU 63通过比较获取的传输波形73a的电压Ein与反射波形73b的电压Eout,判定第一接合面23a的接合面积Ab是大于还是小于导线16的剖面面积Aw(接合判定工序)。
即,接合判定器62的CPU 63在获取的反射波形73b的电压Eout的大小比获取的传输波形73a的电压Ein大的情况下,判定为第一接合面23a的接合面积Ab小于导线16的剖面面积Aw,在获取的反射波形73b的电压Eout的大小小于或等于传输波形73a的电压Ein的情况下,判定为第一接合面23a的接合面积Ab大于或等于导线16的剖面面积Aw。
如以上所说明那样,导线接合状态判定装置60使入射波71入射到导线16,检测导线16中的传输波形73a的电压Ein、及自压接球23与焊盘36的第一接合面23a的反射波形73b的电压Eout,通过比较电压Ein与电压Eout的简便方法,可判定第一接合面23a的接合面积Ab是否大于导线16的剖面面积Aw。
另外,接合判定器62的CPU 63在获取的反射波形73b的电压Eout的大小小于或等于传输波形73a的电压Ein的情况下,可判定为第一接合面23a的接合状态良好,在获取的反射波形73b的电压Eout的大小大于所获取的传输波形73a的电压Ein的情况下,可判定为第一接合面23a的接合状态为不良。再者,在接合判定工序中,说明了以导线的剖面面积为基准判定接合状态,但不限于此,例如也可根据接合面积相对于压接球23的下表面的比率、接合面积相对于第二接合部25或后述的针脚接合部的导线侧面的比率等判断接合状态。
接着,参照图8对实施方式的导线接合状态判定装置60的另一操作进行说明。如图8所示那样,准备包括焊盘36与导线16的接合状态良好、与焊盘36的第一接合面23a的接合面积Ab成为基准接合面积As的基准第一接合部P1s的半导体装置。然后,获取包括使入射波71从波形检测器61入射到导线16时的导线16的传输波形74a及自第一接合面23a的反射波形74b的电压波形,作为基准波形74。然后,将所获取的基准波形74存储在接合判定器62的存储器64中的基准波形数据库65中(基准波形检测工序)。
如图8所示那样,在第一接合面23a的基准接合面积As的大小大于导线16的剖面面积Aw的情况下,基准波形74中包含的反射波形74b的电压Eout成为比基准波形74中包含的传输波形74a的电压Ein小的Es。
与之前参照图5说明的同样,在第一接合面23a的接合面积Ab大于或等于作为规定面积的基准接合面积As的情况下,电压Eout变得比电压Es低。相反,在第一接合面23a的接合面积Ab小于作为规定面积的基准接合面积As的情况下,电压Eout变得比电压Es高。
在进行第一接合面23a的接合面积的判定的情况下,与参照图4说明的同样,导线接合状态判定装置60使在时刻t0电压从0步进变化为Ein的入射波71从波形检测器61入射到夹持器17,且利用波形检测器61检测包括传输波形73a及反射波形73b的检测波形73。接合判定器62的CPU 63获取紧接在时刻t1之后的反射波形73b的电压值作为电压Eout。然后,接合判定器62的CPU 63将存储在基准波形数据库65中的基准波形74中包含的反射波形74b的电压Es与反射波形73b的电压Eout进行比较,判定第一接合面23a的接合面积Ab比基准接合面积As大还是小(接合判定工序)。
即,接合判定器62的CPU 63在获取的反射波形73b的电压Eout的大小比基准波形74中包含的反射波形74b的电压Es大的情况下,判定为第一接合面23a的接合面积Ab小于基准接合面积As,在获取的反射波形73b的电压Eout的大小小于或等于基准波形74中包含的反射波形74b的电压Es的情况下,判定为第一接合面23a的接合面积Ab大于或等于基准接合面积As。
由此,能够以简便的方法检测焊盘36与导线16的接合面积Ab是否大于基准接合面积As。另外,接合判定器62在反射波形73b的电压Eout的大小比基准波形74中包含的反射波形74b的电压Es大的情况下,可判断为第一接合面23a的接合状态不良,在反射波形73b的电压Eout的大小小于或等于基准波形74中包含的反射波形74b的电压Es的情况下,可判断为第一接合面23a的接合状态良好。
在以上的说明中,说明了第一接合面23a通过球形接合进行接合、判定压接球23与焊盘36的第一接合面23a的接合面积Ab的大小的情况,但不限于此,也可适用于通过针脚接合进行接合的第二接合部25的导线16的侧面与引线32的第二接合面25a。
首先,与参照图8说明的同样,如图9所示那样,准备引线32与导线16的侧面的接合状态良好、与引线32的第二接合面25a的接合面积Ab为基准接合面积As的基准第二接合部P2s。然后,在时刻t0使入射波71从波形检测器61入射到导线16。当在时刻t0使入射波71从波形检测器61入射到导线16时,自第二接合面25a的反射波72在从t0起经过时间Δt2后的时刻t2返回到波形检测器61。
此处,关于Δt2,将夹持器17与引线32的第二接合面25a的距离设为L2,
Δt2=2*L2/(导线中的电力波形的传播速度)---(式2)。
因此,波形检测器61在从时刻t0到反射波72返回的时刻t2之间,检测电压从0步进变化为Ein的传输波形75a,在反射波72返回的时刻t2以后,检测电压为Eout的反射波形75b。波形检测器61获取包含导线16的传输波形75a及自第二接合面25a的反射波形75b的电压波形作为基准波形75。然后,将所获取的基准波形75存储在接合判定器62的存储器64中的基准波形数据库65中(基准波形检测工序)。
如图9所示那样,在第二接合面25a的基准接合面积As的大小比导线16的剖面面积Aw大的情况下,基准波形75中包括的反射波形75b的电压Eout成为比基准波形75中包括的传输波形75a的电压Ein小的Es2。
与之前参照图8说明的同样,在第二接合面25a的接合面积Ab大于或等于作为规定面积的基准接合面积As的情况下,电压Eout变得比电压Es2低。相反,在第二接合面25a的接合面积Ab小于作为规定面积的基准接合面积As的情况下,电压Eout变得比电压Es2高。
与之前参照图8说明的同样,在进行第二接合面25a的接合面积的判定的情况下,导线接合状态判定装置60使入射波71从波形检测器61入射到夹持器17。接合判定器62的CPU63在反射波形73b的电压Eout的大小比电压Es2大的情况下,判定为第二接合面25a的接合面积Ab小于基准接合面积As,在反射波形73b的电压Eout的大小小于或等于电压Es2的情况下,判定为第二接合面25a的接合面积Ab大于或等于基准接合面积As。
再者,与参照图8说明的同样,也可基于反射波形73b的电压Eout的大小判定第二接合面25a的接合是否良好。
接着,参照图10、图11说明导线接合状态判定装置60的另一操作。导线接合状态判定装置60也可适用于在球形接合后,执行多次针脚接合,利用导线16连续地连接在基板30上积层安装成多层的多层半导体芯片34的各层的焊盘36与基板30的引线32的链接合的中间针脚接合部的接合面的接合状态的判定。
参照图10,对链接合的例子进行说明。图10所示的例子是从基板30的引线32朝向积层的半导体芯片134、半导体芯片234的各焊盘136、236连续地进行接合的逆接合。
在图10所示的链接合中,打线接合装置100的控制部50最初在基板30的引线32上进行球形接合而形成压接球80。压接球80与引线32的压接面为第一接合面81a,且构成第一接合部81。接着,控制部50将毛细管20朝向第一层的半导体芯片134的焊盘136环形化,将导线16的侧面按压在焊盘136上进行针脚接合。焊盘136与导线16的侧面的压接面为第二接合面82a,构成第二接合部82。同样地,控制部50将毛细管20朝向第二层的半导体芯片234的焊盘236环形化,将导线16的侧面按压在焊盘236上进行针脚接合。焊盘236与导线16的侧面的压接面为第三接合面83a,构成第三接合部83。第一接合部81与第二接合部82之间通过环形导线85连接,而第二接合部82与第三接合部83之间通过环形导线86连接。
接着,对作为链接合的中间的针脚接合部的第二接合部82的第二接合面82a的接合是否良好的判断进行说明。
在进行第二接合面82a是否良好的判断之前,与之前参照图8、图9说明的相同,导线接合状态判定装置60进行将使入射波71入射到第一接合面81a、第二接合面82a、第三接合面83a的各接合面的接合状态良好的基准环路时的电压波形作为基准波形76而存储在基准波形数据库65中的基准波检测工序。
如图11所示那样,波形检测器61向夹持器17输入在时刻t0电压从0步进变化为Ein的入射波71。入射到夹持器17的入射波71从夹持器17向导线16传输。然后,在图10所示的第三接合面83a反射后,电压Eout3的反射波72返回到波形检测器61。另外,从第三接合面83a传播到环形导线86的入射波71在第二接合面82a反射,电压Eout2的反射波72返回波形检测器61。进而,从第二接合面82a入射到环形导线85的入射波71在第一接合面81a反射,电压Eout1的反射波72返回到波形检测器61。
自第一接合面81a、第二接合面82a、第三接合面83a的反射波72返回的时间分别是时刻t0的时间Δt83、Δt82、Δt81之后。此处,时间Δt83、Δt82、Δt81如以下般计算。
Δt83=2*L83/(电力波形的传播速度)---(式3)
Δt82=2*L82/(电力波形的传播速度)---(式3)
Δt81=2*L81/(电力波形的传播速度)---(式3)
此处,L83是从夹持器17到第三接合面83a的距离,L82是在L83上加上沿着环形导线86的第三接合面83a到第二接合面82a的距离后的距离,L81是在L82上加上沿着环形导线85的第二接合面82a到第一接合面81a的距离后的距离。
如图11所示那样,波形检测器61在从时刻t0到时刻t83期间,检测电压Ein的传输波形76a,在时刻t83到时刻t82期间,检测自第三接合面83a的电压Eout3的反射波形76b,在时刻t82到时刻t81期间,检测自第二接合面82a的电压Eout2的反射波形76c,在时刻t81以后,检测自第一接合面81a的电压Eout1的反射波形76d。
接合判定器62将在使入射波71入射到第一接合面81a、第二接合面82a、第三接合面83a的各接合面的接合状态良好的基准环路时波形检测器61检测出的包含传输波形76a、及反射波形76b、反射波形76c、反射波形76d的电压波形作为基准波形76存储在基准波形数据库65中。另外,将检测出的各反射波形76b、反射波形76c、反射波形76d的各电压Eout3、电压Eout2、电压Eout1分别作为基准电压Es83、基准电压Es82、基准电压Es81存储在基准波形数据库65中。
导线接合状态判定装置60在判定第二接合面82a的接合状态是否良好的情况下,在针对第三接合部83的针脚接合结束之后,如图10所示那样,使入射波71从波形检测器61入射到夹持器17。然后,利用波形检测器61如图11的虚线所示,检测包括传输波形77a、及反射波形77b、反射波形77c、反射波形77d的检测波形77。
然后,接合判定器62将检测波形77所包含的自第二接合面82a的反射波形77c与基准波形76所包含的自第二接合面82a的反射波形76c进行比较。在第二接合面82a的接合不良的情况下,反射波形77c的电压变得高于基准电压Es82。因此,接合判定器62在反射波形77c的电压高于基准电压Es82的情况下,判定为第二接合面82a的接合不良。另一方面,在反射波形77c的电压等于或低于基准电压Es82的情况下,判定为第二接合面82a的接合良好。
如以上所说明那样,实施方式的导线接合状态判定装置60可判定链接合中的中间针脚接合部的接合是否良好。
再者,在以上的说明中,以从基板30的引线32向积层的半导体芯片134、半导体芯片234的各焊盘136、236连续地进行接合的逆接合为例进行了说明,但所述的方法也可适用于对第二层的半导体芯片234的焊盘236进行球形接合,对第一层的半导体芯片134的焊盘136及基板30的引线32进行针脚接合的链接合的第二接合部82的接合是否良好的判断。
如以上所说明那样,实施方式的导线接合状态判定装置60可高精度地检测焊盘36与导线16的接合状态、或者引线32与导线16的接合状态。
符号的说明
10:基座
11:XY平台
12:接合头
13:Z方向马达
13a:轴
13b:定子
14:接合臂
14a:根部
15:超声波喇叭
16:导线
17:夹持器
18:放电电极
19:接合载台
20:毛细管
21:贯通孔
22:无空气球
23、80:压接球
23a、81a:第一接合面
24:导线尾端
25:第二接合部
25a、82a:第二接合面
26、85、86:环形导线
30:基板
32:引线
34、134、234:半导体芯片
36、136、236:焊盘
50:控制部
51、63:CPU
52、64:存储器
60:导线接合状态判定装置
61:波形检测器
62:接合判定器
65:基准波形数据库
71:入射波
72:反射波
73、77:检测波形
73a、74a、75a、76a、77a:传输波形
73b、74b、75b、76b、77b:反射波形
74、75、76:基准波形
81:第一接合部
82:第二接合部
83:第三接合部
83a:第三接合面
100:打线接合装置
Claims (10)
1.一种导线接合状态判定方法,在电极上接合导线之后判定所述电极与所述导线的接合状态,所述导线接合状态判定方法的特征在于包括:
波形检测工序,向所述导线入射规定的电力波形,检测所述导线的传输波形、及自所述电极与所述导线的接合面的反射波形;以及
接合判定工序,基于在所述波形检测工序中检测出的所述传输波形及所述反射波形,判定所述电极与所述导线的接合状态。
2.根据权利要求1所述的导线接合状态判定方法,其特征在于,
所述接合判定工序是,基于在所述波形检测工序检测出的所述传输波形及所述反射波形,判定所述接合面的接合面积的大小。
3.根据权利要求2所述的导线接合状态判定方法,其特征在于,
所述接合判定工序是,在所述波形检测工序检测出的所述反射波形的大小大于所述传输波形的大小的情况下,判定为所述接合面的接合面积小于规定面积,在所述反射波形的大小小于或等于所述传输波形的大小的情况下,判定为所述接合面的接合面积大于或等于所述规定面积。
4.根据权利要求1所述的导线接合状态判定方法,其特征在于包括:
基准波形检测工序,向与所述电极的接合状态良好的所述导线入射规定的电力波形,将所述导线的传输波形及自所述接合面的所述反射波形作为基准波形进行检测,且
所述接合判定工序中,在所述波形检测工序中检测出的所述反射波形的大小大于所述基准波形中包含的所述反射波形的大小的情况下,判定为接合不良,在所述波形检测工序中检测出的所述反射波形的大小小于或等于所述基准波形中包含的所述反射波形的大小的情况下,判定为接合良好。
5.根据权利要求1至4中任一项所述的导线接合状态判定方法,其特征在于,
所述导线对所述电极的接合通过将形成于所述导线的前端的无空气球压接接合在所述电极上而形成压接球的球形接合来进行,
所述接合面为所述压接球与所述电极的第一接合面。
6.根据权利要求5所述的导线接合状态判定方法,其特征在于,
所述导线对所述电极的接合包括:球形接合,将形成于所述导线的前端的所述无空气球压接接合在所述电极上;以及针脚接合,在球形接合之后将所述导线的侧面压接接合在另一电极,
所述接合面为通过所述针脚接合形成的所述导线的侧面与所述另一电极的第二接合面。
7.一种导线接合状态判定装置,在将导线接合到电极上之后判定所述电极与所述导线的接合状态,其特征在于包括:
波形检测器,向所述导线入射规定的电力波形,检测所述导线的传输波形、及自所述电极与所述导线的接合面的反射波形;以及
接合判定器,基于由所述波形检测器检测出的所述传输波形及所述反射波形,判定所述电极与所述导线的接合状态。
8.根据权利要求7所述的导线接合状态判定装置,其特征在于,
所述接合判定器基于由所述波形检测器检测出的所述传输波形及所述反射波形,判定所述接合面的接合面积的大小。
9.根据权利要求8所述的导线接合状态判定装置,其特征在于,
所述接合判定器在由所述波形检测器检测出的所述反射波形的大小大于所述传输波形的大小的情况下,判定为所述接合面的接合面积小于规定面积,在所述反射波形的大小小于或等于所述传输波形的情况下,判定为所述接合面的接合面积大于或等于所述规定面积。
10.根据权利要求7所述的导线接合状态判定装置,其特征在于,
所述接合判定器包括基准波形数据库,所述基准波形数据库将从所述波形检测器向与所述电极的接合状态良好的所述导线入射规定的电力波形时的所述导线的传输波形及自所述接合面的所述反射波形存储为基准波形,且
参照所述基准波形数据库,在由所述波形检测器检测出的所述反射波形的大小大于所述基准波形中包含的所述反射波形的大小的情况下,判定为接合不良,在由所述波形检测器检测出的所述反射波形的大小小于或等于所述基准波形中包含的所述反射波形的大小的情况下,判定为接合良好。
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