CN114255708A - 具有内部补偿的显示装置和像素单元 - Google Patents

具有内部补偿的显示装置和像素单元 Download PDF

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Publication number
CN114255708A
CN114255708A CN202111086735.7A CN202111086735A CN114255708A CN 114255708 A CN114255708 A CN 114255708A CN 202111086735 A CN202111086735 A CN 202111086735A CN 114255708 A CN114255708 A CN 114255708A
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CN
China
Prior art keywords
transistor
node
period
gate electrode
voltage
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Pending
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CN202111086735.7A
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English (en)
Inventor
金玄俊
姜章美
金慧玟
朴埈贤
郑珉在
表基贤
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Publication of CN114255708A publication Critical patent/CN114255708A/zh
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    • G09G2320/00—Control of display operating conditions
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
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    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
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    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
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Abstract

提供了具有内部补偿的显示装置和像素单元。显示装置包括连接到第一扫描线、第二扫描线、第三扫描线、数据线、第一发射控制线和第二发射控制线的像素。像素中的每个包括：发光元件；第一晶体管，连接在与第一电源连接的第一节点和与发光元件的阳极连接的第二节点之间，并且包括连接到第三节点的栅电极；第二晶体管，连接在数据线与第四节点之间，并且包括连接到第一扫描线的栅电极；第一电容器，连接在第二节点与第五节点之间；第二电容器，连接在第四节点与第五节点之间；第四晶体管，连接在第三节点与第五节点之间，并且包括连接到第二扫描线的栅电极；以及第六晶体管，连接在第三节点与第四节点之间，并且包括连接到第一发射控制线的栅电极。

Description

具有内部补偿的显示装置和像素单元
相关申请的交叉引用
本申请要求于2020年9月25日向韩国知识产权局提交的第10-2020-0125224号韩国专利申请的优先权，通过引用并入该韩国专利申请的全部内容。
技术领域
本公开总体上涉及显示装置，并且更具体地涉及具有内部补偿的显示装置。
背景技术
随着信息技术的发展，可提供用户与信息之间的连接媒介的显示装置的作用越来越受到重视。响应于此，诸如液晶显示装置、有机发光显示装置等的显示装置的使用日益增加。
显示装置可包括连接到扫描线和数据线的像素、用于驱动扫描线的扫描驱动器和用于驱动数据线的数据驱动器。每个像素可包括像素电路，像素电路包括晶体管、电容器和发光元件。当从扫描线供给扫描信号时，像素电路可从数据线接收数据电压并且根据数据电压将驱动晶体管的电流供给到发光元件。发光元件可发射具有对应于驱动晶体管的电流的强度的光。
在存在工艺偏差、劣化等情况下，由于像素之间的驱动晶体管的电特性(诸如，阈值电压)的偏差，可能无法准确地实现期望的像素灰度值。因此，内部补偿方法可用于补偿像素内部的驱动晶体管的电特性的偏差，和/或外部补偿方法可用于补偿像素外部的驱动晶体管的电特性的偏差。
发明内容
内部补偿方法可包括在源极跟随器方法中设置驱动晶体管的栅-极电压。源极跟随器内部补偿方法可在调节驱动晶体管的栅极电位的同时，朝着栅极电位升高源极电位，以补偿驱动晶体管的电特性的偏差。
在源极跟随器型的像素中，当另一电容器连接到布置在驱动晶体管的栅电极与源电极之间的存储电容器时，存储电容器的两端之间的电压差可根据两个电容器之间的电容比而改变。当存储电容器的两端之间的电压差减小时，为了实现期望的灰度值，可向像素供给更大的数据电压。
本公开的实施方式提供了一种能够防止由于电容器而引起的数据电压的损失或劣化的像素。本公开的另一实施方式提供了一种能够通过充分确保用于补偿驱动晶体管的诸如阈值电压的电特性的偏差的时段来进行高分辨率和高速驱动的像素。然而，本公开的实施方式不限于上述实施方式，并且可在不脱离本公开的范围和精神的情况下进行各种适配或扩展。
根据本公开的实施方式的显示装置可包括连接到第一扫描线、第二扫描线、第三扫描线、数据线、第一发射控制线和第二发射控制线的多个像素。多个像素中的每个可包括：发光元件；第一晶体管，连接在与第一电源连接的第一节点和与发光元件的阳极连接的第二节点之间，并且包括连接到第三节点的栅电极；第二晶体管，连接在数据线与第四节点之间，并且包括连接到第一扫描线的栅电极；第一电容器，连接在第二节点与第五节点之间；第二电容器，连接在第四节点与第五节点之间；第四晶体管，连接在第三节点与第五节点之间，并且包括连接到第二扫描线的栅电极；以及第六晶体管，连接在第三节点与第四节点之间，并且包括连接到第一发射控制线的栅电极。显示装置还可包括：第三晶体管，连接在第三节点与第三电源之间，并且包括连接到第二扫描线的栅电极。显示装置还可包括：第五晶体管，连接在第二节点与第四电源之间，并且包括连接到第三扫描线的栅电极。显示装置还可包括：第七晶体管，连接在第一节点与第一电源之间，并且包括连接到第二发射控制线的栅电极。
显示装置还可包括非发射时段和发射时段，非发射时段包括：初始化时段，在初始化时段中第二节点由第四电源初始化并且第五节点由第三电源初始化；补偿时段，在补偿时段中第一晶体管的阈值电压被补偿；以及数据写入时段，在数据写入时段中通过数据线施加的数据电压供给到第三节点，在发射时段中发光元件响应于数据电压发射光。数据写入时段可与补偿时段重叠，并且在补偿时段期间，可由第三电源来保持第五节点的电压。
第一晶体管至第七晶体管可以是N型薄膜晶体管，栅极导通电压可具有逻辑高电平，并且栅极关断电压可具有逻辑低电平。第三晶体管和第四晶体管可在初始化时段、补偿时段和数据写入时段期间保持在导通状态中，并且第五晶体管可在初始化时段期间导通。在补偿时段期间，第七晶体管可保持在导通状态中。
在补偿时段期间，第二节点的电压可收敛于第三电源与第一晶体管的阈值电压之间的电压差，并且在补偿时段期间，第一电容器的两端之间的电压差可对应于第一晶体管的阈值电压。数据写入时段可与补偿时段重叠，并且第二晶体管可在数据写入时段期间导通。在数据写入时段期间，第二电容器的两端之间的电压差可以是数据电压与第三电源之间的差值。
在发射时段期间，第一电容器和第二电容器可串联连接在第二节点与第三节点之间。在发射时段期间，第六晶体管和第七晶体管可保持在导通状态中，并且第四晶体管可保持在关断状态中。发光元件的阴极可连接到第二电源。
根据本公开的实施方式的像素单元可包括多个像素，每个像素包括：发光元件，包括连接到第二电源的阴极；第一晶体管，包括第一电极、连接到发光元件的阳极的第二电极和栅电极；第三晶体管，包括连接到第三电源的第一电极、连接到第一晶体管的栅电极的第二电极和连接到第二扫描线的栅电极；第四晶体管，包括连接到第一晶体管的栅电极的第一电极、第二电极和连接到第二扫描线的栅电极；第一电容器，连接在第一晶体管的第二电极与第四晶体管的第二电极之间；以及第七晶体管，包括连接到第一电源的第一电极、连接到第一晶体管的第一电极的第二电极和连接到第二发射控制线的栅电极。第一晶体管的栅电极可连接第三晶体管的第二电极和第四晶体管的第一电极。
每个像素还可包括第二晶体管，第二晶体管包括连接到数据线的第一电极、第二电极和连接到第一扫描线的栅电极。每个像素还可包括第二电容器，第二电容器连接在第二晶体管的第二电极与第四晶体管的第二电极之间。每个像素还可包括：第五晶体管，包括连接到第一晶体管的第二电极的第一电极、连接到第四电源的第二电极以及连接到第三扫描线的栅电极；以及第六晶体管，包括连接到第二晶体管的第二电极的第一电极、连接到第一晶体管的栅电极的第二电极和连接到第一发射控制线的栅电极。第一晶体管至第七晶体管可以是P型薄膜晶体管，栅极导通电压可具有逻辑低电平，并且栅极关断电压可具有逻辑高电平。
附图说明
被包括以提供对本发明构思的进一步理解的附图，被并入并且构成本说明书的一部分，示出了本发明构思的实施方式，并且与描述一起用于解释本发明构思的原理。
图1是示出根据本公开的实施方式的显示装置的框图；
图2是用于解释根据本公开的实施方式的像素的电路图；
图3是示出供给到图2的像素的驱动信号的示例的时序图；
图4是用于解释在初始化时段中的像素的操作的混合的电路和时序图；
图5是用于解释在补偿时段中的像素的操作的混合的电路和时序图；
图6是用于解释在数据写入时段中的像素的操作的混合的电路和时序图；以及
图7是用于解释在发射时段中的像素的操作的混合的电路和时序图。
具体实施方式
将参照附图详细描述本公开的实施方式。在图中，相同或相似的附图标记可用于相同或相似的元件，并且可省略针对相同或相似元件的重复描述。
图1示出了根据本公开的实施方式的显示装置。
参照图1，显示装置1000可包括像素单元100、扫描驱动器200、发射驱动器300、数据驱动器400和时序控制器500。驱动器和/或控制器中的每个可实现为一个或多个电路。替代性地，驱动器和/或控制器中的一个或多个可组合在集成电路中。
在实施方式中，显示装置1000还可包括电力供给单元，电力供给单元用于向像素单元100供给第一电源VDD、第二电源VSS、第三电源Vref和第四电源Vint的电压。然而，这是示例，并且第一电源VDD、第二电源VSS、第三电源Vref和第四电源Vint中的至少一个可从时序控制器500或数据驱动器400供给。
像素单元100可包括多个第一扫描线SL11至SL1n、多个第二扫描线SL21至SL2n、多个第三扫描线SL31至SL3n、多个第一发射控制线EL11至EL1n、多个第二发射控制线EL21至EL2n、多个数据线DL1至DLm、以及连接到第一扫描线SL11至SL1n、第二扫描线SL21至SL2n、第三扫描线SL31至SL3n、第一发射控制线EL11至EL1n、第二发射控制线EL21至EL2n以及数据线DL1至DLm的多个(例如，n×m的矩阵)像素PX，其中n和m可以是大于1的整数。像素PX中的每个可包括驱动晶体管和多个开关晶体管。
扫描驱动器200可基于诸如扫描控制信号SCS的第一控制信号，通过第一扫描线SL11至SL1n、第二扫描线SL21至SL2n和第三扫描线SL31至SL3n向像素PX顺序地供给扫描信号。扫描驱动器200可从时序控制器500接收第一控制信号、至少一个时钟信号等。
在实施方式中，在一个帧时段中供给到一个扫描线的扫描信号可包括至少一个扫描脉冲。例如，扫描信号可包括顺序地供给到第一扫描线SL11至SL1n的第一扫描信号SS1(参见图2)、顺序地供给到第二扫描线SL21至SL2n的第二扫描信号SS2(参见图2)以及顺序地供给到第三扫描线SL31至SL3n的第三扫描信号SS3(参见图2)。
第一扫描信号SS1可包括至少一个第一扫描脉冲，第二扫描信号SS2可包括至少一个第二扫描脉冲，并且第三扫描信号SS3可包括至少一个第三扫描脉冲。这里，第一扫描脉冲、第二扫描脉冲和第三扫描脉冲可以是用于导通包括在像素PX中的晶体管的栅极导通电压。例如，当包括在像素PX中的晶体管是P沟道金属氧化物半导体(PMOS)晶体管(例如，P型)时，栅极导通电压可设置为逻辑低电平，并且栅极关断电压可设置为逻辑高电平。当包括在像素PX中的晶体管是N沟道金属氧化物半导体(NMOS)晶体管(例如，N型)时，栅极导通电压可设置为逻辑高电平，并且栅极关断电压可设置为逻辑低电平。在替代实施方式中，晶体管中的一些可以是N型并且其它晶体管可以是P型，但不限于此。
在实施方式中，扫描驱动器200可包括：依赖地彼此连接以便将包括第一扫描脉冲的第一扫描信号SS1顺序地输出到第一扫描线SL11至SL1n的第一级、依赖地彼此连接以便将包括第二扫描脉冲的第二扫描信号SS2顺序地输出到第二扫描线SL21至SL2n的第二级以及依赖地彼此连接以便将包括第三扫描脉冲的第三扫描信号SS3顺序地输出到第三扫描线SL31至SL3n的第三级。
发射驱动器300可基于诸如发射控制信号ECS的第二控制信号，通过第一发射控制线EL11至EL1n和第二发射控制线EL21至EL2n向像素PX顺序地供给发射控制信号。发射驱动器300可从时序控制器500接收第二控制信号、时钟信号等。每个发射控制信号可针对位于相同的水平线或行上的像素PX将一个帧时段划分为发射时段和非发射时段。
在实施方式中，发射控制信号可包括顺序地供给到第一发射控制线EL11至EL1n的第一发射控制信号EM1(参见图2)和顺序地供给到第二发射控制线EL21至EL2n的第二发射控制信号EM2(参见图2)。
数据驱动器400可从时序控制器500接收诸如数据控制信号DCS的第三控制信号和诸如红-绿-蓝RGB的图像数据。数据驱动器400可基于第三控制信号和图像数据，通过数据线DL1至DLm将诸如数据电压的数据信号供给到像素PX。在实施方式中，数据驱动器400可将与图像的灰度值对应的数据信号供给到数据线DL1至DLm。例如，对应的像素PX的数据信号可与包括第一扫描脉冲的每个第一扫描信号SS1同步地供给到对应的像素PX。
时序控制器500可基于从外部供给的时序信号来控制扫描驱动器200、发射驱动器300和数据驱动器400的驱动。时序控制器500可向扫描驱动器200供给包括第一控制信号、扫描时钟信号等的控制信号，并且可向发射驱动器300供给包括第二控制信号、发射控制时钟信号等的控制信号。控制数据驱动器400的第三控制信号可包括源极起始信号、源极输出使能信号、源极采样时钟等。
图2示出了根据本公开的实施方式的像素。为了解释的便利，在第i行和第j列中布置的像素PX将被描述为示例，其中i和j可以是大于1的自然数。
参照图1和图2，像素PX可包括像素电路PXC和连接到像素电路PXC的发光元件LD。像素电路PXC可响应于数据电压Vdata来控制从第一电源VDD经由发光元件LD流向第二电源VSS的电流量。第一电源VDD可设置为高于第二电源VSS的电压。发光元件LD的阳极可连接到像素电路PXC，并且阴极可连接到第二电源VSS。发光元件LD可响应于从像素电路PXC供给的电流量而生成具有预定亮度的光。
在替代实施方式中，发光元件LD的阳极可连接到第一电源VDD，并且阴极可连接到像素电路PXC。
根据实施方式的像素电路PXC可包括第一晶体管TR1至第七晶体管TR7、第一电容器C1和第二电容器C2。
第一晶体管TR1可包括连接到第一节点N1的第一电极、连接到第二节点N2的第二电极和连接到第三节点N3的栅电极。第一电极可经由第七晶体管TR7连接到第一电源VDD，并且第二电极可连接到发光元件LD的阳极。栅电极可经由第二晶体管TR2和第六晶体管TR6连接到第j数据线DLj。
根据实施方式，第一电极可以是第一晶体管TR1的漏电极，并且第二电极可以是第一晶体管TR1的源电极。第一晶体管TR1可向发光元件LD供给与第三节点N3(诸如，栅电极)的电压对应的驱动电流。即，第一晶体管TR1可用作像素PX的驱动晶体管。
第二晶体管TR2可包括连接到第j数据线DLj的第一电极、连接到第四节点N4的第二电极和连接到第一第i扫描线SL1i的栅电极。栅电极可通过第一第i扫描线SL1i接收第一扫描信号SS1。当第二晶体管TR2由第一扫描信号SS1导通时，数据电压Vdata可传输到第四节点N4。
第三晶体管TR3可包括连接到第三电源Vref的第一电极、连接到第三节点N3的第二电极和连接到第二第i扫描线SL2i的栅电极。栅电极可通过第二第i扫描线SL2i接收第二扫描信号SS2。当第三晶体管TR3由第二扫描信号SS2导通时，第三电源Vref可传输到第三节点N3。在这种情况下，第三电源Vref可设置为具有基本上DC分量的特定电压。
第四晶体管TR4可包括连接到第三节点N3的第一电极、连接到第五节点N5的第二电极和连接到第二第i扫描线SL2i的栅电极。栅电极可通过第二第i扫描线SL2i接收第二扫描信号SS2。当第四晶体管TR4由第二扫描信号SS2导通时，第三节点N3的电压，诸如第三电源Vref，可传输到第五节点N5。
第五晶体管TR5可包括连接到第二节点N2的第一电极、连接到第四电源Vint的第二电极和连接到第三第i扫描线SL3i的栅电极。栅电极可通过第三第i扫描线SL3i接收第三扫描信号SS3。当第五晶体管TR5由第三扫描信号SS3导通时，第四电源Vint可传输到第二节点N2。在这种情况下，第四电源Vint可以是接地电压。然而，第四电源Vint不限于此，并且可像第三电源Vref一样，设置为具有基本上DC分量的特定电压。
第六晶体管TR6可包括连接到第四节点N4的第一电极、连接到第三节点N3的第二电极和连接到第一第i发射控制线EL1i的栅电极。栅电极可通过第一第i发射控制线EL1i接收第一发射控制信号EM1。当第六晶体管TR6由第一发射控制信号EM1导通时，第四节点N4的电压，诸如数据电压Vdata，可传输到第三节点N3。
第七晶体管TR7可包括连接到第一电源VDD的第一电极、连接到第一节点N1的第二电极和连接到第二第i发射控制线EL2i的栅电极。栅电极可通过第二第i发射控制线EL2i接收第二发射控制信号EM2。当第七晶体管TR7由第二发射控制信号EM2导通时，第一电源VDD可传输到第一节点N1。
第一电容器C1可连接在第二节点N2与第五节点N5之间。在这种情况下，第五节点N5可经由第四晶体管TR4连接到第一晶体管TR1的栅电极。即，第一电容器C1可连接在第一晶体管TR1的栅电极与源电极(诸如，第二电极)之间。第一电容器C1可存储根据像素PX的操作时序而改变的第二节点N2的电压与第三节点N3的电压之间的电压差。
第二电容器C2可连接在第四节点N4与第五节点N5之间。在这种情况下，第四节点N4可经由第二晶体管TR2连接到第j数据线DLj。即，第二电容器C2可连接在第j数据线DLj与第五节点N5之间。第二电容器C2可存储通过第j数据线DLj施加的数据电压Vdata。此后，当第六晶体管TR6导通时，数据电压Vdata可提供给第三节点N3，诸如第一晶体管TR1的栅电极。
发光元件LD可连接在第二节点N2与第二电源VSS之间。发光元件LD的阴极可接收第二电源VSS。第一电源VDD和第二电源VSS可具有不同的电位。作为示例，第一电源VDD可设置为高电位电源，并且第二电源VSS可设置为低电位电源。在这种情况下，在像素PX的发射时段期间，第一电源VDD与第二电源VSS之间的电位差可设置为大于或等于发光元件LD的阈值电压。
图3示出了供给到图2的像素的驱动信号的示例。
参照图1、图2和图3，显示装置1000的一个帧时段可包括发射时段EP和非发射时段NEP。在这种情况下，虽然包括在一个帧时段中的非发射时段NEP被示出为比发射时段EP长，但是应理解的是，发射时段EP的长度实际上可比非发射时段NEP的长度长。
非发射时段NEP可以是从第一时间点t1至第九时间点t9的时段，并且可限定为像素PX实质上不发射光的时段。发射时段EP可以是从第九时间点t9到下一帧开始之前的第十时间点t10的时段，并且可限定为像素PX响应于接收的数据信号而实质上发射光的时段。第二扫描信号SS2可在第二时间点t2从逻辑低电平改变为逻辑高电平。
显示装置1000的非发射时段NEP可包括用于在非发射时段NEP期间初始化第一晶体管TR1的源电极(诸如，第二电极)和栅电极的初始化时段P1、用于补偿第一晶体管TR1的诸如阈值电压Vth的电特性的补偿时段P2以及用于向第一晶体管TR1的栅电极写入数据信号的数据写入时段P3。在这种情况下，初始化时段P1可对应于从第三时间点t3至第四时间点t4的时段，补偿时段P2可对应于从第五时间点t5至第八时间点t8的时段，并且数据写入时段P3可对应于从第六时间点t6至第七时间点t7的时段。
根据本公开的实施方式，在初始化时段P1中，第一晶体管TR1的栅电极可由第三电源Vref初始化，并且源电极(诸如，第二电极)可由第四电源Vint初始化。
在补偿时段P2中，第一晶体管TR1的源电极(诸如，第二电极)的电压Vs可收敛于第三电源Vref与第一晶体管TR1的阈值电压Vth之间的差值，即，Vs＝Vref-Vth。此时，由于第一晶体管TR1的栅电极的电压Vg可对应于第三电源Vref，所以第一晶体管TR1的阈值电压Vth可存储在第一电容器C1中。
在数据写入时段P3中，与数据信号对应的数据电压Vdata可存储在第二电容器C2中。
在发射时段EP中，可响应于第一晶体管TR1的栅电极(诸如，第三节点N3)的电压Vg从第一晶体管TR1向发光元件LD供给预定电流。在这种情况下，发光元件LD可响应于从第一晶体管TR1供给的电流量而生成具有预定亮度的光。
以下可参照图4至图7进一步描述在时段P1、P2、P3和EP中的每个中的像素PX的详细操作。
图4示出了在初始化时段中的像素的操作。
参照图4，在初始化时段P1中，第一发射控制信号EM1和第二发射控制信号EM2可各自具有逻辑低电平，第一扫描信号SS1可具有逻辑低电平，第二扫描信号SS2可具有逻辑高电平，并且第三扫描信号SS3可从逻辑低电平改变为逻辑高电平。相应地，第一电容器C1可由第三电源Vref和第四电源Vint初始化。
具体地，由于第三晶体管TR3和第四晶体管TR4在初始化时段P1期间处于导通状态中，所以第三电源Vref可供给到第三节点N3和第五节点N5。此外，由于第五晶体管TR5在初始化时段P1期间处于导通状态中，所以第四电源Vint可供给到第二节点N2。结果，第一电容器C1可由与第三电源Vref和第四电源Vint之间的差对应的电压初始化。在这种情况下，由于第六晶体管TR6和第七晶体管TR7在初始化时段P1期间处于关断状态中，所以发光元件LD可保持非发射状态。
图5示出了在补偿时段中的像素的操作。
参照图5，在补偿时段P2中，第一发射控制信号EM1可具有逻辑低电平，第二发射控制信号EM2可从逻辑低电平改变为逻辑高电平，第一扫描信号SS1可具有逻辑低电平，第二扫描信号SS2可具有逻辑高电平，并且第三扫描信号SS3可具有逻辑低电平。相应地，与第一晶体管TR1的阈值电压Vth对应的电压可通过第一电源VDD和第三电源Vref存储在第一电容器C1中。
具体地，在第一晶体管TR1导通的同时，第五晶体管TR5可关断，并且第三晶体管TR3和第四晶体管TR4可保持在导通状态中。相应地，第三电源Vref可供给到第三节点N3，诸如第一晶体管TR1的栅电极，并且第二节点N2，诸如第一晶体管TR1的源电极，可通过关断的第五晶体管TR5而被电浮置。相应地，第一晶体管TR1可由第三节点N3(诸如，第一晶体管TR1的栅电极)的第三电源Vref导通，以作为源极跟随器操作，并且可在源极电压是通过从第三电源Vref减去第一晶体管TR1的阈值电压Vth而获得的电压Vref-Vth时关断，并且因此，与第一晶体管TR1的阈值电压Vth对应的电压(诸如，补偿电压)可充电在第一电容器C1中。即，第一电容器C1可充电有等于第三电源Vref与第一晶体管TR1的阈值电压Vth之间的差的电压或接近第一晶体管TR1的阈值电压Vth的电压。
图6示出了数据写入时段中的像素的操作。
参照图6，在数据写入时段P3中，第一发射控制信号EM1可具有逻辑低电平，第二发射控制信号EM2可具有逻辑高电平，第一扫描信号SS1可从逻辑低电平改变为逻辑高电平，第二扫描信号SS2可具有逻辑高电平，并且第三扫描信号SS3可具有逻辑低电平。相应地，数据电压Vdata可存储在第二电容器C2中。
具体地，由于第三晶体管TR3和第四晶体管TR4在数据写入时段P3期间处于导通状态中，所以第三电源Vref仍然可供给到第五节点N5。此外，由于第六晶体管TR6在数据写入时段P3期间处于关断状态中，因此第三节点N3与第四节点N4可被电开路。由于第二晶体管TR2处于导通状态中，通过第j数据线DLj接收的数据电压Vdata可供给到第四节点N4。即，第二电容器C2可充电有等于第三电源Vref与第四节点N4的电压之间的差的电压或者接近数据电压Vdata的电压。
这样，尽管数据写入时段P3与补偿时段P2重叠，但是补偿操作和数据写入操作能通过在补偿时段P2期间向串联连接的第一电容器C1与第二电容器C2之间的中间节点持续供给第三电源Vref而分开。即，由于第五节点N5用作接地节点，因此能通过第一电容器C1补偿第一晶体管TR1的阈值电压Vth，并且同时，能通过第二电容器C2写入数据电压Vdata。相应地，由于根据本公开的实施方式的像素PX能确保足够的补偿时段P2，因此能预期以高分辨率和高速来驱动显示装置1000的效果。
图7示出了在发射时段中的像素的操作。
参照图7，在发射时段EP中，第一发射控制信号EM1和第二发射控制信号EM2可具有逻辑高电平，并且第一扫描信号SS1、第二扫描信号SS2和第三扫描信号SS3可具有逻辑低电平。相应地，发光元件LD可通过第一电源VDD以及第一电容器C1和第二电容器C2的电压而发射光。
由于第六晶体管TR6在发射时段EP期间处于导通状态中，所以可将存储在第二电容器C2中的数据电压Vdata供给到第三节点N3，诸如第一晶体管TR1的栅电极。此外，由于第七晶体管TR7处于导通状态中，所以第一电源VDD可供给到第一节点N1，诸如第一晶体管TR1的漏电极。然后，第一晶体管TR1可响应于第三节点N3(诸如，第一晶体管TR1的栅电极)的电压而控制从第一电源VDD经由发光元件LD流向第二电源VSS的电流量。相应地，在发射时段EP期间，发光元件LD可响应于从第一晶体管TR1供给的电流量而生成具有预定亮度的光。在发射时段EP期间，从第一晶体管TR1供给到发光元件LD的电流Ids可如下面的等式中所示地设置。在这种情况下，第一晶体管TR1的栅电极的电压Vg可以是Vdata[V]，并且源电极的电压Vs可以是Vref-Vth[V]。
[等式1]
Ids＝k(Vgs-Vth)2＝k(Vdata-(Vref-Vth)-Vth)2＝k(Vdata-Vref)2
这里，k表示常数，并且Vgs表示作为第一晶体管TR1的栅电极的电压Vg与源电极的电压Vs之间的电压差的第一晶体管TR1的栅-源电压。
参照以上等式，可与数据电压Vdata与第三电源Vref之间的电压差对应地确定从第一晶体管TR1供给到发光元件LD的电流Ids。由于第三电源Vref是固定电压，所以可与数据电压Vdata对应地确定供给到发光元件LD的电流Ids。
如等式中所示的，可与第一电源VDD和第一晶体管TR1的阈值电压Vth无关地确定供给到发光元件LD的电流Ids。相应地，在本公开中，可与第一电源VDD的电压降和第一晶体管TR1的阈值电压Vth的偏差无关地将电流Ids供给到发光元件LD。相应地，能确保显示装置1000的显示品质的可靠性。
此外，在发射时段EP期间，由于第一电容器C1和第二电容器C2串联连接在第二节点N2(诸如，第一晶体管TR1的源电极)与第三节点N3(诸如，第一晶体管TR1的栅电极)之间，能防止第一晶体管TR1的栅-源电压Vgs根据电容器之间的电容比而改变的现象。即，能防止数据电压Vdata的损失。
结果，由于不需要向像素PX供给更大的数据电压Vdata来补偿损失的数据电压Vdata(即，由于数据摆动范围不增加)，因此可实现降低驱动显示装置1000所需的功耗的效果。
在根据本公开的实施方式的像素中，能通过向串联连接的电容器的中间节点施加具有DC分量的基准电压来防止由于电容器而引起的数据电压的损失。
根据本公开的实施方式，像素可用N型薄膜晶体管来实现，并且具有DC分量的基准电压可施加到串联连接的电容器的中间节点。因此，能通过充分确保用于补偿驱动晶体管的诸如阈值电压的电特性的偏差的时段来实现高分辨率和高速驱动。
然而，根据本公开的效果不限于上述效果，并且可在不脱离本公开的精神和范围的情况下进行各种扩展。例如，在替代实施方式中，第一晶体管至第七晶体管可以是P型薄膜晶体管，栅极导通电压可具有逻辑低电平，并且栅极关断电压可具有逻辑高电平。
以上已参照图描述了本公开的实施方式。然而，本公开所属的相关领域的普通技术人员将领会的是，在不脱离如随附的权利要求书中阐述的本发明构思的范围和精神的情况下，能对所公开的实施方式进行各种修改和改变。

Claims (20)

1.一种显示装置，包括：
多个像素，连接到第一扫描线、第二扫描线、第三扫描线、数据线、第一发射控制线和第二发射控制线，
其中，所述多个像素中的每个包括：
发光元件；
第一晶体管，连接在与第一电源联接的第一节点和与所述发光元件的阳极联接的第二节点之间，并且包括连接到第三节点的栅电极；
第二晶体管，连接在所述数据线与第四节点之间，并且包括连接到所述第一扫描线的栅电极；
第一电容器，连接在所述第二节点与第五节点之间；
第二电容器，连接在所述第四节点与所述第五节点之间；
第四晶体管，连接在所述第三节点与所述第五节点之间，并且包括连接到所述第二扫描线的栅电极；以及
第六晶体管，连接在所述第三节点与所述第四节点之间，并且包括连接到所述第一发射控制线的栅电极。
2.如权利要求1所述的显示装置，还包括：
第三晶体管，连接在所述第三节点与第三电源之间，并且包括连接到所述第二扫描线的栅电极。
3.如权利要求2所述的显示装置，还包括：
第五晶体管，连接在所述第二节点与第四电源之间，并且包括连接到所述第三扫描线的栅电极。
4.如权利要求3所述的显示装置，还包括：
第七晶体管，连接在所述第一节点与所述第一电源之间，并且包括连接到所述第二发射控制线的栅电极。
5.如权利要求4所述的显示装置，还包括：
非发射时段，包括：初始化时段，在所述初始化时段中所述第二节点由所述第四电源初始化并且所述第五节点由所述第三电源初始化；补偿时段，在所述补偿时段中所述第一晶体管的阈值电压被补偿；以及数据写入时段，在所述数据写入时段中通过所述数据线施加的数据电压供给到所述第三节点；以及
发射时段，在所述发射时段中所述发光元件响应于所述数据电压发射光。
6.如权利要求5所述的显示装置，
其中，所述数据写入时段与所述补偿时段重叠，并且
其中，在所述补偿时段期间，由所述第三电源来保持所述第五节点的电压。
7.如权利要求5所述的显示装置，其中，所述第一晶体管至所述第七晶体管是N型薄膜晶体管，栅极导通电压具有逻辑高电平，并且栅极关断电压具有逻辑低电平。
8.如权利要求5所述的显示装置，
其中，所述第三晶体管和所述第四晶体管在所述初始化时段、所述补偿时段和所述数据写入时段期间保持在导通状态中，并且
其中，所述第五晶体管在所述初始化时段期间导通。
9.如权利要求5所述的显示装置，其中，在所述补偿时段期间，所述第七晶体管保持在导通状态中。
10.如权利要求9所述的显示装置，
其中，在所述补偿时段期间，所述第二节点的电压收敛于所述第三电源与所述第一晶体管的所述阈值电压之间的电压差，并且
其中，在所述补偿时段期间，所述第一电容器的两端之间的电压差对应于所述第一晶体管的所述阈值电压。
11.如权利要求10所述的显示装置，
其中，所述数据写入时段与所述补偿时段重叠，并且
其中，所述第二晶体管在所述数据写入时段期间导通。
12.如权利要求11所述的显示装置，其中，在所述数据写入时段期间，所述第二电容器的两端之间的电压差是所述数据电压与所述第三电源之间的差值。
13.如权利要求5所述的显示装置，其中，在所述发射时段期间，所述第一电容器和所述第二电容器串联连接在所述第二节点与所述第三节点之间。
14.如权利要求13所述的显示装置，其中，在所述发射时段期间，所述第六晶体管和所述第七晶体管保持在导通状态中，并且所述第四晶体管保持在关断状态中。
15.如权利要求1所述的显示装置，其中，所述发光元件的阴极连接到第二电源。
16.一种像素单元，所述像素单元包括多个像素，每个像素包括：
发光元件，包括连接到第二电源的阴极；
第一晶体管，包括第一电极、连接到所述发光元件的阳极的第二电极和栅电极；
第三晶体管，包括连接到第三电源的第一电极、连接到所述第一晶体管的所述栅电极的第二电极和连接到第二扫描线的栅电极；
第四晶体管，包括连接到所述第一晶体管的所述栅电极的第一电极、第二电极和连接到所述第二扫描线的栅电极；
第一电容器，连接在所述第一晶体管的所述第二电极与所述第四晶体管的所述第二电极之间；以及
第七晶体管，包括连接到第一电源的第一电极、连接到所述第一晶体管的所述第一电极的第二电极和连接到第二发射控制线的栅电极，
其中，所述第一晶体管的所述栅电极连接所述第三晶体管的所述第二电极和所述第四晶体管的所述第一电极。
17.如权利要求16所述的像素单元，每个像素还包括：
第二晶体管，包括连接到数据线的第一电极、第二电极和连接到第一扫描线的栅电极。
18.如权利要求17所述的像素单元，每个像素还包括：
第二电容器，连接在所述第二晶体管的所述第二电极与所述第四晶体管的所述第二电极之间。
19.如权利要求18所述的像素单元，每个像素还包括：
第五晶体管，包括连接到所述第一晶体管的所述第二电极的第一电极、连接到第四电源的第二电极以及连接到第三扫描线的栅电极；以及
第六晶体管，包括连接到所述第二晶体管的所述第二电极的第一电极、连接到所述第一晶体管的所述栅电极的第二电极和连接到第一发射控制线的栅电极。
20.如权利要求19所述的像素单元，其中，所述第一晶体管至所述第七晶体管是P型薄膜晶体管，栅极导通电压具有逻辑低电平，并且栅极关断电压具有逻辑高电平。
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