CN114242788A - 一种埋栅晶体管及其制造方法、半导体存储器件 - Google Patents
一种埋栅晶体管及其制造方法、半导体存储器件 Download PDFInfo
- Publication number
- CN114242788A CN114242788A CN202010939666.9A CN202010939666A CN114242788A CN 114242788 A CN114242788 A CN 114242788A CN 202010939666 A CN202010939666 A CN 202010939666A CN 114242788 A CN114242788 A CN 114242788A
- Authority
- CN
- China
- Prior art keywords
- layer
- gate
- metal layer
- barrier layer
- gate metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 72
- 239000002184 metal Substances 0.000 claims abstract description 72
- 230000004888 barrier function Effects 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000004020 conductor Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 32
- 230000008569 process Effects 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 12
- 238000001020 plasma etching Methods 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000003112 inhibitor Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- -1 tungsten nitride Chemical class 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims description 2
- 238000003860 storage Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 10
- 230000003071 parasitic effect Effects 0.000 description 8
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000012552 review Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明公开一种埋栅晶体管及其制造方法、半导体存储器件,涉及半导体制造技术领域,以提高半导体存储器件的性能。该埋栅晶体管应用于半导体存储器件,埋栅晶体管包括半导体衬底;位于衬底中的栅极沟槽;位于栅极沟槽内壁上的栅介质层;位于栅极沟槽下部中的栅导体层,栅导体层包括阻挡层和栅金属层,阻挡层的顶部低于栅金属层的顶部;以及位于栅导体层上的盖层;其中,阻挡层的顶面与盖层的底面之间形成空气侧墙。本发明提供的埋栅晶体管及其制造方法、半导体存储器件用于半导体存储器件的制造。
Description
技术领域
本发明涉及半导体制造技术领域,尤其涉及一种埋栅晶体管及其制造方法、半导体存储器件。
背景技术
在制造应用于半导体存储器件的埋栅晶体管的过程中,栅金属层通常埋设在晶体管的衬底中。
在半导体存储器件工作的过程中,栅金属层与有源接触部之间会形成寄生电容。随单元器件集成密度的增加,这些寄生电容的存在会造成阻容迟滞(RC Delay)的问题,从而影响半导体存储器件的性能。
发明内容
本发明的目的在于提供一种埋栅晶体管及其制造方法、半导体存储器件,以提高半导体存储器件的性能。
为了实现上述目的,本发明提供一种埋栅晶体管。该埋栅晶体管应用于半导体存储器件。所述埋栅晶体管包括:半导体衬底;位于所述衬底中的栅极沟槽;位于所述栅极沟槽内壁上的栅介质层;位于所述栅极沟槽下部中的栅导体层,所述栅导体层包括阻挡层和栅金属层,所述阻挡层的顶部低于所述栅金属层的顶部;以及位于所述栅导体层上的盖层;其中,所述阻挡层的顶面与所述盖层的底面之间形成空气侧墙。
与现有技术相比,本发明提供的埋栅晶体管设置有空气侧墙,而空气侧墙的介电常数小。当空气侧墙作为栅金属层与有源接触部之间的介电层时,可以削弱栅金属层与有源接触部之间产生的寄生电容,进而降低因寄生电容产生的阻容迟滞。此时,由于阻容迟滞的降低,可以减少半导体存储器件的电量损耗,提高刷新频率,进而提高半导体存储器件的性能。
本发明还提供一种埋栅晶体管的制造方法。该埋栅晶体管的制造方法包括:
提供半导体衬底;
在所述衬底上形成栅极沟槽;
在所述栅极沟槽内壁上形成栅介质层;
在所述栅极沟槽的下部形成阻挡层和栅金属层,并将所述阻挡层回刻至低于所述栅金属层的顶面;
在所述阻挡层和所述栅金属层上形成盖层;
其中,所述阻挡层的顶面与所述盖层的底面之间形成空气侧墙。
与现有技术相比,本发明提供的埋栅晶体管的制造方法的有益效果与上述技术方案所述埋栅晶体管的有益效果相同,在此不做赘述。
附图说明
此处所说明的附图用来提供对本发明的进一步理解,构成本发明的一部分,本发明的示意性实施例及其说明用于解释本发明,并不构成对本发明的不当限定。在附图中:
图1为现有技术制造埋栅晶体管时,提供一衬底的状态示意图;
图2为现有技术制造埋栅晶体管时,形成栅金属层后的状态示意图;
图3现有技术制造埋栅晶体管时,形成盖层后的状态示意图;
图4为本发明实施例提供的埋栅晶体管的结构示意图;
图5为本发明实施例制造埋栅晶体管时,提高一衬底的状态示意图;
图6为本发明实施例制造埋栅晶体管时,形成栅极沟槽的状态示意图;
图7为本发明实施例制造埋栅晶体管时,形成栅介质层的状态示意图;
图8为本发明实施例制造埋栅晶体管时,形成阻挡层和栅金属层的状态示意图;
图9为本发明实施例制造埋栅晶体管时,形成空气侧墙的状态示意图;
图10为本发明实施例制造埋栅晶体管时,形成盖层的状态示意图。
附图标记:
10-衬底, 11-栅极沟槽, 20-栅介质层,
30-阻挡层, 40-栅金属层, 50-空气侧墙,
60-盖层。
具体实施方式
为了便于清楚描述本发明实施例的技术方案,在本发明的实施例中,采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定,并且“第一”、“第二”等字样也并不限定一定不同。
需要说明的是,本发明中,“示例性的”或者“例如”等词用于表示作例子、例证或说明。本发明中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言,使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本发明中,“至少一个”是指一个或者多个,“多个”是指两个或两个以上。“和/或”,描述关联对象的关联关系,表示可以存在三种关系,例如,A和/或B,可以表示:单独存在A,同时存在A和B,单独存在B的情况,其中A,B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达,是指的这些项中的任意组合,包括单项(个)或复数项(个)的任意组合。例如,a,b或c中的至少一项(个),可以表示:a,b,c,a和b的结合,a和c的结合,b和c的结合,或a、b和c的结合,其中a,b,c可以是单个,也可以是多个。
在制造应用于半导体存储器件的埋栅晶体管的过程中,通常包括如下步骤:
如图1所示,提供一半导体衬底10。
如图2所示,在衬底10上刻蚀出栅极沟槽11,并在栅极沟槽11中依次形成栅介质层20、阻挡层30和栅金属层40。
如图3所示,在阻挡层30和栅金属层40的顶面形成盖层60。
当半导体存储器件工作时,如上所述制造的埋栅晶体管的栅金属层40与有源接触部等会形成较大的寄生电容。寄生电容的产生,导致半导体存储器件工作时存在较大的阻容迟滞,进而造成耗电量增加、刷新频率低的问题,影响半导体存储器件的性能。
为了解决上述技术问题,本发明实施例提供一种埋栅晶体管。图4示出一种本发明实施例提供的埋栅晶体管的结构示意图。该埋栅晶体管应用于半导体存储器件。
具体实施时,在本发明实施例提供的埋栅晶体管(具有栅金属层)上制造位线和电容器,从而获得半导体存储器件。为了便于半导体存储器件集成,可以将埋栅晶体管阵列布置。
如图4所示,本发明实施例提供的埋栅晶体管包括半导体衬底10;位于衬底10中的栅极沟槽11;位于栅极沟槽11内壁上的栅介质层20;位于栅极沟槽11下部中的栅导体层,栅导体层包括阻挡层30和栅金属层40,阻挡层30的顶部低于栅金属层4的顶部;以及位于栅导体层上的盖层60;其中,阻挡层30的顶面与盖层60的底面之间形成空气侧墙50。
由上可知,本发明实施例提供的埋栅晶体管设置有空气侧墙50,而空气侧墙50的介电常数小,当空气侧墙50作为栅金属层40与有源接触部之间的介电层时,可以削弱栅金属层40与有源接触部之间产生的寄生电容,进而降低因寄生电容产生的阻容迟滞。此时,由于阻容迟滞的降低,可以减少半导体存储器件的电量损耗,提高刷新频率,进而提高半导体存储器件的性能。
上述衬底10可以为硅、锗、镓砷化物、硅锗、陶瓷、绝缘体上半导体等半导体衬底,也可以为在半导体衬底上已经形成有半导体器件的衬底10,且不仅限于此。
上述栅极沟槽11,是指在衬底10的顶面向下刻蚀形成的栅极沟槽11。
上述栅介质层20覆盖栅极沟槽12的内壁,并环绕在栅导体层的外围,也就是说,栅介质层20设置在栅导体层的侧壁与衬底10之间,以及栅导体层的底表面与衬底10之间。栅介质层20可以为氧化硅层、热氧化物层或高介电常数层(高k层)。
上述栅金属层40位于栅极沟槽11下部中,其顶面低于衬底10的顶面,以使栅金属层40埋设在衬底10中。该栅金属层40的材料可以为钨,也可以为铜等电阻低的金属。
上述阻挡层30环绕在栅金属层40外周,可以防止栅金属层40的金属扩散到栅介质层20中,破坏器件的性能。在实际应用中,阻挡层30位于栅介质层20和栅金属层40之间,阻挡层30的顶面低于栅金属层40的顶面。该阻挡层30的材料可以为氮化钛、氮化钨等导电材料。
为了将栅金属层40与其上部电路结构隔离开,上述埋栅晶体管还可以包括盖层60。该盖层60设置在栅金属层40和扩散层30上方,并与衬底10的顶面相平齐。盖层60的材料可以选择绝缘材料,例如,氧化硅、氮化硅等。
上述阻挡层30的顶面、盖层60的底面、栅介质层20与栅金属层40合围形成空气侧墙50。此时,空气侧墙50位于栅金属层40的两侧。此时,阻挡层30与有源接触部(位线节点接触部、存储节点接触部)之间的距离,相对于没有设置空气侧墙50时,会大大增大,从而可以避免导电结构(有源接触部、阻挡层30)相互靠近引起的电干扰,进而避免电干扰产生的电流泄露。此外,空气侧墙50的设置,还可以避免有源接触部的物质扩散,减少漏电流。
上述阻挡层30可以为一层,也可以为两层、三层或更多层。当阻挡层30为多层时,可以设计至少一层阻挡层30的顶面低于栅金属层40的顶面,从而形成空气侧墙50。
上述阻挡层30与栅介质层20之间,阻挡层30与栅金属层40之间还可以具有驱动能力增强层。此时,可以提高沟道载流子的迁移率,从而可以提高半导体存储器件的电流驱动能力。该驱动能力增强层可以为半导体材料层。例如,衬底10为硅衬底时,驱动能力增强层可以为锗硅层。
本发明实施例还提供一种埋栅晶体管的制造方法。该埋栅晶体管的制造方法如下所述:
如图5所示,提供一半导体衬底10。
如图6所示,自衬底10的顶面向下刻蚀形成栅极沟槽11。具体实施时,可以先在衬底10的顶面形成光刻胶层,然后利用光刻工艺将栅极沟槽图案复制到光刻胶层上。此时,光刻胶层上具有与栅极沟槽图案相对应的孔洞,在光刻胶层的保护下,对衬底10进行刻蚀,也就是刻蚀孔洞位置暴露的衬底10,从而形成栅极沟槽11。具体的,刻蚀衬底10时,可以采用干法刻蚀、湿法刻蚀等工艺。
如图7所示,在栅极沟槽11的内壁形成栅介质层20,也就是在栅极沟槽11的内侧壁和底部形成栅介质层20。在实际应用中,形成栅介质层20的方法包括在衬底10上淀积栅介质薄膜,然后对栅极沟槽11内的栅介质薄膜进行各向异性刻蚀,从而在栅极沟槽11的侧壁和底部形成栅介质层20。淀积栅介质薄膜时,可以采用原子层淀积等台阶覆盖性能好的薄膜形成方法。
如图8所示,在栅极沟槽11的下部形成阻挡层30。在阻挡层30围合成的空间内形成栅金属层40。此时,阻挡层30和栅介质层20均环绕在栅金属层40外围。阻挡层30的顶面和栅金属层40的顶面均低于衬底10的顶面。阻挡层30和栅金属层40均可以利用薄膜淀积工艺和刻蚀工艺形成。
如图9所示,将阻挡层30回刻至低于栅金属层40的顶面;阻挡层30的顶面与盖层60的底面之间形成空气侧墙50。具体的,阻挡层30、栅金属层40、栅介质层20以及下述的盖层60合围的空间为空气侧墙50。此时,空气侧墙50位于栅介质层20与栅金属层40之间,空气侧墙50环绕栅金属层40侧面。
刻蚀阻挡层30形成空气侧墙50后,剩余的阻挡层30为支撑层,起到支撑栅金属层40的作用。为了确保剩余足够多的支撑层,防止栅金属层40倒塌,可以设置合理的刻蚀时间和刻蚀工艺,避免刻蚀过多、刻蚀过快。在实际应用中,刻蚀阻挡层30时,可以采用湿法刻蚀工艺,也可以干法刻蚀工艺。
当采用湿法刻蚀工艺刻蚀阻挡层30时,可以使用H2O2刻蚀溶液刻蚀阻挡层30。具体实施时,该刻蚀溶液的温度为25℃~100℃。刻蚀溶液的体积浓度为1%~37%。为了防止刻蚀溶液刻蚀掉栅金属层40,该刻蚀溶液可以包括栅金属层材料刻蚀抑制剂、栅金属层材料钝化剂等。
例如,当栅金属层40的材料为钨,阻挡层30为氮化钛时,刻蚀溶液为包含钨刻蚀抑制剂的H2O2溶液。刻蚀溶液的温度可以为25℃、32℃、41℃、56℃、63℃、78℃、85℃、96℃、100℃等。刻蚀溶液的体积浓度可以为1%、8%、15%、24%、29%、32%、37%等。
当采用干法刻蚀工艺刻蚀阻挡层30时,可以使用等离子体刻蚀工艺刻蚀该阻挡层30。具体实施时,刻蚀气体可以为NF3、He和H2的混合气体,等离子体刻蚀工艺的射频功率可以为100W~300W,等离子体刻蚀工艺的工作温度可以为100℃~300℃。此时,在等离子体刻蚀设备中,NF3和He可以产生氟自由基,混合H2可以提高刻蚀选择比。
示例性的,等离子体刻蚀工艺的射频功率可以为100W、134W、164W、210W、240W、280W、300W,等离子体刻蚀工艺的工作温度可以为100℃、140℃、165℃、180℃、230℃、250℃、270℃、300℃。
如图10所示,在栅金属层40和空气侧墙50上方形成盖层60,以将栅金属层40与上部电路结构隔离开。在实际应用中,可以采用薄膜淀积和平坦化工艺在栅金属层40和空气侧墙50上方形成盖层60。
在实际应用中,为了避免淀积形成盖层60的过程中,盖层物质过多的进入栅金属层40和栅介质层20之间,也就是说,为了避免盖层物质进入填充空气侧墙50,可以采用台阶覆盖性能较差的工艺形成盖层。例如,可以采用物理气相淀积工艺形成盖层。也可以采用常压化学气相淀积工艺形成盖层。
本发明实施例还提供一种半导体存储器件。该半导体存储器件包括至少一个上述技术方案记载的埋栅晶体管。具体的,该埋栅晶体管位于半导体存储器件的有源区。
与现有技术相比,本发明实施例提供的半导体存储器件的有益效果与上述技术方案所述的埋栅晶体管的有益效果相同,在此不做赘述。
本发明实施例还提供一种电子设备。该电子设备包括上述的半导体存储器件。电子设备包括通信设备或移动终端。
与现有技术相比,本发明实施例提供的电子设备的有益效果与上述技术方案所述的半导体器件的制造方法的有益效果相同,在此不做赘述。
尽管在此结合各实施例对本发明进行了描述,然而,在实施所要求保护的本发明过程中,本领域技术人员通过查看附图、公开内容、以及所附权利要求书,可理解并实现公开实施例的其他变化。在权利要求中,“包括”(comprising)一词不排除其他组成部分或步骤,“一”或“一个”不排除多个的情况。相互不同的从属权利要求中记载了某些措施,但这并不表示这些措施不能组合起来产生良好的效果。
尽管结合具体特征及其实施例对本发明进行了描述,显而易见的,在不脱离本发明的精神和范围的情况下,可对其进行各种修改和组合。相应地,本说明书和附图仅仅是所附权利要求所界定的本发明的示例性说明,且视为已覆盖本发明范围内的任意和所有修改、变化、组合或等同物。显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包括这些改动和变型在内。
Claims (10)
1.一种埋栅晶体管,其特征在于,应用于半导体存储器件,所述埋栅晶体管包括:
半导体衬底;
位于所述衬底中的栅极沟槽;
位于所述栅极沟槽内壁上的栅介质层;
位于所述栅极沟槽下部中的栅导体层,所述栅导体层包括阻挡层和栅金属层,所述阻挡层的顶面低于所述栅金属层的顶面;
位于所述栅导体层上的盖层;
其中,所述阻挡层的顶面与所述盖层的底面之间形成空气侧墙。
2.根据权利要求1所述的埋栅晶体管,其特征在于,所述空气侧墙位于所述栅金属层的两侧,所述空气侧墙为所述阻挡层的顶面、所述盖层的底面、所述栅介质层与所述栅金属层合围的空间。
3.根据权利要求1所述的埋栅晶体管,其特征在于,所述阻挡层的材料为氮化钛或氮化钨;和/或,
所述栅金属层的材料为钨或者铜。
4.根据权利要求1所述的埋栅晶体管,其特征在于,所述盖层的材料为氧化硅或氮化硅。
5.一种埋栅晶体管的制造方法,其特征在于,包括:
提供半导体衬底;
在所述衬底上形成栅极沟槽;
在所述栅极沟槽内壁上形成栅介质层;
在所述栅极沟槽的下部形成阻挡层和栅金属层,并将所述阻挡层回刻至低于所述栅金属层的顶面;
在所述阻挡层和所述栅金属层上形成盖层;
其中,所述阻挡层的顶面与所述盖层的底面之间形成空气侧墙。
6.根据权利要求5所述的埋栅晶体管的制造方法,其特征在于,所述空气侧墙位于所述栅金属层的两侧,所述空气侧墙为所述阻挡层的顶面、所述盖层的底面、所述栅介质层与所述栅金属层合围的空间。
7.根据权利要求5所述的埋栅晶体管的制造方法,其特征在于,将所述阻挡层回刻至低于所述栅金属层的顶面包括:
采用H2O2刻蚀溶液将所述阻挡层回刻至低于所述栅金属层的顶面;
所述H2O2刻蚀溶液包括栅金属层材料刻蚀抑制剂或栅金属层材料钝化剂,所述H2O2刻蚀溶液的温度为25℃~100℃;所述H2O2刻蚀溶液的体积浓度为1%~37%。
8.根据权利要求5所述的埋栅晶体管的制造方法,其特征在于,将所述阻挡层回刻至低于所述栅金属层的顶面包括:
采用等离子体刻蚀工艺将所述阻挡层回刻至低于所述栅金属层的顶面;
所述等离子体刻蚀工艺的刻蚀气体为NF3、He和H2的混合气体;所述等离子体刻蚀工艺的射频功率为100W~300W,所述等离子体刻蚀工艺的工作温度为100℃~300℃。
9.根据权利要求5~8任一项所述的埋栅晶体管的制造方法,其特征在于,
所述阻挡层的材料为氮化钛或氮化钨;和/或,
所述栅金属层的材料为钨或者铜;和/或,
所述盖层的材料为氧化硅或氮化硅。
10.一种半导体存储器件,其特征在于,包括至少一个权利要求1~4任一项所述的埋栅晶体管。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010939666.9A CN114242788A (zh) | 2020-09-09 | 2020-09-09 | 一种埋栅晶体管及其制造方法、半导体存储器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010939666.9A CN114242788A (zh) | 2020-09-09 | 2020-09-09 | 一种埋栅晶体管及其制造方法、半导体存储器件 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN114242788A true CN114242788A (zh) | 2022-03-25 |
Family
ID=80742623
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010939666.9A Pending CN114242788A (zh) | 2020-09-09 | 2020-09-09 | 一种埋栅晶体管及其制造方法、半导体存储器件 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN114242788A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115732549A (zh) * | 2022-11-30 | 2023-03-03 | 上海功成半导体科技有限公司 | 一种屏蔽栅功率器件及其制备方法 |
-
2020
- 2020-09-09 CN CN202010939666.9A patent/CN114242788A/zh active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115732549A (zh) * | 2022-11-30 | 2023-03-03 | 上海功成半导体科技有限公司 | 一种屏蔽栅功率器件及其制备方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6362073B2 (en) | Method for forming semiconductor device having low parasite capacitance using air gap and self-aligned contact plug | |
KR100547227B1 (ko) | 신규한 디램 액세스 트랜지스터 | |
US7344954B2 (en) | Method of manufacturing a capacitor deep trench and of etching a deep trench opening | |
KR100375218B1 (ko) | 반사 방지막 및 자기정렬 콘택 기술을 사용하는 반도체 소자의 제조 방법 및 그에 의해 제조된 반도체 소자 | |
CN113035870B (zh) | 半导体结构的制造方法 | |
US20150214234A1 (en) | Semiconductor device and method for fabricating the same | |
CN114242788A (zh) | 一种埋栅晶体管及其制造方法、半导体存储器件 | |
CN111916399B (zh) | 一种半导体器件的制备方法以及半导体器件 | |
KR100376986B1 (ko) | 반도체소자의 제조방법 | |
CN113517288A (zh) | 半导体结构及其形成方法 | |
KR100487915B1 (ko) | 반도체소자의캐패시터형성방법 | |
US6890815B2 (en) | Reduced cap layer erosion for borderless contacts | |
US20220130836A1 (en) | Semiconductor structure formation method and semiconductor structure | |
US20230027860A1 (en) | Semiconductor structure and manufacturing method thereof | |
US11956944B2 (en) | DRAM semiconductor structure formation method and DRAM semiconductor structure | |
US7026210B2 (en) | Method for forming a bottle-shaped trench | |
KR100440079B1 (ko) | 반도체소자의 자기정렬적인 콘택 형성방법 | |
KR100440076B1 (ko) | 반도체소자의 자기정렬적인 콘택 형성방법 | |
US10304692B1 (en) | Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the FET circuits | |
KR100195837B1 (ko) | 반도체 소자의 미세콘택 형성방법 | |
JPH11251553A (ja) | 半導体メモリ装置のコンタクト形成方法及びその構造 | |
KR100400298B1 (ko) | 반도체소자의 자기정렬적인 콘택방법 | |
CN113782605A (zh) | 一种半导体器件及其制造方法、电子设备 | |
KR100444312B1 (ko) | 반도체소자의미세콘택형성방법 | |
KR100416659B1 (ko) | 반도체장치의 커패시터 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |