CN114175266A - 功率晶体管单元与功率晶体管 - Google Patents

功率晶体管单元与功率晶体管 Download PDF

Info

Publication number
CN114175266A
CN114175266A CN202080054755.3A CN202080054755A CN114175266A CN 114175266 A CN114175266 A CN 114175266A CN 202080054755 A CN202080054755 A CN 202080054755A CN 114175266 A CN114175266 A CN 114175266A
Authority
CN
China
Prior art keywords
region
power transistor
field shield
trench
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202080054755.3A
Other languages
English (en)
Inventor
K·埃耶斯
A·马丁内斯-利米亚
J-H·阿尔斯迈尔
W·法伊勒
S·施魏格尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of CN114175266A publication Critical patent/CN114175266A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623Buried supplementary region, e.g. buried guard ring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种具有层布置(101,201,301,401,501,601)的功率晶体管单元(100,200,300,400,500,600),该层布置具有前侧和后侧,其中,该前侧与该后侧相对置,其中,沟槽(104,204,304,404,504,604)自该前侧起并垂直于该前侧沿着第一方向(105,205,305,405,505,605)延伸至该层布置(101,201,301,401,501,601)中,并且该沟槽(104,204,304,404,504,604)至少到达电流扩散层(106,206,306,406,506,606)中,其中,该沟槽(104,204,304,404,504,604)沿着垂直于该第一方向(105,205,305,405,505,605)布置的第二方向(107,207,307,407,507,607)延展,并且场屏蔽区(108,208,308,408,508,608)至少局部地布置在该电流扩散层(106,206,306,406,506,606)中,其特征在于,源极区域(109,209,309,409,509,609)和场屏蔽接触区(111,211,311,411,511,611)沿着该第二方向(107,207,307,407,507,607)交替地布置,其中,在每个源极区域(109,209,309,409,509,609)与每个场屏蔽接触区(111,211,311,411,511,611)之间分别布置有体区(110,210,310,410,510,610)的一部分,其中,该场屏蔽接触区(111,211,311,411,511,611)将该场屏蔽区(108,208,308,408,508,608)与该前侧(102,202,302,402,502,602)上的第一金属区(112,212,312,412,512,612)连接,并且该场屏蔽接触区(111,211,311,411,511,611)至少局部地触碰该沟槽(104,204,304,404,504,604)的侧面。

Description

功率晶体管单元与功率晶体管
技术领域
本发明涉及一种功率晶体管单元和一种功率晶体管。
背景技术
碳化硅晶体管用于同时需要高截止强度和低导通电阻的应用。在此,在高截止电压下产生的电场与由具有窄带隙的半导体材料制成的功率晶体管相比明显更大,从而需要措施以保护栅极氧化物免受高场强的影响。
文献US 7700971 B2描述布置在漂移区中的p掺杂的区域,所述区域在水平方向上以规则间隔布置并且处于沟槽MOSFET结构下方,其中,所述区域经由接触结构与源极电位连接。在此,构件的源极区域侧向布置在沟槽旁边,而接触结构是在蚀刻SiC材料之后通过掩埋p区的暴露部分的表面的金属化而实现的,所述掩埋p区处于栅极/沟槽结构区域外部。
在构件的反向运行中,在此,在掩埋p区直至外部接触结构的较长区段上的电流传导是不利的,因为其造成更大的能量损耗并且在运行中需要更缓慢的切换频率。
文献US 9306061 A描述布置在漂移区中的p掺杂的区域,所述区域经由接触区与源极电位连接。在此,源极区域和接触区侧向布置在沟槽旁边,其中,接触区横越或突破(durchstoβen)源极区域。在此,源极区域侧向地紧邻沟槽。接触区与沟槽横向间隔开地布置并且触碰源极区域。沿着沟槽的长度传播部
Figure BDA0003493418690000011
源极区域和接触区的序列保持不变。这意味着,源极区域和接触区横向于沟槽的长度传播部而交替,其中,源极区域始终触碰沟槽,并且接触区从未触碰沟槽。
在此不利的是,功率晶体管的横向于沟槽纵向传播部的侧向尺寸大。
本发明的任务是克服这些缺点。
发明内容
功率晶体管单元包括层布置,该层布置具有前侧和后侧。在此,该前侧与该后侧相对置。沟槽自该前侧起沿着第一方向延伸至该层布置中,并且至少到达电流扩散层(Stromspreizschicht)中。该沟槽沿着垂直于该第一方向布置的第二方向延展。场屏蔽区至少局部地布置在该电流扩散层中。根据本发明,源极区域和场屏蔽接触区沿着该第二方向交替地布置,其中,在每个源极区域与每个场屏蔽接触区之间分别布置有体区(Bodybereichs)的一部分或者说带。该场屏蔽接触区将该场屏蔽区与该前侧上的第一金属区连接,其中,该场屏蔽接触区至少局部地触碰该沟槽的侧面。换句话说,源极区域和场屏蔽接触区在沟槽的传播方向上交替地布置,其中,源极区域和场屏蔽接触区是间接地彼此相继的。这意味着,源极区域和场屏蔽接触区分别由体区的一部分或者说带彼此分离。因此,源极区域、体区和场屏蔽接触区在沟槽的长度走向中交替地至少局部地与沟槽的侧面连接。在此,源极区域自一个沟槽至下一沟槽地沿着垂直于第一方向和第二方向地布置的第三方向延伸,至少局部地没有中断。
在此,优点为功率晶体管单元的尺寸小。这意味着,与传统的沟槽功率晶体管单元相比,功率晶体管单元的间距减小,由此减小导通电阻。
在一种扩展方案中,场屏蔽区布置在电流扩散层中并且与漂移层间隔开地布置。
在此有利的是,能够实现在低导通电阻下的高的竖直和横向电流传导。
在另一构型中,相比于沟槽的底部,场屏蔽区与前侧具有更大距离。换句话说,自前侧来看,场屏蔽区深于沟槽底部。
在此有利的是,保护沟槽免受高电场强度的影响。
在另一构型中,电流扩散层横向于场屏蔽区钟形地构型。
在此,优点为电流流动不受场屏蔽区消极影响,因为场屏蔽区与沟槽具有横向距离。
在一种扩展方案中,电流扩散层横向于场屏蔽区矩形地构型。
在此有利的是,将电流传导区域的面积最大化。
在另一构型中,所述体区内的体接触区局部地布置在所述源极区域下方,其中,体接触区经由场屏蔽接触区与层布置的前侧的第一金属区连接。
在此,优点为改善体接触。这意味着,改善反激二极管(Rücklaufdiode)的特性。
在一种扩展方案中,场屏蔽区在沟槽和/或后侧的方向上倒圆角。
在此有利的是,将电场强度降低。
在另一构型中,层布置包括具有宽带隙的半导体衬底。
在此,优点为所得构件具有更大的击穿电压、更低的损耗、更高的运行温度和更高的切换频率。
在一种扩展方案中,该半导体衬底包括碳化硅或氮化镓。
根据本发明的功率晶体管包括多个功率晶体管单元,该功率晶体管单元具有带有前侧和后侧的层布置。在此,该前侧与该后侧相对置。沟槽自该前侧起沿着第一方向延伸至该层布置中并且至少到达电流扩散层中。该沟槽沿着垂直于该第一方向布置的第二方向延展。场屏蔽区至少局部地布置在该电流扩散层中。根据本发明,源极区域和场屏蔽接触区沿着该第二方向交替地布置,其中,在每个源极区域与每个场屏蔽接触区之间分别布置有体区的一部分或带。场屏蔽接触区将场屏蔽区与该前侧上的第一金属区连接,其中,场屏蔽接触区至少局部地触碰该沟槽的侧面。
在此,优点为功率晶体管具有小的间距尺寸,由此减小导通电阻。
其他优点从对实施例的以下描述或者说从属专利权利要求中得出。
附图说明
以下基于优选实施方式和附图对本发明进行阐述。附图示出:
图1a功率晶体管单元的平面图;
图1b功率晶体管单元的沿着平面AA'的截面图的局部视图;
图1c功率晶体管单元的沿着平面BB'的截面图的局部视图;
图1d功率晶体管单元的沿着平面CC'的截面图;
图2a前功率晶体管半单元的平面图;
图2b前功率晶体管半单元沿着平面AA'的截面图;
图2c前功率晶体管半单元沿着平面BB'的截面图;
图2d前功率晶体管半单元的后视图;
图3a另一前功率晶体管半单元的平面图;
图3b另一前功率晶体管半单元沿着平面AA'的截面图;
图3c另一前功率晶体管半单元沿着平面BB'的截面图;
图3d另一前功率晶体管半单元的后视图;
图4a另一前功率晶体管半单元的平面图;
图4b另一前功率晶体管半单元沿着平面AA'的截面图;
图4c另一前功率晶体管半单元沿着平面BB'的截面图;
图4d另一前功率晶体管半单元的后视图;
图5a另一前功率晶体管半单元的平面图;
图5b另一前功率晶体管半单元沿着平面AA'的截面图;
图5c另一前功率晶体管半单元沿着平面BB'的截面图;
图5d另一前功率晶体管半单元的后视图;
图6a另一前功率晶体管半单元的平面图;
图6b另一前功率晶体管半单元沿着平面AA'的截面图;
图6c另一前功率晶体管半单元沿着平面BB'的截面图;
图6d另一前功率晶体管半单元的后视图;
图7a两个功率晶体管单元的平面图;
图7b另一功率晶体管单元的平面图;
图8a第一六边形单元几何形状;
图8b第二六边形单元几何形状;
图8c第三六边形单元几何形状;
图9a第一正方形单元几何形状;
图9b第二正方形单元几何形状;并且
图9c第三正方形单元几何形状。
具体实施方式
图1a示出功率晶体管单元100的平面图。功率晶体管单元100包括沿着第二方向107彼此相继地布置的前功率晶体管半单元102和后功率晶体管半单元103。在此,前功率晶体管半单元102和后功率晶体管半单元103相同地构建,其中,所述前功率晶体管半单元和后功率晶体管半单元沿着第二方向107彼此镜像反转地布置。这意味着,前功率晶体管半单元102和后功率晶体管半单元103的触碰表面相同。功率晶体管单元100包括层布置101。层布置101包括半导体衬底115、缓冲层116、漂移层117、电流扩散层106、场屏蔽区108、源极区域109、体区110和场屏蔽接触区111。在此,缓冲层116布置在半导体衬底115上。漂移层117布置在缓冲层116上。电流扩散层106布置在漂移层117上。源极区域109和体区110局部地布置在电流扩散层106上。第一金属区112布置在层布置101的前侧上以用于与源极区域109和体区110接触。在接触时,欧姆接触形成于第一金属区112与源极区域109之间或第一金属区112与体区110之间。场屏蔽区108至少局部地布置在电流扩散层106中。在此,所述场屏蔽区经由场屏蔽接触区111与第一金属区112电连接。第二金属区114布置在半导体衬底115下方。此第二金属区充当漏极金属化部。欧姆接触形成于半导体衬底115与第二金属区114之间。在第一方向105上至少到达电流扩散层106中的沟槽104自前侧起延伸。沟槽104在垂直于第一方向105地布置的第二方向107上延展。在此,第二方向107对应于沟槽104的传播方向或纵向方向。沟槽104在底部上具有场氧化物118并且在侧壁上具有栅极氧化物119。在此,相比于栅极氧化物119,该场氧化物118可以具有更大的层厚度。沟槽104填充有高度掺杂的n型或p型多晶硅。源极区域109和场屏蔽接触区111沿着沟槽104的传播方向交替地布置。在每个源极区域109与每个场屏蔽接触区111之间分别布置有体区110的带状部分。这意味着,沿着功率晶体管单元100的沟槽长度,源极区域109、体区110的一部分、场屏蔽接触区111、另一体区110的一部分和另一源极区域109分别布置在沟槽的上部区域中。在此,源极区域109和体区110紧邻沟槽104的侧壁。场屏蔽接触区111同样局部地紧邻沟槽104的侧壁并且触碰沟槽104的侧壁。另外,电流扩散层106和漂移层117局部地邻接沟槽104的侧壁。
在实施例中,自层布置101的前侧来看,相比于沟槽104的底部,场屏蔽区108的表面布置在与前侧相距较小距离处。在此,场屏蔽区108自电流扩散层106延伸至漂移层117中。
半导体衬底115是高度n掺杂的,并且缓冲层116是n掺杂的。漂移层117和电流扩散层106是n掺杂的,其中,相比于漂移层117,电流扩散层106具有更高的掺杂浓度。这导致沟道区下方的更好的电流传导并且因此导致更低的导通电阻。源极区域109是高度n掺杂的,并且体区110、场屏蔽区108和场屏蔽接触区111是p掺杂的。
半导体衬底115可以包括硅、碳化硅、氮化镓或氧化镓。
场屏蔽接触区111借助离子注入或外延而制造。
图1b示出功率晶体管单元100沿着平面AA'的截面图的局部视图。在此,该局部视图示出前功率晶体管半单元102沿着平面AA'的截面。在此,线AA'平行于如下平面地布置:该平面由第一方向105和第二方向107展开并且沿着第三方向121延伸穿过沟槽中心。图1b示出第二金属层114、半导体衬底115、缓冲层116、漂移层117、场氧化物118、栅极金属化部120和第一金属层112。通过参考标记CPz表示前功率晶体管半单元102沿着第二方向107的深度。
图1c示出功率晶体管单元100沿着平面BB'的截面图的局部视图。在此,该局部视图示出前功率晶体管半单元102沿着平面BB'的截面。在此,平面BB'平行于如下平面地布置:该平面由第一方向105和第二方向107展开并且沿着第三方向121在沟槽104与第一金属层112之间在侧向间隔处延伸。图1c示出第二金属层114、半导体衬底115、缓冲层116、漂移层117、电流扩散层106、体区110、源极区域109、场屏蔽接触区111和第一金属层112。通过参考标记WPz表示场屏蔽接触区111沿着第二方向107的深度,并且通过参考标记CPz表示前功率晶体管半单元102沿着第二方向107的深度。
图1d示出功率晶体管单元100的沿着平面CC'的截面图。该截面示出功率晶体管单元100的前功率晶体管半单元102的后视图。在此,功率晶体管单元100的截面平行于如下平面:该平面由第一方向105和第三方向121展开。在第二方向107上,该截面延伸穿过一半沟槽长度的点。图1d的参考标记对应于图1a的参考标记并且描述相同部件。场屏蔽接触区111和源极区域109沿着沟槽104的传播方向交替。可以看出,场屏蔽接触区111既不邻接源极区域109,也不突破或横越所述源极区域。
图2a示出前功率晶体管半单元202的平面图。图2a的参考标记的两个后面的位置(其对应于图1a的相同的后面的参考标记)描述与图1a中相同的部件。与图1a的差异在于,相比于沟槽底部,场屏蔽区208具有与层布置201的前侧的更大距离。换句话说,自前侧来看,场屏蔽区208深于沟槽底部。由此产生场屏蔽,该场屏蔽在沟槽底部处以场减小的方式起作用。
图2b示出功率晶体管单元200的前功率晶体管半单元202沿着平面AA'的截面图。图2b的参考标记的两个后面的位置(其对应于图1b的相同的后面的参考标记)描述与图1b中相同的部件。与图1b的差异在于,在图2b中,电流扩散层206布置在漂移层217与场氧化物218之间。换句话说,沟槽完全位于电流扩散层206中。
图2c示出功率晶体管单元200的前功率晶体管半单元202沿着平面BB'的截面图。图2c的参考标记的两个后面的位置(其对应于图1c的相同的后面的参考标记)描述与图1c中相同的部件。与图1c的差异在于,电流扩散层206自层布置的前侧起更深地延伸层布置201中。这就是说,在与图1c中相同的结构高度的情况下,相比于图1c中的漂移区117,漂移区217具有更低的高度。
图2d示出前功率晶体管半单元202的后视图。场屏蔽接触区211在沟槽204下方具有渐变的走向。这意味着,若沿着第三方向221跟踪场屏蔽接触区211与电流扩散层206的边界的走向,则其在第一方向205上具有不均一的深度。在此,电流扩散层206钟形或箭头形地构造。因此,电流扩散层206变得更大。这导致在沟道区下方在竖直方向或第一方向205上、在横向方向或第二方向207上和在第三方向221上更好的电流传导。
图3a示出另一前功率晶体管半单元302的平面图。图3a的参考标记的两个后面的位置(其对应于图2a的相同的后面的参考标记)描述与图2a中相同的部件。图3a的另一前功率晶体管半单元302的平面图与图2a的前功率晶体管半单元202的平面图没有区别。
图3b示出另一前功率晶体管半单元302沿着平面AA'的截面图。在此,图3b与图2b没有区别。
图3c示出另一前功率晶体管半单元202沿着平面BB'的截面图。图3c与图2c没有区别。
图3d示出另一前功率晶体管半单元302的后视图。电流扩散层306矩形地构造。由此,电流扩散层306在沟槽304下方相同式样地或均匀地扩展。这导致在沟槽304下方沿着第二方向307和第三方向321经改善的电流传导。
图4a示出另一前功率晶体管半单元402的平面图。图4a的参考标记的两个后面的位置(其对应于图2a的相同的后面的参考标记)描述与图2a中相同的部件。与图2a的差异在于,图4a附加地具有与体区410接触的体接触区413。在此,体接触区413布置在源极区域409下方。体接触区413与场屏蔽接触区411电连接。体接触区413导致,在极陡漏极电压瞬变的情况下,功率晶体管单元对由电流扩散层406、体区410和源极区域409形成的寄生npn晶体管的激活是不敏感的。替代地,体接触区413延伸至电流扩散层406中,即,所述体接触区局部地布置在体区410外部。
图4b示出另一前功率晶体管半单元402沿着平面AA'的截面图。在此,图4b与图2b没有区别。
图4c示出另一前功率晶体管半单元402沿着平面BB'的截面图。图4c的参考标记的两个后面的位置(其对应于图2c的相同的后面的参考标记)描述与图2c中相同的部件。与图2c的差异在于,图4c附加地具有与体区410接触的体接触区413。体接触区413是平坦的。
图4d示出另一前功率晶体管半单元402的后视图。图4d的参考标记的两个后面的位置(其对应于图2d的相同的后面的参考标记)描述与图2d中相同的部件。附加地,图4d示出体接触区413。
图5a示出另一前功率晶体管半单元502的平面图。图5a的参考标记的两个后面的位置(其对应于图4a的相同的后面的参考标记)描述与图4a中相同的部件。与图4a的差异在于,自层布置501的前侧来看,相比于图4a中的电流扩散层406,电流扩散层506更深地延伸至层布置501中。换句话说,沟槽底部504和场屏蔽区508完全处于电流扩散层506中并且与漂移层517间隔开。由此抵消沿着第三方向521相邻场屏蔽区508之间的JFET效应,从而产生更小的导通电阻。附加地,场屏蔽区511的角部可以在沟槽504和半导体衬底515的方向上倒圆角。
图5b示出另一前功率晶体管半单元502沿着平面AA'的截面图。图5b的参考标记的两个后面的位置(其对应于图4b的相同的后面的参考标记)描述与图4b中相同的部件。图5b在如下方面区别于图4b:相比于图4b的电流扩散层406,电流扩散层506自层布置501的前侧起更深地延伸。
图5c示出另一前功率晶体管半单元502沿着平面BB'的截面图。图5c的参考标记的两个后面的位置(其对应于图4c的相同的后面的参考标记)描述与图4c中相同的部件。图5c在如下方面区别于图4c:相比于图4c的电流扩散层406,电流扩散层506自层布置501的前侧起更深地延伸。
图5d示出另一前功率晶体管半单元502的后视图。图5d的参考标记的两个后面的位置(其对应于图4d的相同的后面的参考标记)描述与图4d中相同的部件。在此,相比于图4d中的电流扩散层406,电流扩散层506自层布置的前侧起更深地延伸至层布置中。
图6a示出另一前功率晶体管半单元602的平面图。图6a的参考标记的两个后面的位置(其对应于图5a的相同的后面的参考标记)描述与图5a中相同的部件。与图5a的差异在于,源极区域609、体区610和场屏蔽接触区611的宽度在功率晶体管单元600的宽度上变化。换句话说,场屏蔽接触区611沿着第二方向607的延展尺度在功率晶体管单元600的宽度上不上是恒定的,而是在沟槽之间的中心区域中是最大的,即,例如,当两个功率晶体管单元沿着第三方向621相互连接(aneinandergefügt)时。这意味着,场屏蔽接触区611的触碰沟槽604的侧壁的区域为小。源极区域609的延展尺度以相反的方式表现。延展尺度在中心沟槽之间的区域中是最小的并且沿着沟槽604的侧壁是最大的。这意味着,源极区域609与体区610之间的边界在晶体管单元的表面处三角形地延伸,其中,三角形的底侧或者说更宽的侧邻接沟槽604的侧壁。因此,此实施例组合了沟槽附近的窄的场屏蔽接触区611、小的导通电阻和用于场屏蔽区608的良好电连接的在场屏蔽区608上方的宽的场屏蔽接触区611。
图6b示出另一前功率晶体管半单元602沿着平面AA'的截面图。图6b的参考标记的两个后面的位置(其对应于图5b的相同的后面的参考标记)描述与图5b中相同的部件。
图6c示出另一前功率晶体管半单元602沿着平面BB'的截面图。图6c的参考标记的两个后面的位置(其对应于图5c的相同的后面的参考标记)描述与图5c中相同的部件。图6c在如下方面区别于图5c:源极区域609、体区610和场屏蔽接触区611沿着功率晶体管单元600的宽度不具有恒定的宽度。
图6d示出另一前功率晶体管半单元602的后视图。图6d的参考标记的两个后面的位置(其对应于图5d的相同的后面的参考标记)描述与图5d中相同的部件。在此同样可以看到的是,源极区域609、体区610和场屏蔽接触区611的宽度沿着功率晶体管单元的宽度发生变化。
图7a示出沿着第二方向707布置的两个功率晶体管单元700的平面图。源极区域709、体区710和场屏蔽接触区711矩形地构型。这意味着,源极区域709的宽度、体区710的宽度和场屏蔽接触区711的宽度在功率晶体管单元700的宽度上是恒定的。源极区域709、体区710和场屏蔽接触区711分别自沟槽的侧面延伸至功率晶体管单元边缘。
图7b示出另一功率晶体管单元700的平面图。源极区域709、体区710和场屏蔽接触区711沿着第三方向721具有不同宽度。
功率晶体管包括多个功率晶体管单元700。功率晶体管单元700沿着第二方向707和第三方向721相互连接。在此,优选地,将相同结构类型的功率晶体管单元相互连接。然而。也可以将不同的功率晶体管单元相互连接。
在另一实施方式中,在相邻功率晶体管单元中,功率晶体管单元嵌套地布置,从而在一个带中存在场屏蔽接触区,并且在相邻的带中不存在场屏蔽接触区或仅存在场屏蔽接触区的一部分。
除了功率晶体管单元的带状布置之外,还可以实现其他单元几何形状。图8a、图8b和图8c以示意性平面图示出三个六边形的单元布置,并且图9a、图9b和图9c以示意性平面图示出三个正方形的单元布置。可以看到的是源极区域809和909,和场屏蔽接触区811和911,以及栅极氧化物819和919。没有示出源极金属化部。层布置内部的场屏蔽区808和908示为虚线包围的区域。
替代于n沟道构件,还应通过本发明对与此双重地构建的p沟道构件进行说明。在此,应将所有n掺杂以p掺杂替换,并且应将电压的正负号反转。
以下描述在导通情况下和在截止情况下功率晶体管单元的工作方式。在导通情况下,将源极电位施加至第一金属区、即源极连接端。对于其他实施方案,源极电位用作参考电位。栅极金属化部具有正栅极电位,并且第二金属区、即漏极连接端具有几伏的小的正漏极电位。若栅极电位低于阈值电压Vth,则仅小电流自漏极连接端流动至源极连接端。若栅极电压增大,即,栅极电压具有高于阈值电压的值,则许多电子被移至体区的栅极氧化物侧的表面,从而构造导电沟道。因此产生自漏极连接端穿过半导体衬底、缓冲层、漂移层、电流扩散层、在体区的栅极氧化物侧的表面处形成的沟道、源极区域直至源极连接端的低欧姆的电流路径。功率晶体管单元或者说具有一个或多个功率晶体管单元的部件因此能够传导高的电流密度。
在截止情况下,栅极电压具有低于阈值电压的值。漏极电压具有正电压值。随着漏极电压增加,在p掺杂的场屏蔽区、p掺杂的场屏蔽接触区和p掺杂的体区以及邻接的分别较低地n掺杂的电流扩散层和漂移层之间的pn结的吸收截止电压的空间电荷区基本上延展至n掺杂的区域、即电流扩散层和漂移层中。在截止电压增大的情况下,空间电荷区扩展至缓冲层中,其中,p掺杂的场屏蔽区、p掺杂的场屏蔽接触区和p掺杂的体区未完全清除
Figure BDA0003493418690000111
经由场屏蔽区的总横向宽度WP与功率晶体管单元的总横向间距CP的比率可以获得在低导通电阻与屏蔽效果之间的折衷。若该比率变大,则场屏蔽接触区的屏蔽效果更加有效并且导通电阻更高。若该比率趋于零,则导通电阻极低,然而屏蔽效果同样如此。因此优选大约0.5的比率。
由于内部电压降和高掺杂,场屏蔽区和场屏蔽接触区与邻接的漂移层和电流扩散层相互作用充当本征二极管。若将本征二极管通电,则栅极电压具有小于阈值电压的值并且漏极电压具有负电压。
经由场屏蔽接触区沿着第二方向的延展尺度与功率晶体管单元在第二方向上的延展尺度的比率可以建立在低导通电阻与场屏蔽区的电连接之间的折衷。若比率的值接近值1,则导通电阻高然而电连接极好。若比率的值接近值零,则电连接低但是导通电阻极低。在此优选大约0.25的比率。
功率晶体管可以在用于工业驱动器的反相器、用于诸如风力涡轮机之类的再生能量产生的反相器、用于电动车辆和混合动力车辆的汽车反相器、牵引驱动器或高压整流器中应用。

Claims (10)

1.一种功率晶体管单元(100,200,300,400,500,600),其具有层布置(101,201,301,401,501,601),所述层布置具有前侧和后侧,其中,所述前侧与所述后侧相对置,其中,沟槽(104,204,304,404,504,604)自所述前侧起沿着第一方向(105,205,305,405,505,605)延伸至所述层布置(101,201,301,401,501,601)中,并且所述沟槽(104,204,304,404,504,604)至少到达电流扩散层(106,206,306,406,506,606)中,其中,所述沟槽(104,204,304,404,504,604)沿着垂直于所述第一方向(105,205,305,405,505,605)布置的第二方向(107,207,307,407,507,607)延展,并且场屏蔽区(108,208,308,408,508,608)至少局部地布置在所述电流扩散层(106,206,306,406,506,606)中,其特征在于,源极区域(109,209,309,409,509,609)和场屏蔽接触区(111,211,311,411,511,611)沿着所述第二方向(107,207,307,407,507,607)交替地布置,其中,在每个源极区域(109,209,309,409,509,609)与每个场屏蔽接触区(111,211,311,411,511,611)之间分别布置有体区(110,210,310,410,510,610)的一部分,其中,所述场屏蔽接触区(111,211,311,411,511,611)将所述场屏蔽区(108,208,308,408,508,608)与所述前侧(102,202,302,402,502,602)上的第一金属区(112,212,312,412,512,612)连接,并且所述场屏蔽接触区(111,211,311,411,511,611)至少局部地触碰所述沟槽(104,204,304,404,504,604)的侧面。
2.根据权利要求1所述的功率晶体管单元(100,200,300,400,500,600),其特征在于,所述场屏蔽区(108,208,308,408,508,608)布置在所述电流扩散层(106,206,306,406,506,606)内并且与漂移层(117,217,317,417,517,617)间隔开地布置。
3.根据权利要求1或2所述的功率晶体管单元(100,200,300,400,500,600),其特征在于,相比于所述沟槽(104,204,304,404,504,604)的底部,所述场屏蔽区(108,208,308,408,508,608)与所述层布置(101,201,301,401,501,601)的前侧具有更大距离。
4.根据上述权利要求中任一项所述的功率晶体管单元(100,200,300,400,500,600),其特征在于,所述电流扩散层(106,206,306,406,506,606)横向于所述场屏蔽接触区(111,211,311,411,511,611)钟形地构型。
5.根据权利要求1至3中任一项所述的功率晶体管单元(100,200,300,400,500,600),其特征在于,所述电流扩散层(106,206,306,406,506,606)横向于所述场屏蔽接触区(111,211,311,411,511,611)矩形地构型。
6.根据上述权利要求中任一项所述的功率晶体管单元(400,500,600),其特征在于,所述体区(410,510,610)内的体接触区(413,513,613)局部地布置在所述源极区域(409,509,609)下方,其中,所述体接触区(413,513,613)经由所述场屏蔽接触区(411,511,611)与所述层布置(401,501,601)的前侧的第一金属区(412,512,612)连接。
7.根据上述权利要求中任一项所述的功率晶体管单元(100,200,300,400,500,600),其特征在于,所述场屏蔽区(108,208,308,408,508,608)在所述沟槽(104,204,304,404,504,604)和/或所述后侧的方向上倒圆角。
8.根据上述权利要求中任一项所述的功率晶体管单元(100,200,300,400,500,600),其特征在于,所述层布置(101,201,301,401,501,601)包括具有宽带隙的半导体衬底。
9.根据权利要求8所述的功率晶体管单元(100,200,300,400,500,600),其特征在于,所述半导体衬底具有碳化硅或氮化镓。
10.一种功率晶体管,所述功率晶体管具有多个根据上述权利要求中任一项所述的功率晶体管单元(100,200,300,400,500,600)。
CN202080054755.3A 2019-05-31 2020-05-18 功率晶体管单元与功率晶体管 Pending CN114175266A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102019208010 2019-05-31
DE102019208010.3 2019-05-31
DE102019210681.1A DE102019210681A1 (de) 2019-05-31 2019-07-19 Leistungstransistorzelle und Leistungstransistor
DE102019210681.1 2019-07-19
PCT/EP2020/063821 WO2020239501A1 (de) 2019-05-31 2020-05-18 Leistungstransistorzelle und leistungstransistor

Publications (1)

Publication Number Publication Date
CN114175266A true CN114175266A (zh) 2022-03-11

Family

ID=73264765

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080054755.3A Pending CN114175266A (zh) 2019-05-31 2020-05-18 功率晶体管单元与功率晶体管

Country Status (8)

Country Link
US (1) US20220320286A1 (zh)
EP (1) EP3977519A1 (zh)
JP (1) JP7291807B2 (zh)
KR (1) KR20220016134A (zh)
CN (1) CN114175266A (zh)
DE (1) DE102019210681A1 (zh)
TW (1) TW202114214A (zh)
WO (1) WO2020239501A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115588695A (zh) * 2022-12-09 2023-01-10 无锡先瞳半导体科技有限公司 屏蔽栅场效应晶体管

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3158973B2 (ja) * 1995-07-20 2001-04-23 富士電機株式会社 炭化けい素縦型fet
JP2007005657A (ja) * 2005-06-24 2007-01-11 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
JP2008177335A (ja) 2007-01-18 2008-07-31 Fuji Electric Device Technology Co Ltd 炭化珪素絶縁ゲート型半導体装置。
JP2012069797A (ja) * 2010-09-24 2012-04-05 Toyota Motor Corp 絶縁ゲート型トランジスタ
US9306061B2 (en) 2013-03-13 2016-04-05 Cree, Inc. Field effect transistor devices with protective regions
US20180366569A1 (en) 2016-06-10 2018-12-20 Maxpower Semiconductor Inc. Trench-Gated Heterostructure and Double-Heterostructure Active Devices
JP6880669B2 (ja) * 2016-11-16 2021-06-02 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP7327905B2 (ja) 2017-07-07 2023-08-16 株式会社デンソー 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115588695A (zh) * 2022-12-09 2023-01-10 无锡先瞳半导体科技有限公司 屏蔽栅场效应晶体管

Also Published As

Publication number Publication date
KR20220016134A (ko) 2022-02-08
JP2022534117A (ja) 2022-07-27
EP3977519A1 (de) 2022-04-06
TW202114214A (zh) 2021-04-01
DE102019210681A1 (de) 2020-12-03
US20220320286A1 (en) 2022-10-06
JP7291807B2 (ja) 2023-06-15
WO2020239501A1 (de) 2020-12-03

Similar Documents

Publication Publication Date Title
US10903312B2 (en) Semiconductor device
WO2018220879A1 (ja) 半導体装置
US8823084B2 (en) Semiconductor device with charge compensation structure arrangement for optimized on-state resistance and switching losses
US9147763B2 (en) Charge-compensation semiconductor device
US20190027472A1 (en) Semiconductor device
US11552173B2 (en) Silicon carbide device with trench gate
US11588045B2 (en) Fortified trench planar MOS power transistor
CN109166921B (zh) 一种屏蔽栅mosfet
CN114927561B (zh) 一种碳化硅mosfet器件
CN114512439A (zh) 半导体装置
EP3154091A1 (en) Reverse-conducting semiconductor device
CN109524458B (zh) 半导体装置
KR102387574B1 (ko) 전력 반도체 소자
CN114175266A (zh) 功率晶体管单元与功率晶体管
EP4128362B1 (en) Power semiconductor device
US11575032B2 (en) Vertical power semiconductor device and manufacturing method
US11316021B2 (en) High density power device with selectively shielded recessed field plate
GB2592928A (en) Insulated gate switched transistor
CN114667609A (zh) 垂直场效应晶体管和用于构造其的方法
JP2009111237A (ja) 半導体素子
US11411076B2 (en) Semiconductor device with fortifying layer
US20220384577A1 (en) Semiconductor device and method for designing thereof
CN117063292B (zh) 功率半导体器件
US20220231164A1 (en) Switching element
US20220278231A1 (en) Switching element

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination