CN114068462A - 半导体封装件及其制造方法 - Google Patents
半导体封装件及其制造方法 Download PDFInfo
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- CN114068462A CN114068462A CN202110864235.5A CN202110864235A CN114068462A CN 114068462 A CN114068462 A CN 114068462A CN 202110864235 A CN202110864235 A CN 202110864235A CN 114068462 A CN114068462 A CN 114068462A
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Abstract
公开了半导体封装件及其制造方法。半导体封装件包括重分布衬底,其包括电介质层中的重分布线图案;以及半导体芯片,其位于重分布衬底上。半导体芯片包括芯片焊盘,其电连接至重分布线图案。重分布线图案中的每一个具有基本上共面的顶表面和非共面的底表面。重分布线图案中的每一个包括中心部分和位于中心部分的相对侧上的边缘部分。重分布线图案中的每一个在中心部分处具有作为最小厚度的第一厚度,并且在边缘部分处作为最大厚度的第二厚度。
Description
相关申请的交叉引用
本申请要求于2020年7月31日在韩国知识产权局提交的韩国专利申请No.10-2020-0096203的优先权,该申请的公开内容以引用方式全部并入本文中。
技术领域
本发明构思涉及一种半导体封装件及其制造方法,更具体地,涉及一种包括精细重分布图案的半导体封装件及其制造方法。
背景技术
提供了一种半导体封装件以实施电子产品中使用的集成电路芯片。通常,半导体封装件被配置为使得半导体芯片安装在印刷电路板(PCB)上,并且接合线或凸块用于将半导体芯片电连接至印刷电路板。利用电子工业的发展,已经进行了各种研究,以改善半导体封装件的可靠性和耐久性。
发明内容
本发明构思的一些示例实施例提供了一种紧凑尺寸的半导体封装件及其制造方法。
本发明构思的目的不限于以上所提及的,并且通过下面的描述,对本领域技术人员而言,将更清楚地理解以上未提及的其它目的。
根据本发明构思的一些示例实施例,半导体封装件可以包括:重分布衬底,其包括电介质层中的多个重分布线图案;以及半导体芯片,其位于重分布衬底上,半导体芯片包括电连接至重分布线图案的多个芯片焊盘。重分布线图案中的每一个可以包括基本上平面的顶表面和非平面的底表面。重分布线图案中的每一个可以包括中心部分和位于中心部分的相对侧上的边缘部分。重分布线图案中的每一个可以在中心部分处具有第一厚度作为最小厚度,并且在边缘部分处具有第二厚度作为最大厚度。
根据本发明构思的一些示例实施例,半导体封装件可以包括:重分布衬底,其括电介质层中的多个重分布图案;以及半导体芯片,其位于重分布衬底上,半导体芯片包括电连接至重分布图案的多个芯片焊盘。重分布图案中的每一个可以包括:线部,其位于电介质层中;以及穿通件部分,其穿透电介质层,并且连接至线部。重分布图案中的每一个的线部可以在第一方向上平行于彼此延伸。多个重分布图案的线部中的至少一些可以在垂直于第一方向的第二方向上具有第一宽度。重分布图案中的每一个的线部可以包括中心部分和位于中心部分的相对侧上的边缘部分。重分布图案中的每一个的线部可以包括在中心部分处向上凸出的底表面。
根据本发明构思的一些示例实施例,半导体封装件可以包括:封装衬底;重分布衬底,其位于封装衬底上,重分布衬底包括光敏聚合物层和光敏聚合物层中的多个重分布图案;第一半导体芯片,其位于重分布衬底上;第二半导体芯片,其位于重分布衬底上,并且与第一半导体芯片间隔开,第二半导体芯片包括多个竖直堆叠的存储器芯片;多个第一连接端子,其位于重分布衬底与第一半导体芯片之间以及重分布衬底与第二半导体芯片之间;多个第二连接端子,其将封装衬底连接至重分布衬底;模制层,其位于重分布衬底上,模制层至少部分地覆盖第一半导体芯片和第二半导体芯片;以及热辐射结构,其位于封装衬底上,热辐射结构覆盖或盖住重分布衬底、第一半导体芯片和第二半导体芯片。重分布图案中的每一个可以包括:线部,其在电介质层中沿着一个方向延伸;以及穿通件部分,其穿透电介质层,并且连接至线部。重分布图案中的每一个的线部可以包括基本上平面的顶表面、非平面的底表面以及位于线部的底表面与相对的第一侧壁和第二侧壁之间的第一圆的边缘和第二圆的边缘。重分布图案中的每一个的线部可以包括中心部分以及位于中心部分的相对侧上的第一边缘部分和第二边缘部分。重分布图案中的每一个的线部可以在中心部分处具有第一厚度作为最小厚度,并且在第一边缘部分和第二边缘部分处具有第二厚度作为最大厚度。
根据本发明构思的一些示例实施例,一种制造半导体封装件的方法可以包括:形成重分布衬底;以及将半导体芯片安装在重分布衬底上。形成重分布衬底的步骤可以包括:在电介质层上形成硬掩模层;在硬掩模层上形成光致抗蚀剂图案;使用光致抗蚀剂图案作为蚀刻掩模在电介质层上形成硬掩模图案以蚀刻硬掩模层;以及使用硬掩模图案作为蚀刻掩模形成多个沟槽,以蚀刻电介质层的一部分,其中,多个沟槽在一个方向上平行于彼此延伸。形成硬掩模图案的步骤可以包括在电介质层上形成在一个方向上平行于彼此延伸的多个初始沟槽。初始沟槽中的每一个可以具有这样的深度:其在初始沟槽的边缘部分处的深度大于在初始沟槽的中心部分处的深度。每个沟槽可以包括向上凸出的底表面和位于该沟槽的底表面和侧壁之间的圆的边缘。
其它示例实施例的细节包括在描述和附图中。
附图说明
图1示出了部分示出根据本发明构思的一些示例实施例的半导体封装件的重分布衬底的平面图。
图2至图7示出了根据本发明构思的一些示例实施例的制造半导体封装件的重分布图案的方法的沿图1的线I-I’和线II-II’截取的截面图。
图8示出了示出根据本发明构思的一些示例实施例的通过制造半导体封装件的重分布图案的方法形成的重分布图案的线部的截面图。
图9示出了部分示出根据本发明构思的一些示例实施例的半导体封装件的重分布衬底的平面图。
图10至图13示出了示出根据本发明构思的一些示例实施例的制造半导体封装件的重分布图案的方法的沿图9的线III-III’和线IV-IV’截取的截面图。
图14示出了示出根据本发明构思的一些示例实施例的半导体封装件的简化平面图。
图15、图16和图17示出了示出根据本发明构思的一些示例实施例的半导体封装件的沿图14的线V-V’截取的截面图。
图18、图19和图20示出了示出根据本发明构思的一些示例实施例的半导体封装件的截面图。
具体实施方式
现在将结合附图在下面描述根据本发明构思的一些示例实施例的半导体封装件及其制造方法。
图1示出了部分示出根据本发明构思的一些示例实施例的半导体封装件的重分布衬底的平面图。图2至图7示出了示出根据本发明构思的一些示例实施例的制造半导体封装件的重分布图案的方法的沿图1的线I-I’和线II-II’截取的截面图。图8示出了示出根据本发明构思的一些示例实施例的通过制造半导体封装件的重分布图案的方法形成的重分布图案的线部的截面图。
参照图1和图2,可以在下层10上形成导电图案CP。尽管未示出,但是下层10可以包括承载衬底、半导体衬底或电介质层。下层10可以包括形成在半导体衬底上的存储器电路、逻辑电路或者包括存储器和逻辑电路的组合的半导体集成电路,并且还可以包括覆盖半导体集成电路的多个堆叠的电介质层。
可以通过执行沉积工艺、图案化工艺、电镀工艺或无电镀工艺来形成导电图案CP。导电图案CP可以由以下金属或其合金形成:所述金属中的每一个包括选自铜(Cu)、铝(Al)、镍(Ni)、银(Ag)、金(Au)、铂(Pt)、锡(Sn)、铅(Pb)、钛(Ti)、铬(Cr)、钯(Pd)、铟(In)、锌(Zn)和碳(C)中的至少一种。
电介质层20可以形成在下层10上。例如,可以通过使用诸如旋涂或狭缝涂覆的涂覆工艺来形成电介质层20。尽管示出了单个电介质层20,但是电介质层20可以包括多个堆叠的电介质层。
电介质层20可以包括例如光敏聚合物。光敏聚合物可以包括例如光敏聚酰亚胺、聚苯并噁唑、酚醛聚合物和苯并环丁烯聚合物中的一种或多种。可替代地,电介质层20可以包括例如氧化硅层、氮化硅层或氮氧化硅层。
可以在电介质层20上形成硬掩模层30,并且可以在硬掩模层30上形成光致抗蚀剂图案45。
硬掩模层30可以由相对于电介质层20具有蚀刻选择性的材料形成。硬掩模层30可以包括钛、氮化钛、钽、氮化钽、钨或任何合适的金属材料。可替代地,硬掩模层30可以是多晶硅层、氮化硅层或氮氧化硅层。可以通过使用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)来形成硬掩模层30。
可以通过在硬掩模层30上形成光致抗蚀剂层并且随后执行曝光和显影工艺来形成光致抗蚀剂图案45。光致抗蚀剂图案45可以包括部分地暴露出硬掩模层30的开口,该开口可以具有其线性形状。例如,光致抗蚀剂图案45可以包括线和间隔(line-and-space)图案。光致抗蚀剂图案45可以具有大约1.5μm至大约2.5μm的线宽。
参照图1和图3,光致抗蚀剂图案45可以用作蚀刻掩模以对硬掩模层30执行各向异性蚀刻工艺。可以由此在电介质层20上形成硬掩模图案35。对硬掩模层30的各向异性蚀刻工艺可以包括反应性离子蚀刻(RIE)、磁增强反应性离子刻蚀(MERIE)、感应耦合等离子体(ICP)蚀刻、变压器耦合等离子体(TCP)蚀刻、空心阳极型等离子体蚀刻或螺旋共振器等离子体蚀刻。
对硬掩模层30的各向异性蚀刻工艺可以使用基于CxFy的蚀刻气体。例如,蚀刻气体可以包括CF4、C3F6、C4F6、C4F8、C5F8、CH3F、CHF3、CH2F2或它们的任意组合。另外,诸如氩(Ar)的惰性气体可以在对硬掩模层30的各向异性蚀刻工艺中使用。
可以由于对硬掩模层30的各向异性蚀刻工艺中的过蚀刻而部分地蚀刻电介质层20。因此,可以在电介质层20的上部上形成初始沟槽PT。
当使用等离子体来各向异性蚀刻硬掩模层30时,蚀刻气体的有效离子可以具有强的方向性以允许初始沟槽PT具有基本上垂直的侧壁或基本上竖直的侧壁。另外,当在对硬掩模层30的各向异性蚀刻工艺中增大射频(RF)功率时,蚀刻气体离子可以集中在初始沟槽PT的角部上。因此,初始沟槽PT的角部可以比初始沟槽PT的底表面的中心更尖。例如,初始沟槽PT可以具有不平坦的底表面,并且在初始沟槽PT的侧壁处的深度可以与在初始沟槽PT的中心处的深度不同。在此情况下,初始沟槽PT可以在其侧壁处具有最大深度。例如,初始沟槽PT可以具有大约0.5μm至大约3.0μm的深度d1。
参照图1和图4,硬掩模图案35可以用作蚀刻掩模以对暴露于初始沟槽PT的电介质层20执行各向异性蚀刻工艺。因此,可以在电介质层20上形成沟槽T。
对电介质层20的各向异性蚀刻工艺可以包括反应性离子蚀刻(RIE)、磁增强反应性离子刻蚀(MERIE)、感应耦合等离子体(ICP)蚀刻、变压器耦合等离子体(TCP)蚀刻、空心阳极型等离子体蚀刻或螺旋共振器等离子体蚀刻。
对电介质层20的各向异性蚀刻工艺的射频(RF)功率可以小于对硬掩模层30的各向异性蚀刻工艺的射频(RF)功率。对电介质层20的各向异性蚀刻工艺可以使用基于CxFy的蚀刻气体和含氧的蚀刻气体。另外,可以在对电介质层20的各向异性蚀刻工艺中使用诸如氩(Ar)的惰性气体。
根据一些示例实施例,通过其中硬掩模图案35用作蚀刻掩模的各向异性蚀刻工艺形成的沟槽T的侧壁可以基本上垂直于电介质层20的顶表面(例如,所述侧壁可以基本上竖直)。例如,沟槽T的侧壁可以相对于电介质层20的顶表面具有第一角度θ1,第一角度θ1可以在大约85°至大约95°的范围内。
对电介质层20的各向异性蚀刻工艺可以使初始沟槽PT的尖的角部变圆。沟槽T可以具有向上凸出的底表面和圆的边缘或角部。例如,可以在沟槽T的底表面与相对侧壁之间形成圆的边缘。沟槽T的圆的边缘可以具有大约0.1μm至大约0.3μm的曲率半径(或曲率的半径)R。沟槽T可以具有大约2.0μm至大约3.5μm的深度d2。
参照图1和图5,在形成沟槽T之后,可以去除光致抗蚀剂图案45和硬掩模图案35。可以通过使用包括灰化步骤和清洗步骤的剥离工艺来去除光致抗蚀剂图案45。可以通过使用湿蚀刻工艺来去除硬掩模图案35。
在去除光致抗蚀剂图案45和硬掩模图案35之后,沟槽T可以具有位于其底表面处的被形成为穿透电介质层20的过孔VH。过孔VH可以暴露出下层10上的导电图案CP。
当电介质层20由光敏聚合物层形成时,可以通过对电介质层20执行曝光和显影工艺来形成过孔VH。曝光工艺可以是正性曝光工艺或负性曝光工艺。
参照图1和图6,可以在其上形成有沟槽T和过孔VH的电介质层20上顺序地形成第一金属层51和第二金属层53。
第一金属层51可以被沉积为在其上形成有沟槽T和过孔VH的电介质层20上具有基本上均匀的厚度。例如,第一金属层51可以共形地覆盖沟槽T的内壁、过孔VH的内壁和电介质层20的顶表面。可以通过使用物理气相沉积(PVD)、化学气相沉积(CVD)、或原子层沉积(ALD)来形成第一金属层51。在一些示例实施例中,因为沟槽T具有圆的边缘,当沉积第一金属层51时,可以改善台阶覆盖率。
第一金属层51的形成可以包括顺序地沉积金属阻挡层和金属种子层。金属阻挡层可以包括例如双层或除双层以外的混合层,双层或混合层可以包括钛、氮化钛、钽、氮化钽、钌、钴、锰、氮化钨、镍、硼化镍或者钛/氮化钛。金属种子层可以包括例如铜(Cu)。
第二金属层53可以完全填充沟槽T和过孔VH,第一金属层51形成在沟槽T和过孔VH中的每一个中。可以在电介质层20的其上形成有第一金属层51的顶表面上形成第二金属层53。可以通过执行诸如镀覆或脉冲镀覆的电镀工艺来形成第二金属层53。第二金属层53可以从金属种子层的表面填充沟槽T和过孔VH。
参照图1和图7,第一金属层51和第二金属层53可以经历平面化工艺以暴露出电介质层20的顶表面。可以执行化学机械抛光(CMP)工艺作为平面化工艺。平面化工艺可以形成彼此分开或间隔开的重分布图案50。重分布图案50中的每一个可以包括第一金属图案52和第二金属图案54。平面化工艺可以使重分布图案50具有基本上平坦或平面的顶表面(例如,基本上水平的顶表面)。例如,重分布图案50的顶表面可以基本上与电介质层20的顶表面共面。另外,重分布图案50的顶表面可以基本上平行于下层10的顶表面和电介质层20的底表面。
重分布图案50中的每一个可以包括形成在沟槽T中的线部50a和形成在过孔VH中的穿通件部分50b。线部50a可以在电介质层20的上部上沿着一个方向延伸。
重分布图案50的线部50a可以沿着第一方向D1平行于彼此延伸。每个线部50a可以在垂直于第一方向D1的第二方向D2上具有第一宽度W1。线部50a可以以第一间隔S1彼此间隔开。第一间隔S1和第一宽度W1可以基本上彼此相同。
线部50a的第一宽度W1可以在大约0.5μm至大约2.5μm的范围内,邻近的或相邻的重分布图案50的线部50a之间的第一间隔S1可以在大约0.5μm至大约2.5μm的范围内。另外,重分布图案50的线部50a可以具有大约2.5μm至大约4.0μm的厚度或宽度W1。
在一些示例实施例中,参照图8,重分布图案50的线部50a可以具有不平坦的底表面。例如,重分布图案50的线部50a可以具有弯曲、起伏或波浪状的底表面。重分布图案50的线部50a可以在其底表面与侧壁之间具有圆的边缘或角部。线部50a的圆的边缘可以具有大约0.1μm至大约0.3μm的曲率半径(或曲率的半径)R。重分布图案50的线部50a可以具有相对于电介质层20的顶表面以第一角度取向的侧壁,第一角度可以在大约85°至大约95°的范围内。
重分布图案50的线部50a可以包括中心部分P1和在中心部分P1的相对侧上的边缘部分P2。线部50a可以在中心部分P1处具有第一厚度T1作为其最小厚度,并且在边缘部分P2处具有第二厚度T2作为其最大厚度。大约0.1μm至大约0.2μm可以是作为最小厚度的第一厚度T1与作为最小厚度的第二厚度T2之间的差DT。例如,中心部分P1的底表面S1可以朝向重分布图案50的顶表面凸出或相对于重分布图案50的顶表面凸出,边缘部分P2的底表面S2可以朝向电介质层20的底表面凸出(或者相对于重分布图案50的顶表面凹陷)。另外,边缘部分P2的底表面S2可以具有第一曲率半径(或曲率的半径),中心部分P1的底表面S1可以具有与第一曲率半径不同的第二曲率半径(或曲率的半径)。
图9示出了部分示出根据本发明构思的一些示例实施例的半导体封装件的重分布衬底的平面图。图10至图13示出了示出根据本发明构思的一些示例实施例的制造半导体封装件的重分布图案的方法的沿图9的线III-III’和线IV-IV’截取的截面图。
为了简洁描述起见,可以省略与以上参照图1至图8讨论的实施例的那些相应的技术特征。
参照图9和图10,下层10可以包括第一区R1和第二区R2。可以在第一区R1上形成第一重分布图案50-1,并且可以在第二区R2上形成第二重分布图案50-2。
如参照图2讨论的,可以在下层10上顺序地形成电介质层20和硬掩模层30,并且可以在硬掩模层30上形成光致抗蚀剂图案45。
光致抗蚀剂图案45可以具有第一区R1上的第一开口和第二区R2上的第二开口。第一开口的宽度可以小于第二开口的宽度。光致抗蚀剂图案45的第一开口和第二开口可以各自具有在第一方向D1上延伸的线形。
参照图9和图11,如参照图3讨论的,光致抗蚀剂图案45可以用作蚀刻掩模,以各向异性地蚀刻硬掩模层30以形成硬掩模图案35。
在形成硬掩模图案35期间,可以在第一区R1的电介质层20上形成第一初始沟槽PT1,并且可以在第二区R2的电介质层20上形成第二初始沟槽PT2。
当形成第一初始沟槽PT1和第二初始沟槽PT2时,蚀刻气体离子可以使第一初始沟槽PT1和第二初始沟槽PT2在其侧壁处具有最大深度。第一初始沟槽PT1和第二初始沟槽PT2的角部可以比第一初始沟槽PT1和第二初始沟槽PT2的底表面的中心更尖。
参照图9和图12,如参照图4所讨论的,硬掩模图案35可以用作蚀刻掩模,以对电介质层20执行各向异性蚀刻工艺。因此,可以在第一区R1的电介质层20上形成第一沟槽T1,并且可以在第二区R2的电介质层20上形成第二沟槽T2。
根据一些示例实施例,第一沟槽T1可以各自具有第一宽度W1,第二沟槽T2可以各自具有大于第一宽度W1的第二宽度W2。当形成第一沟槽T1和第二沟槽T2时,负载效应可以使第二沟槽T2具有与第一沟槽T1的深度不同的深度。
如以上所讨论的,第一沟槽T1和第二沟槽T2可以具有基本上垂直于电介质层20的顶表面的侧壁,并且还可以具有圆的边缘。第一沟槽T1的圆的边缘可以具有第一曲率半径(或曲率的半径)r1,第二沟槽T2的圆的边缘可以具有第二曲率半径(或曲率的半径)r2。第二曲率半径r2可以大于第一曲率半径r1。
另外,第一沟槽T1和第二沟槽T2可以具有向上凸出的底表面,第一沟槽T1的底表面可以具有比第二沟槽T2的底表面的曲率半径更大的曲率半径(或曲率的半径)。可替代地,第一沟槽T1可以具有向上凸出的底表面,第二沟槽T2可以具有平坦的或基本上平面的底表面。
参照图9和图13,如以上参照图5和图6所讨论的,可以在第一沟槽T1中形成第一重分布图案50-1,并且可以在第二沟槽T2中形成第二重分布图案50-2。第一重分布图案50-1和第二重分布图案50-2中的每一个可以包括第一金属图案52和第二金属图案54。
根据一些示例实施例,第一重分布图案50-1可以各自具有第一宽度W1,并且可以以第一间隔S1彼此间隔开。第二重分布图案50-2可以各自具有大于第一宽度W1的第二宽度W2,并且可以以大于第一间隔S1的第二间隔S2彼此间隔开。
第一重分布图案50-1和第二重分布图案50-2中的每一个可以包括中心部分和位于中心部分的相对侧上的边缘部分。在第一重分布图案50-1和第二重分布图案50-2中的每一个上,中心部分可以具有最小厚度,边缘部分可以具有其最大厚度。例如,第一重分布图案50-1的最大厚度与最小厚度之间的差DT1可以大于第二重分布图案50-2的最大厚度与最小厚度之间的差DT2。
图14示出了示出根据本发明构思的一些示例实施例的半导体封装件的简化平面图。图15、图16和图17示出了示出根据本发明构思的一些示例实施例的半导体封装件的沿图14的线V-V’截取的截面图。为了简洁起见,可以省略与以上参照图1至图8讨论的实施例的那些相同的技术特征。
参照图14、图15、图16和图17,半导体封装件1000可以包括第一半导体芯片100、第二半导体芯片200、重分布衬底300、封装衬底500和热辐射结构600。
第一半导体芯片100和第二半导体芯片200可以设置在重分布衬底300的顶表面上。
第一半导体芯片100可以具有其底表面上的下芯片焊盘111。第一半导体芯片100可以是包括处理器(诸如微机电系统(MEMS)装置、光电装置、中央处理单元(CPU)、图形处理单元(GPU)、移动应用、或数字信号处理器(DSP))的逻辑芯片。第一半导体芯片100可以具有大约700μm至大约775μm的厚度。
重分布衬底300可以设置在第二半导体芯片200上,并且第二半导体芯片200与第一半导体芯片100间隔开。第二半导体芯片200中的每一个可以包括竖直地堆叠的多个存储器芯片210。多个存储器芯片210可以通过下芯片焊盘221、上芯片焊盘223、芯片穿通件225和连接凸块230彼此电连接。存储器芯片210可以堆叠在重分布衬底300上,以与其侧壁彼此对齐。粘合层235可以设置在存储器芯片210之间。粘合层235可以是例如包括电介质材料的聚合物胶带。粘合层235可以插设在连接凸块230之间,并且可以防止连接凸块230之间的电短路。
第一半导体芯片100和第二半导体芯片200可以通过第一连接端子150连接至重分布衬底300。第一连接端子150可以附着到第一半导体芯片100和第二半导体芯片200的下芯片焊盘111和221。第一连接端子150可以是选自焊球、导电凸块和导电柱中的至少一个。第一连接端子150可以包括铜、锡和铅中的一种或多种。第一连接端子150可以各自具有例如大约30μm至大约70μm的厚度。
重分布衬底300可以设置在模制层330上,模制层330覆盖第一半导体芯片100和第二半导体芯片200。模制层330可以具有与重分布衬底300的侧壁对齐的侧壁。模制层330可以具有基本上与第一半导体芯片100和第二半导体芯片200的顶表面共面的顶表面。模制层330可以包括诸如环氧树脂模塑化合物(EMC)的电介质聚合物。
第一底部填充层可以插设在第一半导体芯片100与重分布衬底300之间以及第二半导体芯片200与重分布衬底300之间。第一底部填充层可以填充第一连接端子150之间的间隙。第一底部填充层可以包括例如可热固性树脂或可光固性树脂。第一底部填充层还可以包括无机填充剂或有机填充剂。在一些示例实施例中,可以省略第一底部填充层,模制层330可以填充重分布衬底300与第一半导体芯片100和第二半导体芯片200的底表面之间的间隙。
重分布衬底300可以设置在封装衬底500上,并且可以通过第二连接端子350连接至封装衬底500。重分布衬底300可以包括芯片区和芯片区周围的边缘区。第一半导体芯片100和第二半导体芯片200可以设置在重分布衬底300的芯片区上。
重分布衬底300可以具有与第一半导体芯片100和第二半导体芯片200相邻的顶表面300a以及与顶表面300a相对的底表面300b。重分布衬底300可以包括顺序地堆叠的多个电介质层20和设置在每个电介质层20中的多个重分布图案50。可以通过以上参照图1至图13讨论的方法来形成重分布图案50。不同电介质层20中的重分布图案50可以与以下将讨论的穿通件部分50b彼此电连接。
第二连接端子350可以附着到重分布衬底300的下焊盘。第二连接端子350可以是由锡、铅和/或铜形成的焊球。第二连接端子350可以各自具有大约40μm至大约80μm的厚度。
封装衬底500可以是例如印刷电路板、柔性衬底或带衬底。例如,封装衬底500可以是柔性印刷电路板、刚性印刷电路板和它们的任意组合中的一种,这些板中的每一个包括形成在其中的内部线521。
封装衬底500可以具有彼此相对的顶表面和底表面,并且可以包括上接合焊盘511、外部接合焊盘513和内部线521。上接合焊盘511可以布置在封装衬底500的顶表面上,外部接合焊盘513可以布置在封装衬底500的底表面上。上接合焊盘511可以通过内部线521电连接至外部接合焊盘513。外部接合端子550可以附着到外部接合焊盘513。球栅阵列(BGA)可以被设置为外部接合端子550。
热辐射结构600可以包括热导材料或导热材料。热导材料可以包括金属材料(例如,铜和/或铝)或含碳的材料(例如,石墨烯、石墨和/或碳纳米管)。热辐射结构600可以具有相对高的热导率。例如,单个金属层或多个堆叠的金属层可以用作热辐射结构600。作为另一示例,热辐射结构600可以包括散热器或热管。作为另一示例,热辐射结构600可以被配置为使用水冷却。
热导层或导热层650可以插设在热辐射结构600与第一半导体芯片100和第二半导体芯片200之间。热导层650可以与半导体封装件1000的顶表面和热辐射结构600的底表面接触。热导层650可以包括热界面材料(TIM)。热界面材料可以包括例如聚合物和热导颗粒。热导颗粒可以分布在聚合物中。当半导体封装件1000操作时,从半导体封装件1000产生的热量可以通过热导层650传递至热辐射结构600。
根据图15中所示的实施例,半导体封装件1000可以被配置为使得形成重分布衬底300并且随后将第一半导体芯片100和第二半导体芯片200安装在重分布衬底300上。
重分布衬底300可以具有与第一半导体芯片100和第二半导体芯片200相邻的顶表面300a以及与顶表面300a相对的底表面300b。
重分布衬底300可以包括多个顺序堆叠的电介质层20和设置在每个电介质层20中的多个重分布图案50。如以上参照图1至图13所讨论的,重分布图案50可以形成在电介质层20中。每个重分布图案50可以包括线部50a和穿通件部分50b,线部50a可以具有基本上平坦的顶表面TS和不平坦的底表面BS。在一些示例实施例中,线部50a的底表面BS可以朝向第一半导体芯片100和第二半导体芯片200凸出。
根据图16中所示的实施例,与图15中描绘的实施例不同,半导体封装件1000可以被配置为使得重分布衬底300形成在第一半导体芯片100和第二半导体芯片200的有源表面上。
如以上所讨论的,重分布衬底300可以包括多个顺序堆叠的电介质层20和设置在每个电介质层20中的多个重分布图案50。
如以上参照图1至图13所讨论的,重分布图案50可以形成在电介质层20中。每个重分布图案50可以包括线部50a和穿通件部分50b,线部50a可以具有基本上平坦的顶表面TS和不平坦的底表面BS。在一些示例实施例中,线部50a的底表面可以朝向第一半导体芯片100和第二半导体芯片200凹陷或相对于第一半导体芯片100和第二半导体芯片200凹陷。例如,线部50a的底表面BS可以朝向封装衬底500凸出。
参照图17,重分布衬底300可以包括基体衬底311、穿通件313和包括重分布图案50的重分布层320。
基体衬底311可以是硅衬底或绝缘体上硅(SOI)衬底。可替代地,基体衬底311可以是玻璃衬底、陶瓷衬底、聚合物衬底或可提供合适的保护和/或互连功能的任何合适的衬底。基体衬底311可以包括有源电子器件和/或无源电子器件。基体衬底311可以具有位于其顶部和底表面上的保护电介质层。
穿通件313可以穿透基体衬底311,并且可以将下焊盘315和上焊盘317彼此电连接。穿通件313可以包括诸如钨(W)、铝(Al)或铜(Cu)的金属材料。
重分布层320可以包括多个堆叠的电介质层20和设置在每个电介质层20中的多个重分布图案50。每个重分布图案50可以包括线部50a和穿通件部分50b,线部50a可以具有基本上平坦的顶表面TS和不平坦的底表面BS。在一些示例实施例中,线部50a的底表面BS可以朝向第一半导体芯片100和第二半导体芯片200凸出。
图18、图19和图20示出了示出根据本发明构思的一些示例实施例的半导体封装件的截面图。为了简洁起见,可以省略与以上参照图1至图8讨论的实施例的那些相同的技术特征。
参照图18,根据本实施例的半导体封装件1000可以包括第一半导体封装件1000a和设置在第一半导体封装件1000a上的第二半导体封装件1000b。
第一半导体封装件1000a可以包括下重分布衬底300L、上重分布衬底300U、第一半导体芯片100、金属柱360和模制层370。
如以上所讨论的,下重分布衬底300L和上重分布衬底300U中的每一个可以包括多个电介质层20和多个重分布图案50。每个重分布图案50可以包括线部50a和穿通件部分50b,线部50a可以具有基本上平坦的顶表面TS和不平坦的底表面BS。
第一半导体芯片100可以设置在下重分布衬底300L上。当在平面中观看时,第一半导体芯片100可以设置在下重分布衬底300L的中心区上。第一半导体芯片100可以具有位于其底表面上的芯片焊盘111。第一半导体芯片100的底表面可以被设置为面对下重分布衬底300L的顶表面300a,第一半导体芯片100的芯片焊盘111可以连接至下重分布衬底300L的重分布图案50。第一连接端子150可以附着到第一半导体芯片100的芯片焊盘111和下重分布衬底300L的重分布图案50,并且位于它们之间。
金属柱360可以设置在第一半导体芯片100周围,并且可以将下重分布衬底300L电连接至上重分布衬底300U。金属柱360可以穿透模制层370,并且可以具有与模制层370的顶表面共面的顶表面。金属柱360可以具有与下重分布衬底300L的重分布图案50直接接触的底表面。
模制层370可以设置在下重分布衬底300L与上重分布衬底300U之间,并且可以覆盖第一半导体芯片100。模制层370可以设置在下重分布衬底300L的顶表面300a上,并且可以覆盖或围绕第一半导体芯片100的侧壁和顶表面。模制层370可以填充金属柱360之间的间隙,并且可以具有与金属柱360的长度基本上相同的厚度。模制层370可以包括诸如环氧类模塑化合物的电介质聚合物。模制层370可以在本文中被称作下模制层。
第二半导体封装件1000b可以设置在上重分布衬底300U上。
第二半导体封装件1000b可以包括封装衬底710、第二半导体芯片200和上模制层730。封装衬底710可以是印刷电路板。可替代地,重分布衬底可以用作封装衬底710。金属焊盘705可以设置在封装衬底710的底表面上。
第二半导体芯片200可以设置在封装衬底710上。第二半导体芯片200可以包括集成电路,集成电路可以包括存储器电路、逻辑电路或它们的组合。第二半导体芯片200可以包括芯片焊盘221,其通过设置在封装衬底710中的布线715电连接至金属焊盘705。可以在封装衬底710上设置上模制层730,上模制层730覆盖第二半导体芯片200。上模制层730可以包括诸如环氧类聚合物的电介质聚合物。
连接端子750可以设置在封装衬底710的金属焊盘705与上重分布衬底300U的重分布焊盘之间。
参照图19,根据本实施例的半导体封装件1000可以包括下重分布衬底300L、上重分布衬底300U、第一半导体芯片100、金属柱360、模制层370和第二半导体芯片200。
下重分布衬底300L、上重分布衬底300U、第一半导体芯片100、金属柱360和模制层370可以基本上与参照图18讨论的第一半导体封装件1000a的那些相同。
根据本实施例,第二半导体芯片200可以具有与上重分布衬底300U的电介质层20直接接触的底表面,并且还可以具有与上重分布衬底300U的重分布焊盘直接接触的芯片焊盘221。第二半导体芯片200的芯片焊盘221可以与上重分布衬底300U的重分布焊盘对应,并且可以具有与上重分布衬底300U的重分布焊盘的尺寸和布置基本上相同的尺寸和布置。第二半导体芯片200的芯片焊盘221可以包括诸如铜(Cu)、镍(Ni)、钴(Co)、钨(W)、钛(Ti)、锡(Sn)的金属或它们的任何合金。
参照图20,根据本实施例的半导体封装件1000可以包括第一半导体封装件1000a和设置在第一半导体封装件1000a上的第二半导体封装件1000b。
第一半导体封装件1000a可以包括重分布衬底300、重分布衬底300上的连接衬底400、第一半导体芯片100和模制层450。
如以上所讨论的,重分布衬底300可以包括多个电介质层20和多个重分布图案50。每个重分布图案50可以包括线部50a和穿通件部分50b,线部50a可以具有基本上平坦的顶表面TS和不平坦的底表面BS。
连接衬底400可以具有暴露出重分布衬底300的顶表面的开口,第一半导体芯片100可以设置在连接衬底400的开口中。可以在设置第一半导体芯片100之前或之后设置连接衬底400。例如,孔或开口可以形成在印刷电路板中,具有孔的印刷电路板可以用作连接衬底400。当在平面中观看时,第一半导体芯片100可以设置在重分布衬底300的中心区上。
连接衬底400可以包括基体层410和导电结构420。基体层410可以包括电介质材料。例如,基体层410可以包括碳基材料、陶瓷或聚合物。导电结构420可以包括线图案和连接各个线图案的线穿通件。连接衬底400的导电结构420可以连接至重分布衬底300的焊盘。导电结构420可以包括金属。导电结构420可以包括例如选自铜、铝、金、铅、不锈钢、银、铁中的至少一种以及它们的任何合金。
模制层450可以形成在第一半导体芯片100和连接衬底400上。模制层450可以延伸到第一半导体芯片100和连接衬底400中并且填充第一半导体芯片100与连接衬底400之间的间隙。模制层450可以包括诸如环氧类聚合物的电介质聚合物。模制层450可以部分地暴露出连接衬底400的导电结构420。模制层450可以在本文中被称作下模制层。
第二半导体封装件1000b可以包括封装衬底710、第二半导体芯片200和上模制层730。封装衬底710可以是印刷电路板。可替代地,重分布衬底可以用作封装衬底710。金属焊盘705可以设置在封装衬底710的底表面上。
第二半导体芯片200可以设置在封装衬底710上。第二半导体芯片200可以包括集成电路,集成电路可以包括存储器电路、逻辑电路或它们的组合。第二半导体芯片200可以包括芯片焊盘221,其通过设置在封装衬底710中的布线715电连接至金属焊盘705。可以在封装衬底710上设置上模制层730,上模制层730覆盖第二半导体芯片200。上模制层730可以包括诸如环氧类聚合物的电介质聚合物。
连接端子750可以设置在模制层450的上孔或开口中。连接端子750可以设置在封装衬底710的金属焊盘705与连接衬底400的导电结构420之间。
根据本发明构思的一些示例实施例,硬掩模图案可以用来各向异性地蚀刻电介质层,然后,可以用金属材料填充沟槽以形成重分布图案。因此,重分布图案可以具有基本上垂直于其顶表面的侧壁,并且可以确保获得相邻的重分布图案之间的空间。因此,可能能够实现细线宽的重分布图案,并且实现尺寸紧凑的半导体封装件。
尽管已经结合附图中示出的本发明构思的一些示例实施例描述了本发明构思,但是本领域技术人员将理解,在不脱离本发明构思的范围的情况下,可以做出各种改变和修改。
Claims (20)
1.一种半导体封装件,包括:
重分布衬底,其包括电介质层中的多个重分布线图案;以及
半导体芯片,其位于所述重分布衬底上,所述半导体芯片包括电连接至所述多个重分布线图案的多个芯片焊盘,
其中,所述多个重分布线图案中的每一个包括实质上平面的顶表面和非平面的底表面,并且
其中,所述多个重分布线图案中的每一个包括中心部分和位于所述中心部分的相对侧上的边缘部分,并且所述多个重分布线图案中的每一个在所述中心部分处具有第一厚度作为最小厚度,并且在所述边缘部分处具有第二厚度作为最大厚度。
2.根据权利要求1所述的半导体封装件,其中,所述多个重分布线图案中的每一个的所述第一厚度与所述第二厚度之间的差在0.1μm至0.2μm的范围内。
3.根据权利要求1所述的半导体封装件,其中,所述多个重分布线图案中的每一个的底表面在所述中心部分处向上凸出。
4.根据权利要求1所述的半导体封装件,其中,所述多个重分布线图案中的每一个的底表面在所述边缘部分处具有第一曲率半径,并且在所述中心部分处具有第二曲率半径,所述第二曲率半径不同于所述第一曲率半径。
5.根据权利要求1所述的半导体封装件,其中,所述多个重分布线图案中的每一个的边缘部分包括圆的边缘。
6.根据权利要求5所述的半导体封装件,其中,所述圆的边缘具有0.1μm至0.3μm的曲率半径。
7.根据权利要求1所述的半导体封装件,其中,
所述多个重分布线图案彼此间隔开第一间隔,
所述多个重分布线图案中的每一个具有第一宽度,并且
所述第一宽度和所述第一间隔各自具有1.5μm至2.5μm的范围。
8.根据权利要求1所述的半导体封装件,其中,所述多个重分布线图案中的每一个包括相对于所述电介质层的顶表面以第一角度取向的侧壁,
其中,所述第一角度具有85°至95°的范围。
9.根据权利要求1所述的半导体封装件,其中,所述多个重分布线图案中的每一个包括:
金属图案;以及
阻挡金属图案,其具有覆盖所述金属图案的相对侧壁和所述金属图案的底表面的实质上均匀的厚度。
10.根据权利要求1所述的半导体封装件,其中,所述多个重分布线图案中的每一个的顶表面与所述电介质层的顶表面实质上共面。
11.根据权利要求1所述的半导体封装件,其中,所述多个重分布线图案中的每一个的第二厚度具有2.5μm至4.0μm的范围。
12.根据权利要求1所述的半导体封装件,其中,所述电介质层包括选自聚酰亚胺、聚苯并噁唑、酚醛聚合物和苯并环丁烯聚合物中的至少一个。
13.一种半导体封装件,包括:
重分布衬底,其包括电介质层中的多个重分布图案;以及
半导体芯片,其位于所述重分布衬底上,所述半导体芯片包括电连接至所述多个重分布图案的多个芯片焊盘,
其中,所述多个重分布图案中的每一个包括:
线部,其位于所述电介质层中;以及
穿通件部分,其穿透所述电介质层,并且连接至所述线部,
其中,所述多个重分布图案中的每一个的线部在第一方向上平行于彼此延伸,
其中,所述多个重分布图案的线部中的至少一些在垂直于所述第一方向的第二方向上具有第一宽度,并且
其中,所述多个重分布图案中的每一个的线部包括中心部分和位于所述中心部分的相对侧上的边缘部分,并且所述多个重分布图案中的每一个的线部包括在所述中心部分上向上凸出的底表面。
14.根据权利要求13所述的半导体封装件,其中,所述多个重分布图案中的每一个包括实质上平面的顶表面。
15.根据权利要求13所述的半导体封装件,其中,所述多个重分布图案中的每一个的线部包括在该线部的底表面与该线部的相对侧壁之间的圆的边缘。
16.根据权利要求13所述的半导体封装件,
其中,所述多个重分布图案中的每一个的线部在所述中心部分处具有第一厚度作为最小厚度,并且在所述边缘部分处具有第二厚度作为最大厚度。
17.根据权利要求13所述的半导体封装件,其中,所述多个重分布图案包括:
多个第一重分布图案,所述多个第一重分布图案中的每一个具有所述第一宽度;以及
多个第二重分布图案,所述多个第二重分布图案中的每一个具有大于所述第一宽度的第二宽度,
其中,所述多个第一重分布图案和所述多个第二重分布图案中的每一个的线部在该线部的底表面与该线部的相对侧壁之间具有圆的边缘,
其中,所述多个第一重分布图案中的每一个的圆的边缘具有第一曲率半径,并且
其中,所述多个第二重分布图案中的每一个的圆的边缘具有与所述第一曲率半径不同的第二曲率半径。
18.一种半导体封装件,包括:
封装衬底;
重分布衬底,其位于所述封装衬底上,所述重分布衬底包括光敏聚合物层和位于所述光敏聚合物层中的多个重分布图案;
第一半导体芯片,其位于所述重分布衬底上;
第二半导体芯片,其位于所述重分布衬底上,并且与所述第一半导体芯片间隔开,所述第二半导体芯片包括多个竖直堆叠的存储器芯片;
多个第一连接端子,其位于所述重分布衬底与所述第一半导体芯片之间以及所述重分布衬底与所述第二半导体芯片之间;
多个第二连接端子,其将所述封装衬底连接至所述重分布衬底;
模制层,其位于所述重分布衬底上,所述模制层至少部分地覆盖所述第一半导体芯片和所述第二半导体芯片;以及
热辐射结构,其位于所述封装衬底上,所述热辐射结构覆盖或盖住所述重分布衬底、所述第一半导体芯片以及所述第二半导体芯片,
其中,所述多个重分布图案中的每一个包括:
线部,其在电介质层中沿着一个方向延伸;以及
穿通件部分,其穿透所述电介质层,并且连接至所述线部,
其中,所述多个重分布图案中的每一个的线部包括实质上平面的顶表面、非平面的底表面以及位于所述线部的底表面与相对的第一侧壁和第二侧壁之间的第一圆的边缘与第二圆的边缘,
其中,所述多个重分布图案中的每一个的线部包括中心部分以及位于所述中心部分的相对侧上的第一边缘部分和第二边缘部分,并且
其中,所述多个重分布图案中的每一个的线部在所述中心部分处具有第一厚度作为最小厚度,并且在所述第一边缘部分和所述第二边缘部分处具有第二厚度作为最大厚度。
19.根据权利要求18所述的半导体封装件,其中,在所述多个重分布图案中的每一个的线部的中心部分上,所述底表面在朝向所述第一半导体芯片和所述第二半导体芯片的方向上凸出。
20.根据权利要求18所述的半导体封装件,其中,在所述多个重分布图案中的每一个的线部的中心部分上,所述底表面相对于所述第一半导体芯片和所述第二半导体芯片凹陷。
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