CN114051653A - 半导体装置和半导体装置的制造方法 - Google Patents

半导体装置和半导体装置的制造方法 Download PDF

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CN114051653A
CN114051653A CN202180004245.XA CN202180004245A CN114051653A CN 114051653 A CN114051653 A CN 114051653A CN 202180004245 A CN202180004245 A CN 202180004245A CN 114051653 A CN114051653 A CN 114051653A
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region
concentration
semiconductor substrate
hydrogen
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洼内源宜
吉村尚
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
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    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
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    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
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    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
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    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
CN202180004245.XA 2020-01-17 2021-01-14 半导体装置和半导体装置的制造方法 Pending CN114051653A (zh)

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JP2020006033 2020-01-17
JP2020-006033 2020-01-17
PCT/JP2021/001135 WO2021145397A1 (ja) 2020-01-17 2021-01-14 半導体装置および半導体装置の製造方法

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US (1) US12294025B2 (https=)
JP (1) JP7231066B2 (https=)
CN (1) CN114051653A (https=)
DE (1) DE112021000038T5 (https=)
WO (1) WO2021145397A1 (https=)

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* Cited by examiner, † Cited by third party
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JP2024154238A (ja) * 2023-04-18 2024-10-30 株式会社デンソー 半導体装置
WO2025187565A1 (ja) * 2024-03-05 2025-09-12 株式会社デンソー 半導体装置およびその製造方法

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US20180012762A1 (en) * 2015-09-16 2018-01-11 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US20180350962A1 (en) * 2016-08-12 2018-12-06 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method of semiconductor device
CN109075191A (zh) * 2016-10-17 2018-12-21 富士电机株式会社 半导体装置
CN109314134A (zh) * 2016-12-16 2019-02-05 富士电机株式会社 半导体装置及制造方法
CN110546767A (zh) * 2017-11-15 2019-12-06 富士电机株式会社 半导体装置

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EP2930741B1 (en) 2013-06-26 2022-06-01 Fuji Electric Co., Ltd. Method for manufacturing semiconductor device
JP6277814B2 (ja) 2014-03-25 2018-02-14 株式会社デンソー 半導体装置
CN106062960B (zh) 2014-09-30 2019-12-10 富士电机株式会社 半导体装置及半导体装置的制造方法
WO2016051973A1 (ja) * 2014-10-03 2016-04-07 富士電機株式会社 半導体装置および半導体装置の製造方法
JP6457324B2 (ja) 2015-04-27 2019-01-23 株式会社ジェイエスピー ガラス板用間紙
WO2016204227A1 (ja) 2015-06-17 2016-12-22 富士電機株式会社 半導体装置および半導体装置の製造方法
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JP6756376B2 (ja) * 2016-11-16 2020-09-16 富士電機株式会社 半導体装置
WO2019181852A1 (ja) * 2018-03-19 2019-09-26 富士電機株式会社 半導体装置および半導体装置の製造方法
JP6958740B2 (ja) * 2018-08-14 2021-11-02 富士電機株式会社 半導体装置および製造方法
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JP7243744B2 (ja) * 2019-01-18 2023-03-22 富士電機株式会社 半導体装置および半導体装置の製造方法
WO2023042886A1 (ja) * 2021-09-15 2023-03-23 富士電機株式会社 半導体装置および半導体装置の製造方法
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US20180012762A1 (en) * 2015-09-16 2018-01-11 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US20180350962A1 (en) * 2016-08-12 2018-12-06 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method of semiconductor device
CN109075191A (zh) * 2016-10-17 2018-12-21 富士电机株式会社 半导体装置
CN109314134A (zh) * 2016-12-16 2019-02-05 富士电机株式会社 半导体装置及制造方法
US20190096989A1 (en) * 2016-12-16 2019-03-28 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method of the same
CN110546767A (zh) * 2017-11-15 2019-12-06 富士电机株式会社 半导体装置

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JPWO2021145397A1 (https=) 2021-07-22
US20220123133A1 (en) 2022-04-21
WO2021145397A1 (ja) 2021-07-22
US12294025B2 (en) 2025-05-06
DE112021000038T5 (de) 2022-04-07
JP7231066B2 (ja) 2023-03-01

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