CN113809158A - 具有分段延伸区的晶体管 - Google Patents

具有分段延伸区的晶体管 Download PDF

Info

Publication number
CN113809158A
CN113809158A CN202110509973.8A CN202110509973A CN113809158A CN 113809158 A CN113809158 A CN 113809158A CN 202110509973 A CN202110509973 A CN 202110509973A CN 113809158 A CN113809158 A CN 113809158A
Authority
CN
China
Prior art keywords
segment
region
gate structure
longitudinal axis
extension
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110509973.8A
Other languages
English (en)
Inventor
亨利·奥尔德里奇
约翰·J·艾利斯-蒙纳翰
M·J·阿布-哈利勒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries US Inc
Original Assignee
GlobalFoundries US Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries US Inc filed Critical GlobalFoundries US Inc
Publication of CN113809158A publication Critical patent/CN113809158A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66659Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明涉及具有分段延伸区的晶体管,涉及场效应晶体管的结构以及形成场效应晶体管的结构的方法。在衬底的沟道区上方形成栅极结构。在与该栅极结构的第一侧壁相邻的该衬底中定位第一源极/漏极区,在与该栅极结构的第二侧壁相邻的该衬底中定位第二源极/漏极区,以及在该衬底中定位延伸区。该延伸区包括分别与该第一源极/漏极区叠置的第一及第二区段。该延伸区的该第一与第二区段沿该栅极结构的纵轴隔开。在该延伸区的该第一与第二区段之间沿该栅极结构的该纵轴定位该沟道区的部分。

Description

具有分段延伸区的晶体管
技术领域
本发明涉及半导体装置制造及集成电路,尤其涉及场效应晶体管的结构以及形成场效应晶体管的结构的方法。
背景技术
可使用互补金属氧化物半导体(complementary-metal-oxide-semiconductor;CMOS)制程来建立p型与n型场效应晶体管的组合,将该p型与n型场效应晶体管用作装置,以构建例如逻辑单元(logic cell)。场效应晶体管通常包括源极、漏极、在该源极与漏极之间提供沟道区的本体、以及与该沟道区叠置的栅极电极。当向该栅极电极施加超过特征阈值电压的控制电压时,在该源极与漏极之间的该沟道区中发生载流子流(carrier flow),从而产生装置输出电流。
随着装置尺寸增加,该装置处于“关”时的电容(也就是,Coff)增加,且该装置处于“开”时的电阻(也就是,Ron)减小,但Coff与Ron的乘积(也就是,品质因数)保持不变。提高品质因数的历史方法包括为获得较高载流子迁移率的应变工程、栅极氧化物微缩、以及不同的装置几何结构(例如,鳍式场效应晶体管)。
需要改进的场效应晶体管的结构以及形成场效应晶体管的结构的方法。
发明内容
在本发明的一个实施例中,提供一种场效应晶体管的结构。该结构包括位于衬底的沟道区上方的栅极结构。该栅极结构具有纵轴、第一侧壁、以及与该第一侧壁相对的第二侧壁。该结构还包括:位于与该栅极结构的该第一侧壁相邻的该衬底中的第一源极/漏极区,位于与该栅极结构的该第二侧壁相邻的该衬底中的第二源极/漏极区,以及位于该衬底中的延伸区。该延伸区包括分别与该第一源极/漏极区叠置的第一区段及第二区段。该延伸区的该第一区段与该第二区段沿该栅极结构的该纵轴隔开。在该延伸区的该第一区段与该第二区段之间沿该栅极结构的该纵轴定位该沟道区的部分。
在本发明的一个实施例中,提供一种形成场效应晶体管的结构的方法。该方法包括:形成栅极结构,该栅极结构设于衬底的沟道区上方;在与该栅极结构的第一侧壁相邻的该衬底中形成第一源极/漏极区;在与该栅极结构的第二侧壁相邻的该衬底中形成第二源极/漏极区;以及在该衬底中形成延伸区。该延伸区包括分别与该第一源极/漏极区叠置的第一区段及第二区段,且该延伸区的该第一区段与该第二区段沿该栅极结构的纵轴隔开。在该延伸区的该第一区段与该第二区段之间沿该栅极结构的该纵轴定位该沟道区的部分。
附图说明
包含于并构成本说明书的一部分的附图示例说明本发明的各种实施例,并与上面所作的有关本发明的概括说明以及下面所作的有关所述实施例的详细说明一起用以解释本发明的所述实施例。在所述附图中,类似的附图标记表示不同视图中类似的特征。
图1显示依据本发明的实施例的场效应晶体管的结构的顶视图。
图2显示大体沿图1中的线2-2所作的剖视图。
图3显示处于图1之后的制造阶段的该结构的顶视图。
图4显示大体沿图3中的线4-4所作的剖视图。
图4A显示大体沿图3中的线4A-4A所作的剖视图。
图5显示依据本发明的替代实施例的场效应晶体管的结构的顶视图。
图6显示大体沿图5中的线6-6所作的剖视图。
图6A显示大体沿图5中的线6A-6A所作的剖视图。
具体实施方式
请参照图1、2并依据本发明的实施例,场效应晶体管的结构10包括设于衬底14上方的栅极结构12。衬底14可由轻掺杂(例如,轻p型掺杂)的单晶半导体材料(例如单晶硅)组成。浅沟槽隔离区16可围绕衬底14的主动区。浅沟槽隔离区16可通过利用光刻及蚀刻制程在衬底14中定义沟槽,通过化学气相沉积沉积由介电材料(例如,二氧化硅)组成的层,并利用化学机械抛光平坦化来形成。
栅极结构12在衬底14的该主动区域上方并贯穿该主动区域沿纵轴18横向延伸。栅极结构12可包括由导体(例如掺杂多晶硅(即,多晶硅)或功函数金属)组成的栅极电极20,以及由电性绝缘体(例如二氧化硅)或高k介电材料(例如氧化铪)组成的栅极介电质22。邻近栅极结构12的侧表面或侧壁19、21设置侧间隙壁24。侧间隙壁24可通过在栅极结构12上方沉积由介电材料(例如,氮化硅)组成的共形层,并利用非等向性蚀刻制程(例如反应离子蚀刻)蚀刻所沉积的共形层来形成。
结构10包括邻近栅极结构12的以相对的间隙壁包覆的侧壁19设置的源极/漏极区26及源极/漏极区28。本文中所使用的术语“源极/漏极区”是指可充当场效应晶体管的源极或漏极的半导体材料掺杂区。在一个实施例中,源极/漏极区26可提供结构10中的源极,且源极/漏极区28可提供结构10中的漏极。在一个替代实施例中,源极/漏极区26可提供结构10中的漏极,且源极/漏极区28可提供结构10中的源极。
源极/漏极区26、28经掺杂以具有相同极性的导电类型。为此,在衬底14的相应部分中通过离子注入制程可同时形成源极/漏极区26、28。源极/漏极区26、28含有一定浓度的n型或p型掺杂物,并可为重掺杂。在一个实施例中,通过注入提供p型电性导电性的p型掺杂物(例如,硼)的离子在衬底14中可形成源极/漏极区26、28。在一个实施例中,通过注入提供n型导电性的n型掺杂物(例如,磷及/或砷)的离子在衬底14中可形成源极/漏极区26、28。源极/漏极区26与源极/漏极区28的掺杂物浓度可相等或实质上相等。
离子注入引入能量离子,如单箭头示意标示,离子轨迹停止于衬底14中的一定深度范围上方。可从合适的源气体生成该离子,并利用离子注入工具以给定的注入条件将该离子注入衬底14中。可选择该注入条件(例如,离子种类、剂量、动能、倾斜角度)以调节源极/漏极区28的特性(例如,深度分布)。栅极结构12可用以自对准形成源极/漏极区26、28的该离子注入制程。
源极/漏极区26、28可具有与衬底14的顶部表面11重合的顶部表面,且源极/漏极区26、28可完全位于衬底14的顶部表面11处及下方。由衬底14的部分提供的沟道区17横向设于源极/漏极区26与源极/漏极区28之间。源极/漏极区26具有边界30,其定义导电类型从源极/漏极区26的导电类型变为沟道区17的导电类型的界面。源极/漏极区28也具有边界30,其定义导电类型从源极/漏极区28的导电类型变为沟道区17的导电类型的界面。边界30相对于衬底14的顶部表面11延伸至深度d1。
请参照图3、4、4A,其中,类似的附图标记表示图1、2中类似的特征,且在下一制造阶段,可邻近源极/漏极区26设置延伸区32,并可邻近源极/漏极区28设置延伸区34。延伸区32、34可通过掩蔽离子注入制程形成于图案化区段38中。为此,可通过光刻制程形成注入掩膜36,该注入掩膜包括设于衬底14的未掩蔽部分(在其中形成延伸区32、34的该些区段)上方的开口。注入掩膜36可包括例如有机光阻层,其通过旋涂制程铺设、经预烘烤、暴露于通过光掩膜投射的光、曝光后烘烤、以及用化学显影剂显影。在形成注入掩膜36以后,通过离子注入在衬底14的该未掩蔽部分中可形成延伸区32的区段38以及延伸区34的区段38。
延伸区32、34的区段38含有具有与被包含于源极/漏极区26、28中的掺杂物相同的电性导电类型(也就是,极性类型)的一定浓度的掺杂物,并可为重掺杂。在源极/漏极区26、28具有p型电性导电性的一个实施例中,延伸区32、34的区段38可通过注入提供p型电性导电性的p型掺杂物(例如,硼)的离子形成于衬底14中。在源极/漏极区26、28具有n型电性导电性的一个替代实施例中,延伸区32、34的区段38可通过注入提供n型电性导电性的n型掺杂物(例如,磷及/或砷)的离子形成于衬底14中。延伸区32的区段38与延伸区34的区段38的掺杂物浓度可相等或实质上相等。
离子注入制程引入能量离子,如单箭头示意标示,离子轨迹停止于衬底14中的一定深度范围上方。可从合适的源气体生成该离子,并利用离子注入工具以给定的注入条件将该离子注入衬底14中。可选择该注入条件(例如,离子种类、剂量、动能、倾斜角度)以调节延伸区32、34的区段38的特性(例如,深度分布)。注入掩膜36具有足以在该能量离子到达衬底14的掩蔽部分之前阻止该能量离子的厚度。在形成延伸区32、34的区段38之后,可接着通过例如灰化来移除注入掩膜36。
延伸区32、34的区段38定位于栅极结构12及其侧间隙壁24下方的隔开的位置处,其反映注入掩膜36中的开口的位置。延伸区32的各区段38及延伸区34的各区段38具有边界33,其定义导电类型从延伸区32、34的导电类型变为衬底14的导电类型的界面。边界33相对于衬底14的顶部表面11延伸至深度d1。延伸区32、34的区段38有效缩短在区段38的位置处的栅极长度以及沟道区17的宽度尺寸。
延伸区32的区段38与源极/漏极区26叠置,并从源极/漏极区26横向延伸,以终止于边界33的侧边缘。延伸区32的区段38沿栅极结构12的纵轴18以间隔布置的方式横向定位。延伸区32的区段38在栅极结构12的侧壁19处的侧间隙壁24下方以及栅极结构12的部分下方沿横切于纵轴18的方向定位。
延伸区34的区段38与源极/漏极区28叠置,并从源极/漏极区28横向延伸,以终止于边界33的侧边缘。延伸区34的区段38也沿栅极结构12的纵轴18(也就是,沿平行于纵轴18的方向)隔开。延伸区32的区段38也在栅极结构12的侧壁21处的侧间隙壁24下方以及栅极结构12的部分下方沿横切于纵轴18的方向定位。
在一个实施例中,延伸区32、34的区段38沿栅极结构12的纵轴18可具有不变的间距。在一个实施例中,延伸区32、34的区段38沿栅极结构的纵轴18可具有可变的间距。
沟道区17的部分40在延伸区32的区段38之间沿栅极结构12的纵轴18横向定位。沟道区17的部分40可将延伸区32的相邻区段38彼此完全隔开,并可在源极/漏极区26的边界30的部分上方与源极/漏极区26共同延伸(也就是,与源极/漏极区共用共同边界)。沟道区17的部分40也在延伸区34的区段38之间沿纵轴18横向定位,并可在源极/漏极区28的边界30的部分上方与源极/漏极区28共同延伸(也就是,与源极/漏极区共用共同边界)。部分40可将延伸区34的相邻区段38彼此完全隔开。部分40沿横切于纵轴18的方向从位于源极/漏极区26的边界30的一端横跨至位于源极/漏极区28的边界30的另一端。
沟道区17的部分41沿横切于纵轴18的方向横向定位于延伸区32的区段38之间及延伸区34的区段38之间。沟道区17的部分40沿该横切方向可宽于部分41,且部分40可从与源极/漏极区26共用的边界30延伸至与源极/漏极区28共用的边界30。
组合后,延伸区32的区段38及沟道区17的部分40沿平行于栅极结构12的纵轴18的方向并邻近栅极结构12的侧壁19提供调制掺杂分布(modulated doping profile)。类似地,组合后,延伸区34的区段38及沟道区17的部分40沿平行于栅极结构12的纵轴18的方向并邻近栅极结构12的侧壁21提供调制掺杂分布。由于在它们形成期间的掩蔽,该不同的调制掺杂分布在沿纵轴18的方向上匹配。
通过电容(Coff)减小,与未分段的延伸区相比,分段的延伸区32、34可提供品质因素的显着改进。可在没有应变工程或栅极氧化物微缩、且无需采取不同的装置几何结构(例如,鳍式场效应晶体管)的情况下实现该改进。
在一个替代实施例中,延伸区32与延伸区34可以不对称的方式形成。在此方面,延伸区32可形成有区段38,而延伸区34可在没有掩蔽的情况下整体形成,从而延伸区34不具有区段38。因此,延伸区34可为连续的,且不具有沟道区17的部分40。
接着执行中间工艺(middle-of-line;MOL)制程及后端工艺(back-end-of-line;BEOL)制程,其包括形成与该场效应晶体管耦接的互连结构的金属特征,例如接触、过孔,以及线路。该互连结构可通过沉积由介电材料组成的层间介电层,并在该各种层间介电层中形成该金属特征以定义金属化层级来形成。
请参照图5、6、6A,其中,类似的附图标记表示图4、4A中类似的特征,且依据本发明的替代实施例,结构10可包括环状区42及环状区44,它们分别利用在适当位置的注入掩膜36通过离子注入以区段48形成。环状区42的区段48可与延伸区32的区段38在位置上重合并叠置。环状区44的区段48可与延伸区34的区段38在位置上重合并叠置。与延伸区32、34相比,环状区42、44在衬底14中延伸至较大的深度。
环状区42、44的区段48可沿栅极结构12的纵轴18横向定位,并由沟道区17的未注入部分40隔开。环状区42、44的区段48通常位于延伸区32、34的边界33下方以及源极/漏极区26、28的边界的至少一部分下方。沟道区17的部分40在环状区42的区段48之间沿栅极结构12的纵轴18横向定位。部分40将环状区42的相邻区段48彼此完全隔开。沟道区17的部分40也在环状区44的区段48之间沿栅极结构12的纵轴18横向定位。部分40将环状区44的相邻区段48彼此完全隔开。沟道区17的部分43也在环状区42的区段48与环状区44的区段48之间沿横切于栅极结构12的纵轴18的方向横向定位。部分40沿该横切方向宽于部分43,且部分41(图4A)也沿该横切方向宽于部分43。
环状区42、44含有具有与被包含于源极/漏极区26、28及延伸区32、34中的掺杂物相反的电性导电类型(也就是,极性类型)的一定浓度的掺杂物。环状区42、44具有与沟道区17相同的导电类型,并局部增加沟道区17的掺杂浓度。在后一方面,与未注入的沟道区17相比,环状区42、44具有较高的掺杂物浓度。在源极/漏极区26、28及延伸区32、34具有p型电性导电性的一个实施例中,环状区42、44可通过注入提供n型电性导电性的n型掺杂物(例如,磷及/或砷)的离子形成。在源极/漏极区26、28及延伸区32、34具有n型电性导电性的一个替代实施例中,环状区42、44可通过注入提供p型导电性的p型掺杂物(例如,硼)的离子形成。环状区42及环状区44具有相等或实质上相等的掺杂物浓度。
离子注入制程引入能量离子,如单箭头示意标示,离子轨迹停止于衬底14中的一定深度范围上方。可从合适的源气体生成该离子,并利用离子注入工具以给定的注入条件将该离子注入衬底14中。可选择该注入条件(例如,离子种类、剂量、动能、倾斜角度)以调节环状区42、44的特性(例如,深度分布)。注入掩膜36具有足以在该能量离子到达衬底14的掩蔽部分之前阻止该能量离子的厚度。在形成延伸区32、34及环状区42、44之后,可接着通过例如灰化来移除注入掩膜36。
在一个替代实施例中,延伸区32、34及环状区42、44可以不对称的方式形成。在此方面,延伸区32可形成有区段38且环状区42可形成有区段48,而延伸区34及环状区44可在没有掩蔽的情况下整体形成,从而延伸区34不具有区段38,且环状区44不具有区段48。延伸区34及环状区44沿该栅极结构的纵轴18是连续的,且不具有沟道区17的部分40。
上述方法用于集成电路芯片的制造。制造者可以原始晶圆形式(例如,作为具有多个未封装芯片的单个晶圆)、作为裸管芯,或者以封装形式分配所得的集成电路芯片。在后一种情况中,该芯片设于单芯片封装件中(例如塑料承载件,其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装件中(例如陶瓷承载件,其具有单面或双面互连或嵌埋互连)。在任何情况下,可将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成,作为中间产品或最终产品的部分。
本文中引用术语例如“垂直”、“水平”等作为示例来建立参考框架,并非限制。本文中所使用的术语“水平”被定义为与半导体衬底的传统平面平行的平面,而不论其实际的三维空间取向。术语“垂直”及“正交”是指垂直于如刚刚所定义的水平面的方向。术语“横向”是指在该水平平面内的方向。
本文中引用的由近似语言例如“大约”、“大致”及“基本上”所修饰的术语不限于所指定的精确值。该近似语言可对应于用以测量该值的仪器的精度,且除非另外依赖于该仪器的精度,否则可表示所述值的+/-10%。
与另一个特征“连接”或“耦接”的特征可与该另一个特征直接连接或耦接,或者可存在一个或多个中间特征。如果不存在中间特征,则特征可与另一个特征“直接连接”或“直接耦接”。如存在至少一个中间特征,则特征可与另一个特征“非直接连接”或“非直接耦接”。在另一个特征“上”或与其“接触”的特征可直接在该另一个特征上或与其直接接触,或者可存在一个或多个中间特征。如果不存在中间特征,则特征可直接在另一个特征“上”或与其“直接接触”。如存在至少一个中间特征,则特征可“不直接”在另一个特征“上”或与其“不直接接触”。
对本发明的各种实施例所作的说明是出于示例说明的目的,而非意图详尽无遗或限于所揭示的实施例。许多修改及变更对于本领域的普通技术人员将显而易见,而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场已知技术上的技术改进,或者使本领域的普通技术人员能够理解本文中所揭露的实施例。

Claims (20)

1.一种场效应晶体管的结构,该结构包括:
衬底,包括沟道区;
栅极结构,位于该沟道区上方,该栅极结构具有纵轴、第一侧壁、以及与该第一侧壁相对的第二侧壁;
第一源极/漏极区,位于与该栅极结构的该第一侧壁相邻的该衬底中;
第二源极/漏极区,位于与该栅极结构的该第二侧壁相邻的该衬底中;以及
第一延伸区,位于该衬底中,该第一延伸区包括分别与该第一源极/漏极区叠置的第一区段及第二区段,且该第一延伸区的该第一区段与该第二区段沿该栅极结构的该纵轴隔开,
其中,该沟道区包括在该第一延伸区的该第一区段与该第二区段之间沿该栅极结构的该纵轴定位的部分。
2.如权利要求1所述的结构,其中,该沟道区的该部分与该第一源极/漏极区共同延伸。
3.如权利要求1所述的结构,其中,该沟道区的该部分将该第一延伸区的该第一区段与该第一延伸区的该第二区段完全隔开。
4.如权利要求1所述的结构,其中,该第一延伸区具有第一导电类型,且该沟道区具有与该第一导电类型相反的第二导电类型。
5.如权利要求1所述的结构,还包括:
第二延伸区,位于该衬底中,该第二延伸区包括分别与该第二源极/漏极区叠置的第一区段及第二区段,该第二延伸区的该第一区段与该第二区段沿该栅极结构的该纵轴隔开。
6.如权利要求5所述的结构,其中,该沟道区包括在该第二延伸区的该第一区段与该第二区段之间沿该栅极结构的该纵轴定位的第二部分。
7.如权利要求5所述的结构,其中,该沟道区包括在该第一延伸区的该第一区段与该第二延伸区的该第一区段之间横切于该栅极结构的该纵轴定位的第二部分,且该沟道区包括在该第一延伸区的该第二区段与该第二延伸区的该第二区段之间横切于该栅极结构的该纵轴定位的第三部分。
8.如权利要求1所述的结构,还包括:
第一环状区,位于该衬底中,该第一环状区包括分别与该第一延伸区叠置的第一区段及第二区段,且该第一环状区的该第一区段与该第二区段沿该栅极结构的该纵轴隔开。
9.如权利要求8所述的结构,其中,该沟道区包括在该第一环状区的该第一区段与该第二区段之间沿该栅极结构的该纵轴定位的第二部分。
10.如权利要求8所述的结构,还包括:
第二延伸区,位于该衬底中,该第二延伸区包括分别与该第二源极/漏极区叠置的第一区段及第二区段,且该第二延伸区的该第一区段与该第二区段沿该栅极结构的该纵轴隔开。
11.如权利要求10所述的结构,还包括:
第二环状区,位于该衬底中,该第二环状区包括分别与该第二延伸区叠置的第一区段及第二区段,且该第二环状区的该第一区段与该第二区段沿该栅极结构的该纵轴隔开。
12.如权利要求11所述的结构,其中,该沟道区包括在该第二环状区的该第一区段与该第二区段之间沿该栅极结构的该纵轴定位的第二部分。
13.如权利要求8所述的结构,其中,该第一延伸区具有第一导电类型,该沟道区及该第一环状区具有与该第一导电类型相反的第二导电类型,且与该沟道区相比,该第一环状区含有较高的掺杂物浓度。
14.一种形成场效应晶体管的结构的方法,该方法包括:
形成栅极结构,该栅极结构设于衬底的沟道区上方;
在与该栅极结构的第一侧壁相邻的该衬底中形成第一源极/漏极区;
在与该栅极结构的第二侧壁相邻的该衬底中形成第二源极/漏极区;以及
在该衬底中形成第一延伸区,
其中,该第一延伸区包括分别与该第一源极/漏极区叠置的第一区段及第二区段,该第一延伸区的该第一区段与该第二区段沿该栅极结构的纵轴隔开,且该沟道区包括在该第一延伸区的该第一区段与该第二区段之间沿该栅极结构的该纵轴定位的第一部分。
15.如权利要求14所述的方法,其中,在该衬底中形成该第一延伸区包括:
在该衬底上方形成图案化掩膜;以及
利用该衬底上方的该图案化掩膜向该衬底中引入掺杂物,以形成该第一延伸区的该第一区段及该第二区段。
16.如权利要求15所述的方法,其中,通过离子注入制程引入该掺杂物。
17.如权利要求14所述的方法,还包括:
在该衬底中形成第二延伸区,
其中,该第二延伸区包括分别与该第二源极/漏极区叠置的第一区段及第二区段,该第二延伸区的该第一区段与该第二区段沿该栅极结构的该纵轴隔开,且该沟道区包括在该第二延伸区的该第一区段与该第二区段之间沿该栅极结构的该纵轴定位的第二部分。
18.如权利要求14所述的方法,还包括:
在该衬底中形成第一环状区,
其中,该第一环状区包括分别与该第一延伸区叠置的第一区段及第二区段,该第一环状区的该第一区段与该第二区段沿该栅极结构的该纵轴隔开,且该沟道区包括在该第一环状区的该第一区段与该第二区段之间沿该栅极结构的该纵轴定位的第二部分。
19.如权利要求18所述的方法,还包括:
在该衬底中形成第二延伸区,
其中,该第二延伸区包括分别与该第二源极/漏极区叠置的第一区段及第二区段,该第二延伸区的该第一区段与该第二区段沿该栅极结构的该纵轴隔开,且该沟道区包括在该第二延伸区的该第一区段与该第二区段之间沿该栅极结构的该纵轴定位的第三部分。
20.如权利要求19所述的方法,还包括:
在该衬底中形成第二环状区,
其中,该第二环状区包括分别与该第二延伸区叠置的第一区段及第二区段,该第二环状区的该第一区段与该第二区段沿该栅极结构的该纵轴隔开,且该沟道区包括在该第二环状区的该第一区段与该第二区段之间沿该栅极结构的该纵轴定位的第四部分。
CN202110509973.8A 2020-06-11 2021-05-11 具有分段延伸区的晶体管 Pending CN113809158A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/899,086 2020-06-11
US16/899,086 US11205701B1 (en) 2020-06-11 2020-06-11 Transistors with sectioned extension regions

Publications (1)

Publication Number Publication Date
CN113809158A true CN113809158A (zh) 2021-12-17

Family

ID=78718882

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110509973.8A Pending CN113809158A (zh) 2020-06-11 2021-05-11 具有分段延伸区的晶体管

Country Status (3)

Country Link
US (1) US11205701B1 (zh)
CN (1) CN113809158A (zh)
DE (1) DE102021111650A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006053241A2 (en) * 2004-11-12 2006-05-18 Texas Instruments Incorporated Ultra-shallow arsenic junction formation in silicon germanium
US20080179673A1 (en) * 2007-01-25 2008-07-31 Ka-Hing Fung Replacing symmetric transistors with asymmetric transistors
US20090121286A1 (en) * 2007-11-14 2009-05-14 Qimonda Ag Integrated Circuit Comprising a Field Effect Transistor and Method of Fabricating the Same
US20100308405A1 (en) * 2009-06-08 2010-12-09 International Business Machines Corporation Mosfet on silicon-on-insulator with internal body contact
CN102893380A (zh) * 2009-11-09 2013-01-23 国际商业机器公司 不对称外延生长及其应用
DE102015003082A1 (de) * 2015-03-11 2016-09-15 Elmos Semiconductor Aktiengesellschaft MOS Transistor mit einem verbesserten Einschaltwiderstand
CN110085676A (zh) * 2015-04-29 2019-08-02 意法半导体公司 具有半导体鳍结构的隧穿场效应晶体管
CN110783409A (zh) * 2018-07-26 2020-02-11 台湾积体电路制造股份有限公司 具有低闪烁噪声的半导体装置和其形成方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121666A (en) 1997-06-27 2000-09-19 Sun Microsystems, Inc. Split gate oxide asymmetric MOS devices
US6475868B1 (en) 1999-08-18 2002-11-05 Advanced Micro Devices, Inc. Oxygen implantation for reduction of junction capacitance in MOS transistors
US7190050B2 (en) * 2005-07-01 2007-03-13 Synopsys, Inc. Integrated circuit on corrugated substrate
US7364957B2 (en) 2006-07-20 2008-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for semiconductor device with improved source/drain junctions
US7704844B2 (en) * 2007-10-04 2010-04-27 International Business Machines Corporation High performance MOSFET
US8278197B2 (en) * 2008-05-30 2012-10-02 International Business Machines Corporation Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device
DE102008049719A1 (de) 2008-09-30 2010-04-08 Advanced Micro Devices, Inc., Sunnyvale Asymmetrische Transistorbauelemente, die durch asymmetrische Abstandshalter und eine geeignete Implantation hergestellt sind
US8236661B2 (en) 2009-09-28 2012-08-07 International Business Machines Corporation Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage
JP2011249586A (ja) * 2010-05-27 2011-12-08 Elpida Memory Inc 半導体装置の製造方法
KR101843595B1 (ko) * 2013-06-17 2018-03-30 매그나칩 반도체 유한회사 반도체 소자 및 그 제조방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006053241A2 (en) * 2004-11-12 2006-05-18 Texas Instruments Incorporated Ultra-shallow arsenic junction formation in silicon germanium
US20080179673A1 (en) * 2007-01-25 2008-07-31 Ka-Hing Fung Replacing symmetric transistors with asymmetric transistors
US20090121286A1 (en) * 2007-11-14 2009-05-14 Qimonda Ag Integrated Circuit Comprising a Field Effect Transistor and Method of Fabricating the Same
US20100308405A1 (en) * 2009-06-08 2010-12-09 International Business Machines Corporation Mosfet on silicon-on-insulator with internal body contact
CN102893380A (zh) * 2009-11-09 2013-01-23 国际商业机器公司 不对称外延生长及其应用
DE102015003082A1 (de) * 2015-03-11 2016-09-15 Elmos Semiconductor Aktiengesellschaft MOS Transistor mit einem verbesserten Einschaltwiderstand
CN110085676A (zh) * 2015-04-29 2019-08-02 意法半导体公司 具有半导体鳍结构的隧穿场效应晶体管
CN110783409A (zh) * 2018-07-26 2020-02-11 台湾积体电路制造股份有限公司 具有低闪烁噪声的半导体装置和其形成方法

Also Published As

Publication number Publication date
US11205701B1 (en) 2021-12-21
DE102021111650A1 (de) 2021-12-16
US20210391425A1 (en) 2021-12-16

Similar Documents

Publication Publication Date Title
US9728632B2 (en) Deep silicon via as a drain sinker in integrated vertical DMOS transistor
US7064385B2 (en) DMOS-transistor with lateral dopant gradient in drift region and method of producing the same
US6524916B1 (en) Controlled gate length and gate profile semiconductor device and manufacturing method therefor
US5016067A (en) Vertical MOS transistor
US20040251492A1 (en) LDMOS transistors and methods for making the same
US20030119229A1 (en) Method for fabricating a high-voltage high-power integrated circuit device
JP2008514007A (ja) スタック状ヘテロドーピング周縁部及び徐々に変化するドリフト領域を備えた促進された表面電界低減化高耐圧p型mosデバイス
US10164006B1 (en) LDMOS FinFET structures with trench isolation in the drain extension
JPH02239633A (ja) サブミクロンシリコンゲートmosfetの製造方法
US6767778B2 (en) Low dose super deep source/drain implant
US20220277960A1 (en) Manufacturing method of semiconductor device using gate-through implantation
CN108231767B (zh) 具有多个氮化层的装置结构
US20190131406A1 (en) Ldmos finfet structures with shallow trench isolation inside the fin
CN109585558B (zh) 具有多个栅极结构的ldmos finfet结构
US20210090953A1 (en) Self-Aligned Trench MOSFET Contacts Having Widths Less Than Minimum Lithography Limits
US11205701B1 (en) Transistors with sectioned extension regions
CN113224137A (zh) 具有不对称设置的源/漏区的晶体管
US6110786A (en) Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof
US11239366B2 (en) Transistors with an asymmetrical source and drain
TWI830292B (zh) 具有多重厚度緩衝介電層的橫向擴散金屬氧化物半導體裝置
CN113437149B (zh) 半导体结构及其形成方法
US11888062B2 (en) Extended-drain metal-oxide-semiconductor devices with a silicon-germanium layer beneath a portion of the gate
EP4235797A1 (en) Extended-drain metal-oxide-semiconductor devices with a gap between the drain and body wells
KR100266689B1 (ko) 고전압 수평 확산 모스 트랜지스터 제조방법
US7402494B2 (en) Method for fabricating high voltage semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination