CN113745216A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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CN113745216A
CN113745216A CN202110412708.8A CN202110412708A CN113745216A CN 113745216 A CN113745216 A CN 113745216A CN 202110412708 A CN202110412708 A CN 202110412708A CN 113745216 A CN113745216 A CN 113745216A
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epitaxial
layer
nanostructures
epitaxial layer
semiconductor
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CN113745216B (zh
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沙哈吉·B·摩尔
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明描述了半导体器件及其形成方法。半导体器件包括位于衬底上的纳米结构和与纳米结构接触的源极/漏极区。源极/漏极区包括外延端帽，其中，每个外延端帽形成在纳米结构的一个纳米结构的端部处。源极/漏极区还包括与外延端帽接触的外延体和形成在外延体上的外延顶帽。半导体器件还包括形成在纳米结构上的栅极结构。本申请的实施例提供了半导体器件及其形成方法。

Description

半导体器件及其形成方法
技术领域
本申请的实施例涉及半导体器件及其形成方法。
背景技术
随着半导体技术的进步，对更高的存储容量，更快的处理系统，更高的性能以及更低的成本的需求不断增长。为了满足这些需求，半导体工业持续按比例缩小半导体器件的尺寸，并且引入了诸如全环栅场效应晶体管和鳍式场效应晶体管(finFET)的三维晶体管。
发明内容
本申请的实施例提供一种半导体器件，包括：多个纳米结构，位于衬底上；源极/漏极区，与所述多个纳米结构接触，所述源极/漏极区包括：多个外延端帽，其中，每个外延端帽形成在所述多个纳米结构的一个纳米结构的端部处；外延体，与所述多个外延端帽接触；以及外延顶帽，形成在所述外延体上；以及栅极结构，形成在所述多个纳米结构上。
本申请的实施例提供一种半导体器件，包括：多个纳米结构，其中，所述多个纳米结构的一个纳米结构包括非平坦的外表面；栅极介电层，环绕包裹所述多个纳米结构的每个纳米结构；栅电极，设置在所述栅极介电层上和所述多个纳米结构上；源极/漏极区，与所述多个纳米结构接触，所述源极/漏极区包括：多个外延端帽，其中，外延端帽形成在所述纳米结构的端部处并且包括第一掺杂剂浓度；以及外延体，与所述外延端帽接触，并且所述外延体包括大于所述第一掺杂剂浓度的第二掺杂剂浓度。
本申请的实施例提供一种方法，包括：在衬底上形成多个纳米结构；形成多个间隔件，其中，每个间隔件位于所述多个纳米结构的纳米结构对之间；蚀刻所述衬底以形成凹槽；在所述多个纳米结构的侧壁上、所述多个间隔件的侧壁上以及在所述凹槽中沉积第一外延层；蚀刻所述第一外延层以在所述凹槽中形成多个外延端帽和外延基底，其中，每个外延端帽形成在所述多个纳米结构的纳米结构的侧壁上，并且所述外延基底与所述多个间隔件的间隔件接触；在所述多个端帽和所述外延基底上沉积第二外延层；蚀刻所述第二外延层；以及在蚀刻的所述第二外延层上沉积第三外延层。
本申请的实施例提供了用于半导体器件的外延结构。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明。要强调的是，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的用于在半导体器件中制造多层外延源极/漏极结构的方法的流程图。
图2A至图2C、图3A、图3B和图4至图9示出了根据一些实施例的半导体器件的处于他们的制造工艺的各个阶段的各个截面图。
图10示出了根据一些实施例的半导体器件的部分的放大图和掺杂剂浓度分布的示意图。
图11和图12示出了根据一些实施例的具有多层外延源极/漏极结构的半导体器件的处于他们的制造工艺的各个阶段的各个截面图。
现在将参考附图描述示出的实施例。在图中，相似的参考数字通常表示相同的、功能相似的和/或结构的相似的元件。
具体实施方式
以下公开内容提供了许多用于实现所提供的主题的不同部件的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。另外，本发明可以在各个实例中重复参考数字和/或字母。该重复是出于简化和清楚的目的，其本身并不指示所讨论的各种实施例和/或结构之间的关系。
进一步，为了便于描述，在此可以使用诸如“在…下面”、“在…之下”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
如本文所使用的首字母缩写词“FET”是指场效应晶体管。FET的实例是金属氧化物半导体场效应晶体管(MOSFET)。MOSFET可以是，例如，(i)在诸如半导体晶圆的衬底的平坦表面中和平坦表面上构建的平面结构，或者(ii)与垂直结构一起构建。
术语“FinFET”是指形成在相对于晶圆的平坦表面垂直定向的鳍的上方的FET。
“S/D”是指形成FET的两个端子的源极和/或漏极结。
如本文所使用的术语“垂直”意味着名义上垂直于衬底的表面。
如本文所使用的术语“标称”是指在产品或工艺的设计阶段设定的，用于组件或工艺操作的特性或参数的期望值或目标值，以及高于和/或低于所期望的值的范围值。范围值通常是由于制造工艺中的轻微变化或公差。
如本文中所使用的术语“约”和“基本上”表示给定量的值，该给定量的值可以基于与主题半导体器件相关的特定技术节点而变化。在一些实施例中，基于特定技术节点，术语“约”和“基本上”可以表示给定量的值，该给定量的值在例如该值的5％(例如，该值的±1％、±2％、±3％、±4％、±5％)、该值的10％、该值的20％等内变化。
术语“垂直方向”和“水平方向”分别是指如本文图中所示出的z方向和x方向。
本发明提供了半导体器件中和/或集成电路中的示例性场效应晶体管(FET)器件(例如，全环栅(GAA)FET、鳍式FET(finFET)、水平或垂直GAA finFET或平面FET)及其示例性制造方法。
在半导体器件中实施外延生长材料以提高器件速度并降低器件功耗。例如，由掺杂的外延材料形成的晶体管器件的源极/漏极端子可以提供诸如增强的载流子迁移率和改善的器件性能的优势。外延源极/漏极端子可以通过在衬底上外延沉积晶体材料来形成。随着半导体工业持续按比例缩小半导体器件的尺寸，电路的复杂性在所有器件级别上已经增加。例如，在超出5nm技术节点或3nm技术节点，增加的源极/漏极隧穿会增加泄漏电流。短沟道效应也会是器件故障的原因之一。实施诸如纳米线的纳米结构的半导体器件，是克服短沟道效应的潜在候选者。其中，GAA晶体管器件可以降低短沟道效应并增强载流子迁移率，这反过来改善器件性能。然而，在用于形成源极/漏极端子的GAA器件的高纵横比开口中设置外延材料，而在沉积的材料中不形成缺陷已经变得越来越具有挑战性。源极/漏极结构中形成的诸如孔洞、聚集的缺陷会影响器件性能并降低器件良率。
本发明中的各个实施例描述了用于形成无孔洞的外延源极/漏极结构的方法。例如，多步骤外延源极/漏极形成工艺可以用于形成用于GAAFET的源极/漏极结构。在一些实施例中，GAAFET可以实施纳米线或纳米片结构，并且在相邻的纳米线或纳米片之间形成间隔件。为了降低缺陷并防止短沟道效应，多步骤外延源极/漏极形成工艺可以包括在纳米线或纳米片的端部周围形成外延端帽。将额外的外延材料设置在外延端帽和间隔件上，直到形成源极/漏极结构的主要部分。可以在额外的外延材料的顶面上形成外延帽层，用以降低源极/漏极结构与随后形成的源极/漏极接触件之间的接触电阻。本文所描述的多步骤外延源极/漏极结构提供了可以改善器件性能、可靠性和良率的各个优势。优势可以包括但不限于降低短沟道效应、降低孔洞以及降低缺陷、此外还有其它的优势。本文描述的实施例使用GAAFET作为实例，并且可以应用于其他半导体结构，诸如finFET和平面FET。另外，本文描述的实施例可以用于各个技术节点，诸如14nm、7nm、5nm、3nm、2nm以及更低的技术节点。
图1是根据一些实施例的用于制造包含多层外延源极/漏极结构的半导体器件的方法100的流程图。为了示出的目的，将参考如图2A至2C、3A、3B、和图4至图12所示出的制造半导体器件200的示例性制造工艺来描述图1所示出的操作。根据特定的应用，可以以不同的顺序执行或不执行操作。应当理解，方法100可能不会产生完成的半导体器件。相应的，应当理解，可以在方法100之前、期间和之后提供附加的工艺，并且本文仅简要描述一些其他工艺。
参考图1，在操作105中，根据一些实施例，在衬底的鳍结构上形成半导体层。例如，可以在衬底106上形成具有鳍基部108A和鳍顶部108B的鳍结构108，如参考图2A至图2C所示出的半导体器件200所描述的。图2B是从A-A线观察的图2A中的结构的截面图。图2C是从B-B线观察的图2A中的结构的截面图。形成鳍结构108可以包括如图2A至图2C所示的在衬底106上形成鳍基部108A和鳍顶部108B。
衬底106可以是半导体材料，诸如硅。在一些实施例中，衬底106包括晶体硅衬底(例如，晶圆)。在一些实施例中，衬底106包括(i)诸如锗的基本半导体；(ii)包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；(iii)包括碳化硅锗、硅锗、磷化砷化镓、磷化镓铟、砷化镓铟、磷化镓铟砷、砷化铝铟和/或砷化铝镓的合金半导体；或(iv)其组合。此外，取决于设计要求(例如，p型衬底或n型衬底)来掺杂衬底106。在一些实施例中，衬底106可以掺杂有p型掺杂剂(例如，硼、铟、铝或镓)或n型掺杂剂(例如，磷或砷)。
鳍结构108沿着x轴延伸。鳍结构108可以是衬底的部分，并且包括鳍基部108A和设置在鳍基部108A上的鳍顶部108B。在一些实施例中，鳍片基部108A可以包括与衬底106相似的材料。鳍基部108A可以由衬底106的光刻图案化和蚀刻形成。在一些实施例中，鳍顶部108B可以包括半导体层的堆叠件。可以随后处理每个半导体层以形成在finFET的随后形成的栅极结构下面的沟道区。鳍顶部108B可以包括以交替配置堆叠的第一组半导体层122和第二组半导体层124。半导体层122和124的每个可以在其下面的层上外延生长，并且可以包括彼此不同的半导体材料。在一些实施例中，半导体层122和124可以包括与衬底106相似或不同的半导体材料。在一些实施例中，半导体层122和124可以包括氧化率和/或蚀刻选择性彼此不同的半导体材料。在一些实施例中，每个半导体层122可以由硅形成，并且每个半导体层124可以由硅锗(SiGe)形成。在一些实施例中，半导体层122可以由硅锗形成，并且半导体层124可以由硅形成。半导体层122和/或半导体层124可以是未掺杂的，或者可以在它们外延生长工艺期间使用(i)诸如硼、铟和镓的p型掺杂剂和/或(ii)诸如磷和砷n型掺杂剂，来原位掺杂。对于p型原位掺杂，可以使用p型掺杂前体，诸如乙硼烷(B2H6)、三氟化硼(BF3)和任何其他p型掺杂前体。对于n型原位掺杂，可以使用n型掺杂前体，诸如磷化氢(PH3)、砷化氢(AsH3)和任何其他n型掺杂前体。尽管在图2A至图2C中示出了用于半导体层122和半导体层124的每个的四层，半导体器件200可以具有任何合适数量的半导体层122和半导体层124。
形成鳍基部108A和鳍顶部108B可以包括在衬底106上形成用于半导体层122和124的材料的堆叠件，并且通过形成在材料的堆叠件上的图案化的硬掩模层134和136蚀刻衬底106和材料的堆叠件的部分。在一些实施例中，硬掩模层134可以是包括使用例如热氧化工艺形成的氧化硅的薄膜。在一些实施例中，硬掩模层136可以由使用例如LPCVD或PECVD的氮化硅形成。材料的堆叠件的蚀刻可以包括干蚀刻、湿蚀刻工艺或其组合。可以在形成鳍结构108之后去除硬掩模层134和136。
参考图1，在操作110中，根据一些实施例，在衬底上形成牺牲栅极结构，并且蚀刻半导体层。参考图3A和图3B，可以在衬底106上形成具有第一和第二保护衬垫138A至138B以及绝缘层138C的STI区域138。图3B是从图3A的线C-C观察的半导体器件200的截面图。在一些实施例中，在形成STI区域138之后，硬掩模层136保留在硬掩模134的顶面上。在一些实施例中，在形成STI区域138之前去除硬掩模层136。形成STI区域138可以包括：(i)在图2A的结构上沉积用于第一保护衬垫138A的氮化物材料层(未示出)，(ii)在氮化物材料层上沉积用于第二保护衬垫138B的氧化物材料层(未示出)，(iii)在氧化物材料层上沉积用于绝缘层138C的绝缘材料层，(iv)退火用于绝缘层138C的绝缘材料层，(v)化学机械抛光(CMP)氮化物和氧化物材料层以及退火的绝缘材料层，以及(vi)回蚀刻抛光的结构以形成图3A的结构。可以使用诸如ALD和CVD的用于沉积氧化物和氮化物材料的合适的工艺来沉积氮化物和氧化物材料层。这些氧化物和氮化物材料层可以防止在用于绝缘层138C的绝缘材料的沉积和退火期间鳍顶部108B的侧壁的氧化。在一些实施例中，用于绝缘层138C的绝缘材料层可以包括氧化硅、氮化硅，氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)或低k介电材料。在一些实施例中，可以使用CVD工艺、高密度等离子体(HDP)CVD工艺、使用硅烷(SiH4)和氧气(O2)作为反应前体来沉积绝缘材料层。在一些实施例中，可以使用次常压CVD(SACVD)工艺或高纵横比工艺(HARP)来形成绝缘材料层，其中工艺气体可以包括正硅酸乙酯(TEOS)和/或臭氧(O3)。
如图3A和图3B所示，在STI区域138上形成多晶硅栅极结构112。多晶硅栅极结构112是牺牲栅极结构，并且可以在栅极替换工艺中被替换以形成金属栅极结构。在一些实施例中，多晶硅栅极结构112的形成可以包括毯式沉积多晶硅材料层并且通过形成在多晶硅材料层上的图案化的硬掩模层116蚀刻多晶硅材料层。在一些实施例中，可以不掺杂多晶硅材料层，并且硬掩模层116可以包括氧化物层和/或氮化物层。可以使用热氧化工艺来形成氧化物层，并且可以通过LPCVD或PECVD来形成氮化物层。硬掩模层116可以保护多晶硅栅极结构112免于随后的处理步骤(例如，在形成间隔件114、源极/漏极区和/或ILD层期间)。多晶硅材料层的毯式沉积可以包括CVD、PVD、ALD或任何其他合适的沉积工艺。在一些实施例中，多晶硅材料的沉积层的蚀刻可以包括干蚀刻、湿蚀刻或其组合。间隔件114可以形成在多晶硅栅极结构112的侧壁上。形成间隔件114可以包括毯式沉积绝缘材料层(例如，氧化物、氮化物和/或碳氮氧化硅材料)，接着进行光刻和蚀刻工艺(例如，反应离子蚀刻或使用氯或氟基蚀刻剂的任何其他合适的干蚀刻工艺)。
可以在形成多晶硅栅极结构112之后蚀刻鳍顶部。蚀刻工艺可以去除暴露在相邻的多晶硅栅极结构112之间的半导体层122和半导体层124的部分。蚀刻工艺可以包括使用例如稀HF的湿蚀刻工艺。在一些实施例中，可以使用一种或多种蚀刻工艺。例如，蚀刻工艺可以包括用于去除硅材料的蚀刻工艺和用于去除硅锗材料的另一蚀刻工艺。在蚀刻工艺期间，可以通过间隔件114和硬掩模层116保护多晶硅栅极结构112免于蚀刻。
参考图1，在操作115中，根据一些实施例，可以在衬底中并且在多晶硅栅极结构之间的形成凹槽。参考图4，可以在衬底106中并且在相邻的多晶硅栅极结构112之间形成凹槽402(例如，凹穴)。可以使用各向异性蚀刻工艺404以在垂直方向(例如，沿着z轴)上的蚀刻速率基本上大于在水平方向(例如，沿x轴)上的蚀刻速率来形成凹槽402。例如，可以使用等离子体蚀刻工艺，该等离子体蚀刻工艺使用氟和/或氯蚀刻剂。在一些实施例中，等离子体蚀刻工艺可以使用六氟化硫、四氟化碳、氟仿、三氯化硼、溴化氢、任何合适的蚀刻剂和/或其组合。在一些实施例中，可以将偏压施加至衬底106以增加在垂直方向上的蚀刻速率。在一些实施例中，可以在蚀刻半导体层122和半导体层124的操作110期间形成凹槽402。例如，蚀刻半导体层122和124可以包括交替的蚀刻工艺循环，并且蚀刻工艺404可以使用与用于蚀刻半导体层122的等离子体蚀刻工艺类似的等离子体种类。在一些实施例中，凹槽402可以具有带有倾斜侧壁的凹形(例如，基本上U形的结构)，这可以通过消除尖角来降低随后形成的源极/漏极区中的孔洞。为了简单起见，尽管在图4中示出了具有U形截面的凹槽402，凹槽402可以具有在图4中未示出的任何其他合适的形状。例如，凹槽402可以具有基本上V形的截面面积。在一些实施例中，凹槽402可以具有基本上垂直的侧壁。
参考图1，在操作120中，根据一些实施例，在半导体层之间形成内部间隔件结构。参考图5，可以回蚀刻半导体层124的部分以形成凹进区域，并且可以在凹进区域中沉积电介质材料以形成内部间隔件127。例如，图5中所示的半导体器件200可以包括n型金属氧化物半导体(NMOS)器件以及回蚀刻半导体层124的部分。
半导体器件200还可以包括p型金属氧化物半导体(PMOS)器件。为了简单起见，图5中没有示出PMOS器件配置。对于PMOS器件配置，可以处理半导体层124以用作沟道区。可以使用合适的蚀刻工艺来回蚀刻半导体层122，并且可以使用与下面描述的类似的沉积和蚀刻工艺在相邻的半导体层124之间形成内部间隔件127。
可以通过干蚀刻工艺、湿蚀刻工艺或其组合来回蚀刻半导体层124。可以将半导体层124的回蚀刻工艺配置为形成半导体层122和124的非平坦外表面。例如，蚀刻工艺可以包括交替的蚀刻和净化工艺循环。在每个循环中的蚀刻工艺可以包括使用具有氟化氢(HF)、三氟化氮(NF3)、氟基气体和氯基气体的气体混合物。如图5的放大图501所示，半导体层122可以具有弯曲的凸外表面122t，并且半导体层124可以具有弯曲的凹外表面124t。在一些实施例中，随后形成的内部间隔件127也可以具有外表面127t，该外表面127t基本上轮廓化半导体层124的外表面124t。内部间隔件127和半导体层122的非平坦(例如，弯曲的)外表面可以通过去除倾向于形成孔洞的尖角来降低在随后形成的源极/漏极结构中的孔洞。
在形成凹槽区域的工艺之后，可以接着介电材料层的毯式沉积，以及毯式沉积的介电材料层的水平蚀刻，以在半导体层124的凹外表面124t上和半导体层122的顶/底面上形成内部间隔件127。在一些实施例中，毯式沉积工艺可以包括多个沉积和蚀刻工艺循环。在每个循环中，蚀刻工艺可以在沉积工艺之后进行以防止在内部间隔件127内形成孔洞。内部间隔件结构127可以包括通过ALD、FCVD或任何其他合适的沉积来沉积介电层的单层或堆叠件。介电材料层的毯式沉积工艺的每个循环中的蚀刻工艺可以包括使用HF和NH3的气体混合物的干蚀刻工艺。内部间隔件结构127可以包括合适的介电材料，诸如硅、氧、碳或氮。可以通过使用HF和NH3的气体混合物的干蚀刻工艺来执行形成内部间隔件127的毯式沉积的介电材料层的水平蚀刻工艺。可以使用用于形成内部间隔件结构127的其他沉积方法和水平蚀刻工艺。
参考图1，在操作125中，根据一些实施例，可以在衬底，内部间隔件和半导体层的暴露表面上设置第一外延层。参考图6，可以在图5中示出的凹槽402中以及半导体层122和内部间隔件127的外表面沉积第一外延层602。在一些实施例中，第一外延层602可以通过选择性生长形成，其中，在选择性表面上生长半导体材料。例如，在NMOS器件中，可以通过使用衬底106和半导体层122的暴露部分作为晶种层外延生长晶体材料来形成第一外延层602。在一些实施例中，衬底106和半导体层122由晶体硅形成，并且可以使用使用自组装单层(SAM)或选择性区域ALD的外延沉积方法以在衬底106和半导体层122的暴露表面上选择性地生长晶体硅。在相邻半导体层122和衬底106上外延沉积的晶体硅材料可以扩展并合并在一起，覆盖内部间隔件127的外表面。对于PMOS器件，可以通过使用衬底106和半导体层124的暴露部分作为晶种层外延生长晶体材料来形成第一外延层602。例如，可以使用晶体硅锗来形成第一外延层602。
在沉积工艺之后，可以形成第一外延层602的连续层。在一些实施例中，第一外延层602可以具有不均匀的厚度。例如，形成在半导体层122的外表面上的第一外延层602可以具有比形成在内部间隔件127的外表面上的第一外延层602更大的厚度。在一些实施例中，形成在内部间隔件127的外表面上的第一外延层602可以具有介于约20nm与约50nm之间的厚度、介于约30nm与约40nm之间的厚度、介于约33nm与约37nm之间的厚度、或任何合适的厚度。在一些实施例中，形成在凹槽402中的第一外延层602可以具有介于约20nm与约100nm之间的厚度、介于约30nm与约80nm之间的厚度、介于约40nm与约60nm之间的厚度、或任何合适的厚度。
第一外延层602可以由硅、硅锗、磷化硅、任何合适的半导体材料和/或它们的组合形成。在一些实施例中，第一外延层602可以掺杂有合适的掺杂剂，诸如硼和磷。
对于NMOS器件配置，可以使用类似的材料形成半导体层122和第一外延层602。例如，包含由硅形成的半导体层122的NMOS器件可以实施由硅形成的第一外延层602。第一外延层602可以掺杂有合适的掺杂剂。例如，第一外延层602可以掺杂有n型掺杂剂，诸如磷。在一些实施例中，第一外延层602可以掺杂有原子浓度介于约0.5×1020at/cm3与约8×1020at/cm3之间，介于约0.7×1020at/cm3与约6×1020at/cm3之间、介于约1×1020at/cm3与约5×1020at/cm3之间、或任何合适的范围的磷或砷。
对于PMOS器件配置，可以使用类似的材料形成半导体层124和第一外延层602。例如，包含由硅锗形成的半导体层124的PMOS器件可以实施由硅锗形成的第一外延层602。在一些实施例中，半导体层124和第一外延层602的锗原子含量比可以在彼此的约±10％内。例如，半导体层124可以具有约25％的锗原子含量比，并且第一外延层602可以具有介于约22％与约28％之间，诸如约25％的锗原子含量比。在一些实施例中，第一外延层602中的锗原子含量可以大于半导体层124中的锗原子含量。在一些实施例中，第一外延层602可以掺杂有合适的掺杂剂。例如，PMOS器件配置中的第一外延层602可以掺杂有p型掺杂剂，诸如硼。例如，PMOS器件中的第一外延层602可以掺杂有原子浓度介于约0.5×1020at/cm3与约8×1020at/cm3之间，介于约0.7×1020at/cm3与约6×1020at/cm3之间、介于约1×1020at/cm3与约5×1020at/cm3之间、或任何合适的范围的硼。
在一些实施例中，可以使用离子注入装置来执行第一外延层602的注入工艺。在注入工艺期间，间隔件114和硬掩模层116可以作为掩模层，以保护下面的半导体层122和124免于损坏或污染。在一些实施例中，调整离子注入能量，从而使得可以将掺杂剂基本上注入至第一外延层602中。在一些实施例中，可以在基本上垂直的方向(例如，z方向)上施加离子。结果，形成在凹槽402中的第一外延层602中的掺杂剂浓度可以具有不均匀的掺杂剂浓度，并且掺杂剂浓度从顶面602t至底面602b减小。
可以使用合适的沉积方法来沉积第一外延层602，诸如(i)化学气相沉积(CVD)、包括但不限于低压CVD(LPCVD)、原子层CVD(ALCVD)、超高真空CVD(UHVCVD)、减压CVD(RPCVD)和任何其他合适的CVD；(ii)分子束外延(MBE)工艺；(iii)任何合适的外延工艺；或(iv)其组合。在一些实施例中，可以通过外延沉积/部分蚀刻工艺来生长第一外延层602，该外延沉积/部分蚀刻工艺至少重复一次外延沉积/部分蚀刻工艺。这种重复的沉积/部分蚀刻工艺也称为循环沉积蚀刻(CDE)工艺。在一些实施例中，使用诸如锗烷、二氯硅烷(dichlorosilane)和盐酸盐的种类的等离子体沉积工艺可以用于沉积由硅锗形成的第一外延层602。在一些实施例中，使用磷烷的等离子体沉积工艺可以用于沉积由磷化硅形成的第一外延层。
在一些实施例中，由于表面的表面晶体取向的差异，第一外延层602的沉积工艺在凹槽402中的沉积速率可以比在半导体层122的暴露表面上的沉积速率更大。例如，使用上述种类(例如锗烷、二氯硅烷和盐酸盐)的等离子体沉积工艺可以比具有(110)或(111)晶向(例如，半导体层122的外表面122t)的表面更大的速率在具有(100)晶向的表面(例如，凹槽402中的表面)上沉积晶体材料。沉积的第一外延层602可以具有与其沉积在其上的材料相同的晶体取向。在一些实施例中，凹槽402中的沉积速率与半导体层122的外表面上的沉积速率之比可以介于约2:1与约7:1之间，介于约3:1与约5:1之间或任何合适的比。使用大于或小于上述范围的沉积速率比值可能在沉积的外延材料中引起孔洞和/或在半导体层122和内部间隔件127上引起的膜覆盖不足。
参考图1，根据一些实施例，在操作130中，回蚀刻第一外延层以暴露内部间隔件结构的外表面的部分。参考图7，可以回蚀刻第一外延层602以暴露下面的内部间隔件127的部分。回蚀刻工艺还可以去除沉积在凹槽402中的第一外延层602的部分。第一外延层602的剩余部分可以形成位于半导体层122的端部上的外延端帽702和位于凹槽中的外延基底704。由于半导体层122的非平坦外表面，外延端帽702可以具有非平坦内表面和外表面。在一些实施例中，外延端帽702可以具有基本上月牙形形状，如图7的放大图701所示。具体地，外延端帽702的内表面和外表面均可以具有弯曲的表面，并且端部分别彼此连接。在一些实施例中，外延端帽702可以使用其他合适的形状形成。外延端帽702可以与内部间隔件127的外表面直接接触。将外延端帽702并入半导体层122上可以降低可能形成在半导体层122的端部上的缺陷(例如，孔洞)，并且还降低短沟道效应。可以在凹槽402中并且在衬底106上形成外延基底704。在一些实施例中，外延基底704可以与一个或多个内部间隔件127直接接触。
形成外延端帽702和外延基底704的第一外延层602的回蚀刻工艺可以包括各向异性蚀刻工艺。例如，形成在半导体层122和内部间隔件127上的第一外延层602的蚀刻速率可以大于形成在凹槽402中的第一外延层602的蚀刻速率。在一些实施例中，蚀刻速率的差异可以归因于晶向差异。例如，与具有(100)晶向(例如，形成在凹槽402中的表面上的第一外延层602)的表面相比，在具有(110)或(111)晶向(例如，形成在半导体层122上方的第一外延层602的侧壁表面)的表面上的蚀刻速率可以更大。各向异性蚀刻工艺可以回蚀刻第一外延层602的侧壁以形成外延端帽702，同时在凹槽402中形成的外延基底704保持与内部间隔件127接触。
参考图1，在操作135中，根据一些实施例，将第二外延层设置在外延端帽、外延基底和内部间隔件上。参考图8，第二外延层806可以是沉积在相邻的多晶硅栅极结构112之间以及在外延端帽702、内部间隔件127和外延基底704的暴露表面上的外延体。第二外延层806可以形成半导体器件200的源极/漏极区的主要部分。在一些实施例中，第二外延层806是与衬底106的材料相同的材料。在一些实施例中，第二外延层806包括与衬底106的材料不同的材料。第二外延层806可以包括：(i)半导体材料，诸如锗和硅；(ii)化合物半导体材料，诸如砷化镓和砷化铝镓；(iii)合金半导体，诸如硅锗和磷化砷化镓。在一些实施例中，可以通过类似于第一外延层602的沉积工艺来生长第二外延层806。在一些实施例中，沉积工艺可以不同。例如，可以使用具有原位注入工艺的等离子体沉积工艺来形成第二外延层806，并且第二外延层806中的掺杂剂浓度可以大于第一外延层602的掺杂剂浓度。在一些实施例中，可以在第二外延层806的沉积工艺期间或之后执行注入工艺。在注入工艺期间，间隔件114和硬掩模层116可以作为掩模层，以保护下面的半导体层122和半导体层124免于损坏或污染。在一些实施例中，调整离子注入能量，从而使得可以将掺杂剂基本上注入至第二外延层806中。在一些实施例中，可以在基本上垂直的方向(例如，z方向)上施加离子。结果，第二外延层806中的掺杂剂浓度可以具有不均匀的掺杂剂浓度，并且掺杂剂浓度从顶面806t至底面806b减小。
在一些实施例中，还可以在间隔件114上沉积第二外延层806。在一些实施例中，第二外延层806可以由硅锗、磷化硅、砷化硅，任何合适的半导体材料和/或其组合形成。在一些实施例中，可以使用与第一外延材料602类似的材料来形成第二外延层806。例如，PMOS器件可以包括由硅锗形成的第二外延层806。在一些实施例中，NMOS器件可以包括由磷化硅形成的第二外延层806。在一些实施例中，第二外延层806可以使用与第一外延材料602不同的材料形成。在一些实施例中，第二外延层806的掺杂剂浓度可以是不均匀的。例如，由硅锗形成的第二外延层806可以具有从第二外延层806的顶面向外延基底704逐渐减小的锗浓度。在一些实施例中，第二外延层806中的掺杂剂浓度可以沿着水平方向(例如，沿着x轴)变化。在一些实施例中，可以将任何合适的掺杂剂注入至第二外延层806中。例如，可以将硼注入至硅锗材料中，并且掺杂剂浓度介于约5×1019at/cm3与约2×1021at/cm3之间。在一些实施例中，可以将磷或砷注入至硅材料中以形成磷化硅或砷化硅，其中，磷或砷的掺杂剂浓度可以介于约5×1019at/cm3与约2×1021at/cm3之间。
可以使用合适的沉积方法来沉积第二外延层806。例如，可以使用与形成第一外延层602类似的方法来沉积第二外延层806。例如，使用诸如锗烷、二氯硅烷和盐酸盐的种类的等离子体沉积工艺可以用于沉积由硅锗形成的第二外延层806。在一些实施例中，使用磷或砷的等离子体沉积工艺可以用于分别沉积由磷化硅或砷化硅形成的第二外延层806。第二外延层806的沉积工艺可以持续至填充位于相对的内部间隔件127和外延端帽702之间的开口。在一些实施例中，第二外延层806的顶面与间隔件114接触并且在最上面的半导体层122的顶面之上。可以使用可选的蚀刻工艺以回蚀刻第二外延层806以防止掺杂剂从第二外延层806扩散至随后形成的替换多晶硅栅极结构112的金属栅极结构中。在一些实施例中，蚀刻工艺可以使用氯化物基的蚀刻剂，诸如盐酸盐。在一些实施例中，蚀刻工艺可以回蚀刻第二外延层806，使得第二外延层806不与间隔件114接触。在一些实施例中，执行蚀刻工艺以降低第二外延层806和间隔件114之间的接触表面区域。例如，顶面806t可以是非平面表面，该非平坦表面具有与低于顶面806t的最高点的间隔件114接触的端部。在一些实施例中，位于相对的半导体层122之间的第二外延层的宽度W可以在约10nm与约80nm之间、在约15nm与约75nm之间，在约20nm与约60nm之间或任何合适的尺寸。在一些实施例中，从第二外延层806的顶面806t和底面806b测量的第二外延层806的高度H可以在约20nm与约140nm之间、在约30nm与约120nm之间、在约40nm与约100nm之间、或任何合适的尺寸。
参考图1，在操作140中，根据一些实施例，在第二外延层上形成第三外延层。参考图9，第三外延层902可以是形成在第二外延层806上并且位于相邻的多晶硅栅极结构112之间的顶帽。在一些实施例中，第三外延层902可以使用硅、硅锗、磷化硅、任何合适的半导体材料和/或其组合形成。在一些实施例中，第三外延层902可以掺杂有合适的掺杂剂，诸如硼。在一些实施例中，第三外延层902的掺杂剂浓度可以与第二外延层806的掺杂剂浓度不同。第三外延层902中的硼或磷的掺杂剂浓度可以大于第二外延层806的掺杂剂浓度。在一些实施例中，第三外延层902的硼或磷的掺杂剂浓度可以在约0.5×1021at/cm3与约5×1021at/cm3之间、在约0.8×1021at/cm3与约4×1021at/cm3之间、在约1×1021at/cm3与约3×1021at/cm3、或任何合适的范围。具有比第二外延层806更高的掺杂剂浓度的第三外延层902可以提供降低与随后形成的源极/漏极接触结构的接触电阻的优势。在一些实施例中，可以使用与形成第一外延层602和第二外延层806的方法类似的等离子体沉积方法来形成第三外延层902。例如，可以使用等离子体沉积工艺和/或选择性外延沉积工艺来形成第三外延层902。第三外延层的厚度T可以在约3nm与约40nm之间、在约5nm与约35nm之间、在约10nm与约30nm之间、或任何合适的厚度。在一些实施例中，第三外延层902的宽度可以类似于第二外延层806的宽度。例如，第三外延层902的宽度可以类似于宽度W并且在约20nm与约60nm之间。根据一些实施例，半导体器件200的源极/漏极区可以包括外延端帽702、外延基底704、第二外延层806和第三外延层902。
根据一些实施例，图10包括图9中示出的区域901的放大图的图示以及在沉积的外延层的各个区域中的掺杂剂分布的示意图。图10中的示意图示出了沿着放大图901中示出的半导体器件200的DD、EE和FF线的第一、第二和第三外延层中的锗浓度和硼掺杂剂浓度变化。如图10所示，水平DD线与半导体层122、外延端帽702和第二外延层806相交。根据一些实施例，如沿着水平线DD的锗浓度和硼掺杂剂浓度图所示，第二外延层806中的浓度可以是最高的，并且在外延端帽702中逐渐减小，并且在半导体层122中进一步逐渐减小。外延端帽702可以通过作为扩散屏障来降低短沟道效应。例如，通过具有低于第二外延层806的掺杂剂浓度，外延端帽702可以防止掺杂剂在半导体层122和第二外延层806之间扩散。水平EE线与半导体层124，内部间隔件127和第二外延层806相交。根据一些实施例，如沿着水平线EE的锗和硼掺杂剂浓度图中所示，第二外延层806中的掺杂剂浓度可以大于半导体层124和内部间隔件127中的掺杂剂浓度。垂直线FF与第三外延层902、第二外延层802和外延基底704相交。根据一些实施例，如沿着垂直线FF的锗掺杂剂浓度图中所示，第三外延层902中的掺杂剂浓度可以是最高的，并且在第二外延层806中逐渐减小，并且在外延基底704中进一步减小。例如，第二外延层806的锗原子比可以在其顶面806t处的从约50％和约60％降低至在其底面806b处的约20％和约30％。如沿着垂直线F-F的硼掺杂剂浓度图中所示，第三外延层902和第二外延层806的掺杂剂浓度可以是基本上相同的。在一些实施例中，第三外延层902的掺杂剂浓度可以大于第二外延层806的掺杂剂浓度。在一些实施例中，第三外延层902的锗原子比可以在约30％与约70％之间、在约35％与约65％之间、在约40％与约60％之间、或任何合适的比。根据一些实施例，外延基底704的硼掺杂剂浓度可以低于第二和第三外延层806和902的掺杂剂浓度。
参考图1，根据一些实施例，在操作145中，沉积层间介电(ILD)层并执行替换栅极工艺。参考图11，ILD层1118沉积在间隔件114之间，并且多晶硅栅极结构由金属栅极结构替换。
可以将ILD层1118设置在源极/漏极区的第三外延层902上和间隔件114之间。ILD层1118可以包括使用适合于可流动的介电材料(例如，可流动的氧化硅、可流动的氮化硅、可流动的氮氧化硅、可流动的碳化硅或可流动的碳氧化硅)的沉积方法沉积的介电材料。例如，可以使用可流动的CVD(FCVD)来沉积可流动的氧化硅。在一些实施例中，介电材料是氧化硅。用于ILD层1118的其他材料和形成方法在本发明的范围和精神内。
可以在形成ILD层1118之后，使用干蚀刻工艺(例如，反应离子蚀刻)或湿蚀刻工艺去除多晶硅栅结构112和半导体层124，以暴露半导体层122的部分。暴露的半导体层122可以称为纳米结构(例如，纳米线或纳米片)。对于PMOS器件配置，可以去除半导体层122，暴露出半导体层124的部分，这也可以称为纳米结构。在一些实施例中，在干蚀刻工艺中使用的气体蚀刻剂可以包括氯、氟、溴或其组合。在一些实施例中，可以使用氢氧化铵(NH4OH)、氢氧化钠(NaOH)和/或氢氧化钾(KOH)湿蚀刻以去除多晶硅栅极结构112和半导体层124，或者可以使用干蚀刻，接着湿蚀刻工艺。栅极介电层1112可以形成在半导体层上。如图11所示，可以将栅极介电层1112环绕包裹在暴露的纳米线形状的第二半导体层122上。形成栅极介电层1112可以包括合适的栅极介电材料层的毯式沉积工艺。在一些实施例中，栅极介电层1112可以由高k介电材料(例如，具有介电常数大于约3.9的介电材料)形成。例如，栅极介电层1112可以由氧化铪形成。功函数层1114形成在栅极介电层1112上。在一些实施例中，每个功函数层1114可以包括一个或多个功函数金属层，并且使用相同或不同的材料和/或厚度形成。栅极介电层1112和栅极功函数层1114可以各自环绕包裹在纳米线形状半导体层122。取决于相邻半导体层122之间的间隔，半导体层122可以由栅极介电层1112和功函数层1114环绕包裹，填充相邻半导体层122之间的间隔。在一些实施例中，随后形成的栅电极材料还可以形成在相邻半导体层122之间的间隔中，如下所描述的。
根据一些实施例，可以在功函数层上形成栅电极1116。在功函数层1114上形成用于栅电极的导电材料层1116。如放大图1140所示，如果相邻半导体层122之间的间距足以容纳栅电极材料的厚度，则可以在相邻半导体层122之间以及功函数层1114上形成形成栅电极1116，从而使得将相邻半导体层122之间的间隔填充。位于相邻半导体层122之间的栅电极1116和形成在间隔件114之间的栅电极1116彼此电耦合。用于栅电极的导电材料层1116可以包括合适的导电材料，诸如钛、银、铝、钨、铜、钌，钼、氮化钨、钴、镍、碳化钛、碳化钛铝、锰、锆、金属合金及其组合。可以通过ALD、PVD、CVD或任何其他合适的沉积工艺来形成栅电极1116。栅电极1116的沉积可以持续至位于相对的间隔件114之间的开口由栅电极1116填充。化学机械抛光工艺可以去除过过量的栅电极1116，从而使得栅电极1116和ILD层1118的顶面是基本上共面的。在一些实施例中，可以形成其他结构，诸如阻挡层。可以在沉积栅电极1116之前形成一个或多个阻挡层(图11中未示出)，以防止栅电极1116的扩散和氧化。
参考图1，在操作150中，根据一些实施例，形成源极/漏极接触件和栅极接触件。参考图12，形成源极/漏极接触件1204和栅极接触件1206以提供分别至源极/漏极区和栅电极的电连接。具体地，可以使用源极/漏极接触件1204和栅极接触件1206在源极/漏极区与栅电极和外部端子(图12中未示出)之间传输电信号。例如，栅极接触件1206可以电耦合至形成在间隔件114之间以及相邻半导体层122之间的栅电极1116。可以在ILD层1118的顶面上形成额外的ILD层。例如，可以在ILD层1118上形成介电层1218。在一些实施例中，可以使用与ILD层1118类似的材料来形成介电层1218。可以通过在介电层1218、栅电极1116和ILD层1118中形成开口并且在开口中沉积导电材料来形成栅极接触件1206和源极/漏极接触件1204。沉积工艺可以包括在开口内沉积金属层，并且执行退火过程以诱使沉积的金属层的硅化。用于形成源极/漏极接触件1204和栅极接触件1206的导电材料可以包括钛、铝、银、钨、钴、铜、钌、锆、镍、氮化钛、氮化钨、金属合金和/或其组合。沉积工艺可以包括ALD、PVD、CVD、任何合适的沉积工艺和/或其组合。栅极接触件1206和源极/漏极接触件1204可以分别连接至栅电极1116和源极/漏极区的第三外延层902。
平坦化工艺可以平坦化介电层1218、源极/漏极接触件1204和栅极接触件1206的顶面，从而使得顶面是基本上共面的。在一些实施例中，栅极接触件1206可以延伸至栅电极1116中。在一些实施例中，源极/漏极接触件1204可以延伸至源极/漏极区的第三外延区域902中。在一些实施例中，源极/漏极接触件1204可以延伸至第二外延层806中。可以在源极/漏极接触件1204和源极/漏极区的第三外延区域902之间形成硅化物区以减小接触电阻。例如，可以在源极/漏极接触件1204与第三外延区域902之间形成硅化物区1202。在一些实施例中，硅化物区1202可以由硅化钛材料形成。硅化物区1202可以通过在第三外延层902上沉积导电材料层并执行退火工艺来形成硅化物区1202。在一些实施例中，导电材料层可以是形成源极/漏极接触件1204的导电材料。在一些实施例中，导电材料层可以是与第三外延层902化学反应以形成硅化物区1202的金属薄膜。在一些实施例中，硅化物区域1202可以包括硅化钌、硅化镍、硅化钴、硅化钨、硅化钽、硅化铂、硅化铒、硅化钯、任何合适的硅化物材料和/或其组合。
在源极/漏极接触件1204和栅极接触件1206上方形成后段制程(BEOL)互连结构。可以在沉积在介电层1218上的介电层1222中形成BEOL互连结构。可以在介电层1222中形成互连件。在一些实施例中，互连件可以是包括垂直(例如，沿着z轴)延伸的通孔1226和横向(例如，沿着x轴)延伸的导线1228的电连接的网络。互连结构可以提供至源极/漏极接触件1204和栅极接触件1206的电连接。在一些实施例中，可以在介电层1218和1222中形成合适的无源和有源半导体器件，并且为了简单起见，未示出该无源和有源半导体器件。
本发明中的各个实施例描述了用于形成无孔洞的外延源极/漏极结构并防止半导体器件中的短沟道效应的方法。例如，可以在形成源极/漏极结构中使用多步骤外延源极/漏极形成工艺。在一些实施例中，半导体器件可以实施具有在相邻纳米线或纳米片之间形成的间隔件的纳米线或纳米片结构。为了降低缺陷并且防止短沟道效应，多步骤外延源极/漏极形成工艺可以包括在纳米线或纳米片的端部周围形成外延端帽。将额外的外延材料设置在外延端帽和间隔件上，直到形成源极/漏极结构的主要部分。可以在额外的外延材料的顶面上形成外延帽层，用以降低源极/漏极结构与随后形成的源极/漏极接触件之间的接触电阻。本文描述的多步骤外延源极/漏极结构提供了可以改善器件性能、可靠性和良率的各个优势。
在一些实施例中，半导体器件包括位于衬底上的纳米结构和与纳米结构接触的源极/漏极区。源极/漏极区包括外延端帽，其中，每个外延端帽形成在纳米结构的一个纳米结构的端部处。源极/漏极区还包括与外延端帽接触的外延体和形成在外延体上的外延顶帽。半导体器件还包括形成在纳米结构上的栅极结构。
在一些实施例中，半导体器件包括纳米结构，以及纳米结构的一个纳米结构具有非平坦的外表面。半导体器件还包括环绕包裹纳米结构的每个纳米结构的栅极介电层以及设置在栅极介电层上和纳米结构上方的栅电极。半导体器件还包括与纳米结构接触的源极/漏极区。源极/漏极区包括外延端帽，其中，外延端帽形成在纳米结构的端部处并且具有第一掺杂剂浓度。源极/漏极区还包括与外延端帽接触的外延体，并且外延体具有大于第一掺杂剂浓度的第二掺杂剂浓度。
在一些实施例中，方法包括在衬底上形成纳米结构以及形成间隔件，其中，每个间隔件位于纳米结构的纳米结构对之间。方法还包括蚀刻衬底以形成凹槽。方法还包括在纳米结构的侧壁上、间隔件的侧壁上以及在凹槽中沉积第一外延层。方法还包括蚀刻第一外延层以在凹槽中形成外延端帽和外延基底，其中，每个外延端帽形成在纳米结构的侧壁上，并且外延基底与间隔件接触。方法还包括在端帽和外延基底上沉积第二外延层。方法还包括蚀刻第二外延层，并在蚀刻的第二外延层上沉积第三外延层。
本申请的实施例提供一种半导体器件，包括：多个纳米结构，位于衬底上；源极/漏极区，与所述多个纳米结构接触，所述源极/漏极区包括：多个外延端帽，其中，每个外延端帽形成在所述多个纳米结构的一个纳米结构的端部处；外延体，与所述多个外延端帽接触；以及外延顶帽，形成在所述外延体上；以及栅极结构，形成在所述多个纳米结构上。在一些实施例中，多个外延端帽的每个外延端帽包括月牙形截面形状。在一些实施例中，多个纳米结构的每个纳米结构包括非平坦外表面，并且所述多个端帽的每个外延端帽包括与所述非平坦外表面轮廓化的内表面。在一些实施例中，多个内部间隔件的一个内部间隔件形成在所述多个纳米结构的相邻的纳米结构之间。在一些实施例中，多个外延端帽的外延端帽与所述内部间隔件接触。在一些实施例中，还包括形成在所述衬底的凹穴中的外延基底，其中，所述外延基底和所述多个外延端帽使用相同的材料形成。在一些实施例中，外延体包括第一锗原子浓度，并且所述外延基底包括低于所述第一锗原子浓度的第二锗原子浓度。在一些实施例中，外延体包括第一锗原子浓度，并且所述多个外延端帽包括低于所述第一锗原子浓度的第二锗原子浓度。在一些实施例中，外延体包括第一锗原子浓度，并且所述外延顶帽包括大于所述第一锗原子浓度的第二锗原子浓度。在一些实施例中，外延体包括不均匀的锗原子浓度，所述锗原子浓度从所述外延体的顶面至底面减小。
本申请的实施例提供一种半导体器件，包括：多个纳米结构，其中，所述多个纳米结构的一个纳米结构包括非平坦的外表面；栅极介电层，环绕包裹所述多个纳米结构的每个纳米结构；栅电极，设置在所述栅极介电层上和所述多个纳米结构上；源极/漏极区，与所述多个纳米结构接触，所述源极/漏极区包括：多个外延端帽，其中，外延端帽形成在所述纳米结构的端部处并且包括第一掺杂剂浓度；以及外延体，与所述外延端帽接触，并且所述外延体包括大于所述第一掺杂剂浓度的第二掺杂剂浓度。在一些实施例中，还包括形成在所述外延体上的外延顶帽，其中，所述外延顶帽包括大于所述第二掺杂剂浓度的第三掺杂剂浓度。在一些实施例中，外延端帽包括月牙形截面形状。在一些实施例中，还包括多个间隔件，其中，所述多个间隔件的间隔件与所述外延端帽接触并且与所述多个纳米结构的所述一个纳米结构接触。在一些实施例中，间隔件与所述外延体接触。
本申请的实施例提供一种方法，包括：在衬底上形成多个纳米结构；形成多个间隔件，其中，每个间隔件位于所述多个纳米结构的纳米结构对之间；蚀刻所述衬底以形成凹槽；在所述多个纳米结构的侧壁上、所述多个间隔件的侧壁上以及在所述凹槽中沉积第一外延层；蚀刻所述第一外延层以在所述凹槽中形成多个外延端帽和外延基底，其中，每个外延端帽形成在所述多个纳米结构的纳米结构的侧壁上，并且所述外延基底与所述多个间隔件的间隔件接触；在所述多个端帽和所述外延基底上沉积第二外延层；蚀刻所述第二外延层；以及在蚀刻的所述第二外延层上沉积第三外延层。在一些实施例中，蚀刻所述第一外延层包括形成用于每个外延端帽的月牙形截面形状。在一些实施例中，沉积所述第二外延层包括：将掺杂剂注入至所述第二外延层中，并且所述掺杂剂具有大于所述第一外延层的掺杂剂浓度的掺杂剂浓度。在一些实施例中，还包括：蚀刻所述第三外延层；在所述蚀刻的第三外延层上形成硅化物层；以及在所述硅化物层上形成源极/漏极接触件。在一些实施例中，还包括将掺杂剂浓度注入至所述第三外延层中，所述掺杂剂具有大于所述第二外延层的掺杂剂浓度的掺杂剂浓度。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
多个纳米结构，位于衬底上；
源极/漏极区，与所述多个纳米结构接触，所述源极/漏极区包括：
多个外延端帽，其中，每个外延端帽形成在所述多个纳米结构的一个纳米结构的端部处；
外延体，与所述多个外延端帽接触；以及
外延顶帽，形成在所述外延体上；以及
栅极结构，形成在所述多个纳米结构上。
2.根据权利要求1所述的半导体器件，其中，所述多个外延端帽的每个外延端帽包括月牙形截面形状。
3.根据权利要求1所述的半导体器件，其中，所述多个纳米结构的每个纳米结构包括非平坦外表面，并且所述多个端帽的每个外延端帽包括与所述非平坦外表面轮廓化的内表面。
4.根据权利要求1所述的半导体器件，还包括多个内部间隔件，其中，所述多个内部间隔件的一个内部间隔件形成在所述多个纳米结构的相邻的纳米结构之间。
5.根据权利要求4所述的半导体器件，其中，所述多个外延端帽的外延端帽与所述内部间隔件接触。
6.根据权利要求1所述的半导体器件，还包括形成在所述衬底的凹穴中的外延基底，其中，所述外延基底和所述多个外延端帽使用相同的材料形成。
7.根据权利要求6所述的半导体器件，其中，所述外延体包括第一锗原子浓度，并且所述外延基底包括低于所述第一锗原子浓度的第二锗原子浓度。
8.根据权利要求1所述的半导体器件，其中，所述外延体包括第一锗原子浓度，并且所述多个外延端帽包括低于所述第一锗原子浓度的第二锗原子浓度。
9.一种半导体器件，包括：
多个纳米结构，其中，所述多个纳米结构的一个纳米结构包括非平坦的外表面；
栅极介电层，环绕包裹所述多个纳米结构的每个纳米结构；
栅电极，设置在所述栅极介电层上和所述多个纳米结构上；
源极/漏极区，与所述多个纳米结构接触，所述源极/漏极区包括：
多个外延端帽，其中，外延端帽形成在所述纳米结构的端部处并且包括第一掺杂剂浓度；以及
外延体，与所述外延端帽接触，并且所述外延体包括大于所述第一掺杂剂浓度的第二掺杂剂浓度。
10.一种形成半导体器件的方法，包括：
在衬底上形成多个纳米结构；
形成多个间隔件，其中，每个间隔件位于所述多个纳米结构的纳米结构对之间；
蚀刻所述衬底以形成凹槽；
在所述多个纳米结构的侧壁上、所述多个间隔件的侧壁上以及在所述凹槽中沉积第一外延层；
蚀刻所述第一外延层以在所述凹槽中形成多个外延端帽和外延基底，其中，每个外延端帽形成在所述多个纳米结构的纳米结构的侧壁上，并且所述外延基底与所述多个间隔件的间隔件接触；
在所述多个端帽和所述外延基底上沉积第二外延层；
蚀刻所述第二外延层；以及
在蚀刻的所述第二外延层上沉积第三外延层。
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