TWI789735B - 半導體裝置和其形成方法 - Google Patents

半導體裝置和其形成方法 Download PDF

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TWI789735B
TWI789735B TW110112568A TW110112568A TWI789735B TW I789735 B TWI789735 B TW I789735B TW 110112568 A TW110112568 A TW 110112568A TW 110112568 A TW110112568 A TW 110112568A TW I789735 B TWI789735 B TW I789735B
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epitaxial
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nanostructures
epitaxial layer
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TW110112568A
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TW202209497A (zh
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沙哈吉Ｂ 摩爾
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台灣積體電路製造股份有限公司
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Abstract

本公開描述一種半導體裝置和其形成方法。半導體裝置包括在基板上的奈米結構和接觸奈米結構的源極/汲極區域。源極/汲極區域包括磊晶末端帽，其中磊晶末端帽形成在奈米結構中一者的端部。源極/汲極區域亦包括接觸磊晶末端帽的磊晶塊體和形成在磊晶塊體上的磊晶頂部覆蓋層。半導體裝置進一步包括形成在奈米結構上的閘極結構。

Description

半導體裝置和其形成方法
本公開是關於半導體裝置和其形成方法，且特別是關於半導體裝置的磊晶結構。
隨著半導體科技的進展，增加對高儲存能力、快速製程系統、高性能表現和低成本的需求。為了達成這些需求，半導體工業持續縮小半導體裝置和三維電晶體的尺寸，例如閘極全環繞(gate-all-around，GAA)場效應電晶體(field effect transistor，FET)和鰭片場效應電晶體(fin field effect transistor，finFET)。
根據本公開的實施例提供一種半導體裝置，包括在基板上的複數個奈米結構、接觸奈米結構的源極/汲極區域和形成在奈米結構上的閘極結構。源極/汲極區域包括複數個磊晶末端帽、接觸磊晶末端帽的磊晶塊體和形成在磊晶塊體上的磊晶頂部覆蓋層，其中各個磊晶末端帽形成在奈 米結構中一者的端部。
根據本公開的實施例提供一種半導體裝置，包括複數個奈米結構、環繞各個奈米結構的閘極介電層、配置在閘極介電層和奈米結構上的閘極電極、接觸奈米結構的源極/汲極區域，其中奈米結構的一者包括非平坦外側表面。源極/汲極區域包括複數個磊晶末端帽和接觸磊晶末端帽的磊晶塊體，其中磊晶末端帽的一者形成在奈米結構的端部且具有第一摻雜劑濃度，磊晶塊體具有第二摻雜劑濃度大於第一摻雜劑濃度。
根據本公開的實施例提供一種形成半導體裝置的方法，包括形成複數個奈米結構在基板上、形成複數個間隔物且其中各個間隔物形成在成對的奈米結構之間、蝕刻基板以形成凹槽。方法包括沉積第一磊晶層在奈米結構的側壁上、間隔物的側壁上和凹槽中。方法包括蝕刻第一磊晶層以形成複數個磊晶末端帽和磊晶基部在凹槽中，其中各個磊晶末端帽形成在奈米結構中一者的端部，且磊晶基部接觸間隔物的一者。方法包括沉積第二磊晶層在磊晶末端帽和磊晶基部上、蝕刻第二磊晶層，以及沉積第三磊晶層在經過蝕刻的第二磊晶層上。
100:方法
105,110,115,120,125,130,135,140,145,150:步驟
106:基板
108:鰭片結構
108A:鰭片基部
108B:鰭片頂部
112:多晶矽閘極結構
114:間隔物
116:硬遮罩層
122,124:半導體層
122t,124t:外側表面
127:內側間隔物
127t:外側表面
134,136:硬遮罩層
138:淺溝槽隔離區域
138A:第一保護內襯層
138B:第二保護內襯層
138C:絕緣層
200:半導體裝置
402:凹槽
404:蝕刻製程
501:放大圖
602:第一磊晶層
602b:底表面
602t:頂表面
701:放大圖
702:磊晶末端帽
704:磊晶基部
806:第二磊晶層
806b:底表面
806t:頂表面
901:放大圖
902:第三磊晶層
1112:閘極介電層
1114:功函數層
1116:閘極電極
1118:層間介電層
1140:放大圖
1202:矽化物區域
1204:源極/汲極接觸
1206:閘極接觸
1218,1222:介電層
1226:通孔
1228:導線
A-A,B-B,C-C,D-D,E-E,F-F:截線
H:高度
T:厚度
W1,W2:寬度
x,y,z:軸
當結合附圖閱讀時，從以下詳細描述中可以最好地理解本公開的各方面。應注意，根據工業中的標準方法，各種特徵未按比例繪製。實際上，為了清楚地討論，可任 意增加或減少各種特徵的尺寸。
第1圖是根據一些實施例的製造半導體裝置中多層磊晶源極/汲極結構的方法流程圖。
第2A圖至第2C圖、第3A圖、第3B圖和第4圖至第9圖根據一些實施例繪示在製造製程多個階段的半導體裝置的多個截面圖。
第10圖根據一些實施例繪示部分半導體裝置的放大圖和摻雜劑濃度分佈的示意圖。
第11圖和第12圖根據一些實施例繪示在製造製程多個階段的具有多層磊晶源極/汲極結構的半導體裝置的多個截面圖。
為了實現提及主題的不同特徵，以下公開內容提供了許多不同的實施例或示例。以下描述組件、配置等的具體示例以簡化本公開。當然，這些僅僅是示例，而不是限制性的。例如，在以下的描述中，在第二特徵之上或上方形成第一特徵可以包括第一特徵和第二特徵以直接接觸形成的實施例，並且還可以包括在第一特徵和第二特徵之間形成附加特徵，使得第一特徵和第二特徵可以不直接接觸的實施例。另外，本公開可以在各種示例中重複參考數字和/或字母。此重複是為了簡單和清楚的目的，並且本身並不表示所討論的各種實施例和/或配置之間的關係。
此外，本文可以使用空間相對術語，諸如「在…下 面」、「在…下方」、「下部」、「在…上面」、「上部」等，以便於描述一個元件或特徵與如圖所示的另一個元件或特徵的關係。除了圖中所示的取向之外，空間相對術語旨在包括使用或操作中的裝置的不同取向。裝置可以以其他方式定向(旋轉90度或在其他方向上)，並且同樣可以相應地解釋在此使用的空間相對描述符號。
本文使用的縮寫「FET」代表場效應電晶體。FET的示例之一是金屬氧化物半導體場效應電晶體(metal oxide semiconductor FET，MOSFET)。MOSFET可例如是建於基板的平坦表面內和其上的平面結構(例如半導體晶圓)或是垂直結構。
術語「FinFET」代表形成在鰭片上方的FET，其中鰭片垂直於晶圓的平坦表面。
「S/D」代表形成FET的兩端部的源極及/或汲極接面。
本文使用的術語「垂直」表示標稱垂直於基板的表面。
本文使用的術語「標稱(nominal)」代表在產品或製程的設計階段期間，組成或製程操作的特徵或變數的要求數值或目標數值，以及高於及/或低於要求數值的數值範圍。製造製程的些微變化或公差通常影響數值的範圍。
本文使用的術語「約」和「實質上」表示給定的數值可基於半導體裝置相關的特定技術節點而變化。在一些實施例中，基於特定技術節點，術語「約」和「實質上」 可以表示給定數值在範圍內變化，例如數值的5%(例如數值的±1%、±2%、±3%、±4%、±5%)、數值的10%、數值的20%等。
術語「垂直方向」和「水平方向」分別本文圖式繪示的代表z軸方向和x軸方向。
本公開提供示例的場效應電晶體裝置(例如閘極全環繞(gate-all-around，GAA)FET、鰭式FET(finFET)、水平或垂直GAA finFET或平面FET)半導體裝置中及/或積體電路(integrated circuit，IC)中以及製造相同裝置的示例方法。
在半導體裝置中實現磊晶生長材料以增加裝置速度和減少裝置能量消耗。例如，電晶體裝置中由摻雜的磊晶材料形成的源極/汲極端部可以提供益處，例如增強載子遷移率和改善裝置表現。可以由磊晶沉積結晶材料在基板上形成磊晶源極/汲極端部。當半導體工業持續縮小半導體裝置的尺寸，增加了所有裝置等級的電路複雜度。例如，在5nm技術節點或3nm技術節點下，增加的源極/汲極穿隧可能增加漏電流。短通道效應也可能是裝置失敗的原因之一。具有奈米結構(例如奈米導線)的半導體裝置是克服短通道效應的可能候選。在這樣的裝置中，GAA電晶體裝置可減少短通道效應和增強載子遷移率，並同時改善裝置表現。然而，在GAA裝置中高縱橫比的開口中沉積磊晶材料以形成源極/汲極端部，並避免在沉積的材料中形成缺陷變成更難的挑戰。缺陷(例如形成在源極/汲極結構中的 孔洞(void)和群聚(clustering))可能影響裝置表現和減少裝置產率。
本公開的多種實施例描述形成無孔洞磊晶源極/汲極結構的方法。例如，多步驟磊晶源極/汲極的形成製程可用以形成GAAFET的源極/汲極結構。在一些實施例中，GAAFET可實現具有間隔物形成在相鄰的奈米導線或奈米片之間的奈米導線或奈米片結構。多步驟磊晶源極/汲極的形成製程可包括形成磊晶末端帽環繞奈米導線或奈米片的末端部分，以減少缺陷和避免短通道效應。額外的磊晶材料配置在磊晶末端帽和間隔物上直到形成源極/汲極結構的塊體。磊晶覆蓋層可形成在額外的磊晶材料的頂表面上，以減少源極/汲極結構和後續形成的源極/汲極接觸之間的接觸電阻。本文描述的多步驟磊晶源極/汲極結構提供可改善裝置表現、可靠性和產率的多種益處。益處可包括但不限於減少的短通道效應、減少的孔洞和減少的缺陷，以及其他益處。本文描述的實施例使用GAAFET做為示例，並可應用至其他半導體結構，例如finFET和平面FET。另外，本文描述的實施例可用在多種技術節點，例如14nm、7nm、5nm、3nm、2nm和更小的技術節點。
根據一些實施例，第1圖是製造結合多層磊晶源極/汲極結構的半導體裝置的方法100流程圖。為了繪示的目的，第1圖中繪示的步驟將參考製造半導體裝置200的製造製程示例描述，如第2A圖至第2C圖、第3A圖、第3B圖和第4圖至第12圖中所繪示。根據特定的應用，可 依照不同的順序執行步驟或不執行步驟。應注意，方法100可不製造完整的半導體裝置。因此，應理解可在方法100之前、期間和之後提供額外的製程，且本文僅簡單描述一些其他的製程。
根據一些實施例，參考第1圖的步驟105中，半導體層形成在基板的鰭片結構上。例如，具有鰭片基部108A和鰭片頂部108B的鰭片結構108可形成在基板106上，如第2A圖至第2C圖中所繪示的半導體裝置200。第2B圖是第2A圖中結構從截線A-A觀察的截面圖。第2C圖是第2A圖中結構從截線B-B觀察的截面圖。鰭片結構108的形成可包括形成鰭片基部108A和鰭片頂部108B在基板106上，如第2A圖至第2C圖中所示。
基板106可以是半導體材料，例如矽。在一些實施例中，基板106包括結晶矽基板(例如晶圓)。在一些實施例中，基板106包括元素半導體(例如鍺)、化合物半導體(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(包括碳化矽鍺、矽鍺、砷磷化鎵、磷化鎵銦、砷化鎵銦、砷磷化鎵銦、砷化鋁銦及/或砷化鋁鎵)或上述的組合。進一步地，基板106可以根據設計需求而是摻雜的(例如p型基板或n型基板)。在一些實施例中，基板106可以由p型摻雜劑(例如硼、銦、鋁或鎵)或n型摻雜劑(例如磷或砷)摻雜。
鰭片結構108沿著x軸延伸。鰭片結構108可以是基板的一部分，並包括鰭片基部108A和設置於鰭片基 部108A上的鰭片頂部108B。在一些實施例中，鰭片基部108A可包括類似於基板106的材料。鰭片基部108A可以由微影圖案化和蝕刻基板106所形成。在一些實施例中，鰭片頂部108B可包括半導體層堆疊。各個半導體層可經過後續的製程以在後續形成finFET的通道區域下方的閘極結構。鰭片頂部108B可包括第一組半導體層122和第二組半導體層124以交替方式堆疊。各個半導體層122和半導體層124可磊晶地生長在其下方層之上，並可包括彼此不同的半導體材料。在一些實施例中，半導體層122和半導體層124可包括類似或不同於基板106的半導體材料。在一些實施例中，半導體層122和半導體層124可包括具有彼此不同氧化速率及/或蝕刻選擇性的半導體材料。在一些實施例中，各個半導體層122可以由矽形成，且各個半導體層124可以由矽鍺(SiGe)形成。在一些實施例中，半導體層122可以由矽鍺形成，且半導體層124可以由矽形成。半導體層122及/或半導體層124可以是未摻雜的，或可以在磊晶生長製程中使用p型摻雜劑(例如硼、銦和鎵)及/或n型摻雜劑(例如磷和砷)原位摻雜。針對p型原位摻雜，可使用p型摻雜前驅物，例如乙硼烷(B2H6)、三氟化硼(BF3)和任何其他p型摻雜前驅物。針對n型原位摻雜，可使用n型摻雜前驅物，例如膦(phospahne)(PH3)、砷化氫(AsH3)和任何其他n型摻雜前驅物。儘管第2A圖至第2C圖中示出四層半導體層122和半導體層124，半導體裝置200可具有任何適合數 量的半導體層122和半導體層124。
形成鰭片基部108A和鰭片頂部108B可包括形成半導體層122和半導體層124的材料堆疊在基板106上，並通過形成在材料堆疊上的圖案化硬遮罩層134和硬遮罩層136蝕刻部分的基板106和材料堆疊。在一些實施例中，硬遮罩層134可以是使用例如熱氧化製程所形成包括氧化矽的薄膜。在一些實施例中，硬遮罩層136可以使用例如低壓化學氣相沉積(low pressure chemical vapor deposition，LPCVD)或電漿增強化學氣相沉積(plasma enhanced CVD，PECVD)並由氮化矽形成。材料堆疊的蝕刻可包括乾式蝕刻、濕式蝕刻製程或上述的組合。形成鰭片結構108後，可移除硬遮罩層134和硬遮罩層136。
根據一些實施例，參考第1圖的步驟110中，犧牲閘極結構形成在基板上，且蝕刻半導體層。參考第3A圖和第3B圖，具有第一保護內襯層138A、第二保護內襯層138B和絕緣層138C的淺溝槽隔離區域138可形成在基板106上。第3B圖是第3A圖中的半導體裝置200從截線C-C觀察的截面圖。在一些實施例中，形成淺溝槽隔離區域138之後，硬遮罩層136保留在硬遮罩層134的頂表面上。在一些實施例中，形成淺溝槽隔離區域138之前，移除硬遮罩層136。形成淺溝槽隔離區域138可包括在第2A圖的結構上沉積第一保護內襯層138A的氮化物材料層(未示出)、在氮化物材料層上沉積第二保護內襯層 138B的氧化物材料層(未示出)、在氧化物材料層上沉積絕緣層138C的絕緣材料層、退火絕緣層138C的絕緣材料層、化學機械研磨(chemical mechanical polishing，CMP)氮化物材料層、氧化物材料層和絕緣材料的退火層，以及回蝕研磨的結構以形成第3A圖的結構。可使用適合的製程沉積氧化物和氮化物材料，以沉積氮化物材料層和氧化物材料層，例如原子層沉積(atomic layer deposition，ALD)和CVD。這些氧化物材料層和氮化物材料層在沉積和退火絕緣層138C的絕緣材料期間可避免鰭片頂部108B的側壁氧化。在一些實施例中，絕緣層138C的絕緣材料層可包括氧化矽、氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃(fluoride-doped silicate glass，FSG)或低介電常數介電材料。在一些實施例中，可使用以矽烷(SiH4)和氧氣(O2)做為反應前驅物的CVD製程、高密度電漿(high-density-plasma，HDP)CVD製程沉積絕緣材料層。在一些實施例中，可使用次壓CVD(sub-atmospheric CVD，SACVD)製程或高縱橫比製程(high aspect-ratio process，HARP)形成絕緣材料層，其中製程氣體可包括四乙氧基矽烷(tetraethoxysilane，TEOS)及/或臭氧(O3)。
多晶矽閘極結構112形成在淺溝槽隔離區域138上，如第3A圖和第3B圖中所示。多晶矽閘極結構112是犧牲閘極結構，並且可在閘極替換製程中進行替換以形成金屬閘極結構。在一些實施例中，多晶矽閘極結構112 的形成可包括毯覆沉積多晶矽材料層，並通過形成在多晶矽材料層上的圖案化硬遮罩層116蝕刻多晶矽材料層。在一些實施例中，多晶矽材料層可以是未摻雜的，且硬遮罩層116可包括氧化物層及/或氮化物層。可使用熱氧化製程形成氧化物層，且可使用LPCVD或PECVD形成氮化物層。硬遮罩層116可在後續的製程步驟(例如，在形成間隔物114、源極/汲極區域及/或層間介電層的期間)保護多晶矽閘極結構112。毯覆沉積多晶矽材料層可包括CVD、物理氣相沉積(physical vapor deposition，PVD)、ALD或任何其他適合的沉積製程。在一些實施例中，沉積的多晶矽材料層的蝕刻可包括乾式蝕刻、濕式蝕刻或上述的組合。間隔物114可形成在多晶矽閘極結構112的側壁上。形成間隔物114可包括毯覆沉積絕緣材料層(例如氧化物、氮化物及/或碳氧氮化矽材料)，並接續微影和蝕刻製程(例如，使用氯或氟為基底的蝕刻劑的反應離子蝕刻或任何其他適合的乾式蝕刻製程)。
形成多晶矽閘極結構112後，可蝕刻鰭片的頂部。蝕刻製程可移除在相鄰的多晶矽閘極結構112之間暴露的部分半導體層122和半導體層124。蝕刻製程可包括使用例如稀釋HF的濕式蝕刻製程。在一些實施例中，可使用一或多個蝕刻製程。例如，蝕刻製程可包括移除矽材料的蝕刻製程和移除矽鍺材料的其他蝕刻製程。在蝕刻製程期間，間隔物114和硬遮罩層116可保護多晶矽閘極結構112避免蝕刻。
根據一些實施例，參考第1圖的步驟115中，可形成凹槽在多晶矽閘極結構之間的基板中。參考第4圖，可形成凹槽402(例如溝道)在基板106中和在相鄰的多晶矽閘極結構112之間。可使用各向異性蝕刻製程404形成凹槽402，各向異性蝕刻製程404具有垂直方向(例如沿著z軸)上的蝕刻速率實質上大於水平方向(例如沿著x軸)上的蝕刻速率。例如，可使用以氟及/或氯為蝕刻劑的電漿蝕刻製程。在一些實施例中，電漿蝕刻製程可使用六氟化硫、四氟化碳、三氟甲烷、三氯化硼、溴化氫、任何適合的蝕刻劑及/或上述的組合。在一些實施例中，可施加電壓差至基板106以增加垂直方向上的蝕刻速率。在一些實施例中，可在蝕刻半導體層122和半導體層124的步驟110期間形成凹槽402。例如，蝕刻半導體層122和半導體層124可包括交替循環的蝕刻製程，且蝕刻製程404可使用和蝕刻半導體層122的電漿蝕刻製程相似的電漿種類。在一些實施例中，凹槽402可具有包括傾斜側壁的凹面形狀(例如，實質上U型結構)，藉由減少尖銳轉角以在後續形成的源極/汲極區域中減少孔洞。儘管為簡單起見，第4圖中所示的凹槽402具有U型截面，凹槽402可具有第4圖中未繪示的任何其他適合的形狀。例如，凹槽402可具有實質上V型截面積。在一些實施例中，凹槽402可具有實質上垂直側壁。
根據一些實施例，參考第1圖的步驟120中，內側間隔物結構形成在半導體層之間。參考第5圖，可回蝕 部分的半導體層124以形成凹陷的區域，且可沉積介電材料在凹陷的區域中以形成內側間隔物127。例如，第5圖中所示的半導體裝置200可包括n型金屬氧化物半導體(n-type metal-oxide-semiconductor，NMOS)裝置和回蝕的部分半導體層124。
半導體裝置200也可包括p型金屬氧化物半導體(p-type metal-oxide-semiconductor，PMOS)裝置。為簡單起見，PMOS裝置的配置未示於第5圖中。針對PMOS裝置的配置，半導體層124可經過製程以做為通道區域。半導體層122可使用適合的蝕刻製程進行回蝕，且可使用類似於下述的沉積和蝕刻製程形成內側間隔物127在相鄰的半導體層124之間。
可使用乾式蝕刻製程、濕式蝕刻製程或上述的組合回蝕半導體層124。可配置半導體層124的回蝕製程以形成半導體層122和半導體層124的非平坦外側表面。例如，蝕刻製程可包括交替循環的蝕刻和清洗製程。各個循環中的蝕刻製程可包括使用具有氟化氫(HF)、三氟化氮(NF3)、氟為基底的氣體和氯為基底的氣體的混合氣體。如第5圖的放大圖501中所示，半導體層122可具有曲形凸面的外側表面122t，且半導體層124可具有曲形凹面的外側表面124t。在一些實施例中，後續形成的內側間隔物127也可具有外側表面127t實質上和半導體層124的外側表面124t的輪廓相符。內側間隔物127和半導體層122的非平坦(例如曲形)外側表面可藉由移除容易產生孔洞的尖 銳轉角，在後續形成的源極/汲極結構中減少孔洞。
形成凹陷區域的製程之後可接續毯覆沉積介電材料層和水平蝕刻毯覆沉積的介電材料層，以形成內側間隔物127在半導體層124的凹形外側表面124t和半導體層122的頂表面、底表面上。在一些實施例中，毯覆沉積製程可包括複數個循環的沉積和蝕刻製程。在各個循環中，蝕刻製程可接續在沉積製程之後以避免內側間隔物127之中孔洞的形成。內側間隔物127可包括藉由ALD、FCVD或任何其他適合的沉積製程所沉積的單層或堆疊介電層。介電材料層的毯覆沉積製程的各個循環中，蝕刻製程可包括使用HF和NH3混合氣體的乾式蝕刻製程。內側間隔物127可包括適合的介電材料，例如矽、氧、碳或氮。可藉由使用HF和NH3混合氣體的乾式蝕刻製程，執行毯覆沉積介電材料層的水平蝕刻製程以形成內側間隔物127。也可使用形成內側間隔物127的沉積和水平蝕刻製程的其他方法。
根據一些實施例，參考第1圖的步驟125中，第一磊晶層可配置在基板、內側間隔物和半導體層的暴露表面上。參考第6圖，第一磊晶層602可沉積在凹槽402(如第5圖所繪示)中以及半導體層122和內側間隔物127的外側表面。在一些實施例中，第一磊晶層602可藉由選擇性生長製程形成，其中半導體材料生長在選擇的表面上。例如，在NMOS裝置中，可使用基板106和半導體層122的暴露部分做為種子層，藉由磊晶生長結晶材料形成第一 磊晶層602。在一些實施例中，基板106和半導體層122由結晶矽所形成，且可使用磊晶沉積方法(使用自組裝單層(self-assembly monolayer，SAM)或選擇區域ALD)以選擇性生長結晶矽在基板106和半導體層122的暴露表面上。磊晶沉積在相鄰的半導體層122和基板106上的結晶矽材料可擴張並合併，覆蓋內側間隔物127的外側表面。針對PMOS裝置，可使用基板106和半導體層124的暴露部分做為種子層，藉由磊晶生長結晶材料形成第一磊晶層602。例如，第一磊晶層602可由結晶矽鍺所形成。
在沉積製程後，可形成第一磊晶層602的連續層。在一些實施例中，第一磊晶層602可具有不均勻厚度。例如，形成在半導體層122的外側表面上的第一磊晶層602可具有厚度大於形成在內側間隔物127的外側表面上的第一磊晶層602。在一些實施例中，形成在內側間隔物127的外側表面上的第一磊晶層602可具有厚度介於約20nm和約50nm之間、介於約30nm和約40nm之間、介於約33nm和約37nm之間或任何適合的厚度。在一些實施例中，形成在凹槽402中的第一磊晶層602可具有厚度介於約20nm和約100nm之間、介於約30nm和約80nm之間、介於約40nm和約60nm之間或任何適合的厚度。
第一磊晶層602可由矽、矽鍺、磷化矽、任何適合的半導體材料及/或上述的組合所形成。在一些實施例中，第一磊晶層602可以由適合的摻雜劑摻雜，例如硼和磷。
針對NMOS裝置配置，可使用相似的材料形成半導體層122和第一磊晶層602。例如，具有矽形成的半導體層122的NMOS裝置可實現矽形成的第一磊晶層602。第一磊晶層602可由適合的摻雜劑摻雜。例如，第一磊晶層602可由n型摻雜劑摻雜，例如磷。在一些實施例中，第一磊晶層602可摻雜磷或砷至原子濃度介於約0.5×1020at/cm3和約8×1020at/cm3之間、介於約0.7×1020at/cm3和約6×1020at/cm3之間、介於約1×1020at/cm3和約5×1020at/cm3之間或任何適合的範圍。
針對PMOS裝置配置，可使用相似的材料形成半導體層124和第一磊晶層602。例如，具有矽鍺形成的半導體層124的PMOS裝置可實現矽鍺形成的第一磊晶層602。在一些實施例中，半導體層124和第一磊晶層602的鍺原子含量比例可在彼此的約±10%之間。例如，半導體層124可具有約25%的鍺原子含量比例，且第一磊晶層602可具有約22%和約28%之間的鍺原子含量比例，例如約25%。在一些實施例中，第一磊晶層602中的鍺原子含量可大於半導體層124中的鍺原子含量。在一些實施例中，第一磊晶層602可由適合的摻雜劑摻雜。例如，PMOS裝置配置中的第一磊晶層602可由p型摻雜劑摻雜，例如硼。例如，PMOS裝置中的第一磊晶層602可摻雜硼至原子濃度介於約0.5×1020at/cm3和約8×1020at/cm3之間、介於約0.7×1020at/cm3和約6×1020at/cm3之間、介於約1×1020at/cm3和約5×1020at/cm3之間 或任何適合的範圍。
在一些實施例中，可使用離子佈植設備執行第一磊晶層602的佈植製程。在佈植製程期間，間隔物114和硬遮罩層116可做為遮罩層保護下方的半導體層122和半導體層124避免損傷或汙染。在一些實施例中，調整離子佈植能量以使得摻雜劑可實質上佈植在第一磊晶層602中。在一些實施例中，可在實質上的垂直方向(例如z軸方向)施加離子。因此，形成在凹槽402中的第一磊晶層602的摻雜劑濃度可具有不均勻的摻雜劑濃度，其中摻雜劑濃度從頂表面602t至底表面602b遞減。
可使用適合的沉積方法沉積第一磊晶層602，例如化學氣相沉積(包括但不限於低壓CVD、原子層CVD、超高真空CVD(ultrahigh vacuum CVD，UHVCVD)、減壓CVD(reduced pressure CVD，RPCVD)和任何其他適合的CVD)、分子束磊晶(molecular beam epitaxy，MBE)製程、任何適合的磊晶製程或上述的組合。在一些實施例中，第一磊晶層602可藉由磊晶沉積和部分蝕刻製程生長，其中磊晶沉積和部分蝕刻製程至少重複一次。這樣重複的沉積和部分蝕刻製程也稱為循環沉積蝕刻(cyclic deposition-etch，CDE)製程。在一些實施例中，可藉由使用例如甲鍺烷(germane)、二氯矽烷和鹽酸鹽之種類的電漿沉積製程，沉積矽鍺形成的第一磊晶層602。在一些實施例中，可藉由使用膦的電漿沉積製程，沉積磷化矽形成的第一磊晶層602。
在一些實施例中，由於表面的表面晶體方位(crystal orientation)差異，第一磊晶層602的沉積製程在凹槽402中可具有沉積速率大於在半導體層122的暴露表面上的沉積速率。例如，使用前述種類(例如甲鍺烷、二氯矽烷和鹽酸鹽)的電漿沉積製程在具有(100)晶體方位的表面(例如在凹槽402中的表面)上可具有結晶材料沉積速率大於在具有(110)或(111)晶體方位的表面(例如半導體層122的外側表面122t)上的沉積速率。沉積的第一磊晶層602和其下方的材料可具有相同的晶體方位。在一些實施例中，在凹槽402中的沉積速率對半導體層122的外側表面上的沉積速率的比例可介於約2：1和約7：1之間介於約3：1和約5：1之間或任何適合的比例。使用沉積速率比例大於或小於前述範圍的數值可造成沉積的磊晶材料中的孔洞及/或造成半導體層122和內側間隔物127上不充足的薄膜覆蓋。
根據一些實施例，參考第1圖的步驟130中，回蝕第一磊晶層以暴露內側間隔物結構的部分外側表面。參考第7圖，可回蝕第一磊晶層602以暴露其下方部分的內側間隔物127。回蝕製程也可移除沉積在凹槽402中部分的第一磊晶層602。第一磊晶層602的保留部分可形成在半導體層122的末端部分上的磊晶末端帽702和凹槽402中的磊晶基部704。由於半導體層122的非平坦外側表面，磊晶末端帽702可具有非平坦內側和外側表面。在一些實施例中，磊晶末端帽702可實質上具有新月型，如第7圖 的放大圖701中所示。具體而言，磊晶末端帽702的內側表面和外側表面兩者可具有端部分別彼此連接的曲形表面。在一些實施例中，可以其他適合的形狀形成磊晶末端帽702。磊晶末端帽702可直接接觸內側間隔物127的外側表面。在半導體層122上加入磊晶末端帽702可減少在半導體層122的末端部分上可能形成的缺陷(例如孔洞)，且亦可減少短通道效應。可在凹槽402中和基板106上形成磊晶基部704。在一些實施例中，磊晶基部704可直接接觸一或多個內側間隔物127。
形成磊晶末端帽702和磊晶基部704的第一磊晶層602的回蝕製程可包括各向異性蝕刻製程。例如，形成在半導體層122和內側間隔物127上的第一磊晶層602的蝕刻速率可大於形成在凹槽402中的第一磊晶層602的蝕刻速率。在一些實施例中，蝕刻速率的差異可源自於晶體方位的差異。例如，在具有(110)或(111)晶體方位表面(例如形成在半導體層122上方的第一磊晶層602的側壁表面)上的蝕刻速率可大於在具有(100)晶體方位表面(例如形成在凹槽402中的第一磊晶層602的表面)上的蝕刻速率表面。各向異性蝕刻製程可回蝕第一磊晶層602的側壁以形成磊晶末端帽702，同時在凹槽402中形成的磊晶基部704保持和內側間隔物127的接觸。
根據一些實施例，參考第1圖的步驟135中，第二磊晶層配置在磊晶末端帽、磊晶基部和內側間隔物上。參考第8圖，第二磊晶層806可以是沉積在相鄰的多晶矽 閘極結構112之間和在磊晶末端帽702、內側間隔物127和磊晶基部704的暴露表面上的磊晶塊體(epitaxial body)。第二磊晶層806可形成半導體裝置200的源極/汲極區域的塊材。在一些實施例中，第二磊晶層806可以和基板106是相同的材料。在一些實施例中，第二磊晶層806包括和基板106不同的材料。第二磊晶層806可包括元素半導體材料(例如鍺和矽)、化合物半導體材料(例如砷化鎵和鋁砷化鎵)或半導體合金(例如矽鍺和磷砷化鎵)。在一些實施例中，第二磊晶層806可藉由類似於第一磊晶層602的沉積製程生長。在一些實施例中，沉積製程可以是不同的。例如，第二磊晶層806的形成可使用具有原位佈植製程的電漿沉積製程，且第二磊晶層806中的摻雜劑濃度可大於第一磊晶層602中的摻雜劑濃度。在一些實施例中，可在第二磊晶層806的沉積製程期間或之後執行佈植製程。在佈植製程期間，間隔物114和硬遮罩層116可做為遮罩層保護其下方的半導體層122和半導體層124避免損傷或汙染。在一些實施例中，調整離子佈植能量以使得摻雜劑可實質上佈植在第二磊晶層806中。在一些實施例中，可在實質上的垂直方向(例如z軸方向)施加離子。因此，第二磊晶層806中的摻雜劑濃度可具有不均勻摻雜劑濃度，其中摻雜劑濃度從頂表面806t至底表面806b遞減。
在一些實施例中，第二磊晶層806也可沉積在間隔物114上。在一些實施例中，第二磊晶層806可以由矽 鍺、磷化矽、砷化矽、任何適合的半導體材料及/或上述的組合所形成。在一些實施例中，第二磊晶層806可使用和第一磊晶層602相似的材料形成。例如，PMOS裝置可包括矽鍺形成的第二磊晶層806。在一些實施例中，NMOS裝置可包括磷化矽形成的第二磊晶層806。在一些實施例中，第二磊晶層806可使用不同於第一磊晶層602的材料形成。在一些實施例中，第二磊晶層806的摻雜劑濃度可以是不均勻的。例如，矽鍺形成的第二磊晶層806可具有鍺濃度從第二磊晶層806的頂表面806t朝向磊晶基部704逐漸減少。在一些實施例中，第二磊晶層806的摻雜劑濃度可沿著水平方向(例如沿著x軸)變化。在一些實施例中，可在第二磊晶層806中佈植任何適合的摻雜劑。例如，可在矽鍺材料中佈植硼至摻雜劑濃度介於約5×1019at/cm3和約2×1021at/cm3之間。在一些實施例中，可在矽材料中佈植磷或砷以形成磷化矽或砷化矽，其中磷化物或砷化物的摻雜劑濃度可介於約5×1019at/cm3和約2×1021at/cm3之間。
可使用適合的沉積方法沉積第二磊晶層806。例如，第二磊晶層806的沉積可使用方法類似於形成第一磊晶層602的方法。例如，可藉由使用例如甲鍺烷(germane)、二氯矽烷和鹽酸鹽之種類的電漿沉積製程，沉積矽鍺形成的第二磊晶層806。在一些實施例中，可藉由使用膦或砷的電漿沉積製程，分別沉積磷化矽或砷化矽形成的第二磊晶層806。可持續第二磊晶層806的沉積製 程直到填滿相對的內側間隔物127和磊晶末端帽702之間的開口。在一些實施例中，第二磊晶層806的頂表面806t接觸間隔物114並在最上層的半導體層122的頂表面上方。可使用可選的蝕刻製程以回蝕第二磊晶層806，從而避免摻雜劑從第二磊晶層806擴散進後續替代多晶矽閘極結構112而形成的金屬閘極結構。在一些實施例中，蝕刻製程可使用氯為基底的蝕刻劑，例如鹽酸鹽。在一些實施例中，蝕刻製程可回蝕第二磊晶層806使得第二磊晶層806不接觸間隔物114。在一些實施例中，執行蝕刻製程以減少第二磊晶層806和間隔物114之間的接觸表面面積。例如，頂表面806t可以是具有接觸間隔物114的端部的非平坦表面，其中間隔物114低於頂表面806t的最高部分。在一些實施例中，在相對的半導體層122之間的第二磊晶層806的寬度W1可介於約10nm和約80nm之間、介於約15nm和約75nm之間、介於約20nm和約60nm之間或任何適合的尺寸。在一些實施例中，從第二磊晶層806的頂表面806t測量至底表面806b的第二磊晶層806的高度H可介於約20nm和約140nm之間、介於約30nm和約120nm之間、介於約40nm和約100nm之間或任何適合的尺寸。
根據一些實施例，參考第1圖的步驟140中，形成第三磊晶層在第二磊晶層上。參考第9圖，第三磊晶層902可以是形成在第二磊晶層806上和相鄰的多晶矽閘極結構112之間的頂部覆蓋層。在一些實施例中，第三磊晶 層902的形成可使用矽、矽鍺、磷化矽、任何適合的半導體材料及/或上述的組合。在一些實施例中，第三磊晶層902可以由適合的摻雜劑摻雜，例如硼。在一些實施例中，第三磊晶層902的摻雜劑濃度可不同於第二磊晶層806的摻雜劑濃度。第三磊晶層902中硼或磷的摻雜劑濃度可大於第二磊晶層806的摻雜劑濃度。在一些實施例中，第三磊晶層902的硼或磷的摻雜劑濃度可介於約0.5×1021at/cm3和約5×1021at/cm3之間、介於約0.8×1021at/cm3和約4×1021at/cm3之間、介於約1×1021at/cm3和約3×1021at/cm3之間或任何適合的範圍。具有摻雜劑濃度高於第二磊晶層806的第三磊晶層902可提供減少和後續形成的源極/汲極接觸結構之間接觸電阻的益處。在一些實施例中，第三磊晶層902的形成可使用電漿沉積方法類似於形成第一磊晶層602和第二磊晶層806的方法。例如，可使用電漿沉積製程及/或選擇性磊晶沉積製程形成第三磊晶層902。第三磊晶層902的厚度T可介於約3nm和約40nm之間、介於約5nm和約35nm之間、介於約10nm和約30nm之間或任何適合的厚度。在一些實施例中，第三磊晶層902的寬度可類似於第二磊晶層806的寬度。例如，第三磊晶層902的寬度W2可類似於寬度W1，且介於約20nm和約60nm之間。根據一些實施例，半導體裝置200的源極/汲極區域可包括磊晶末端帽702、磊晶基部704、第二磊晶層806和第三磊晶層902。
根據一些實施例，第10圖繪示包括第9圖中區域的放大圖901和沉積磊晶層的多個區域中的摻雜劑分佈示意圖。第10圖中的示意圖繪示沿著放大圖901中繪示的半導體裝置200的截線D-D、截線E-E和截線F-F，第一磊晶層、第二磊晶層和第三磊晶層中鍺濃度和硼摻雜劑濃度變化。如第10圖中所示，水平的截線D-D與半導體層122、磊晶末端帽702和第二磊晶層806交錯。根據一些實施例，如沿著水平截線D-D的鍺濃度和硼摻雜劑濃度圖所示，第二磊晶層806中的濃度可以是最高的且在磊晶末端帽702中逐漸降低，以及在半導體層122中進一步逐漸降低。磊晶末端帽702可做為擴散屏障以減少短通道效應。例如，具有摻雜劑濃度低於第二磊晶層806的磊晶末端帽702可避免摻雜劑擴散至半導體層122和第二磊晶層806之間。水平的截線E-E與半導體層124、內側間隔物127和第二磊晶層806交錯。根據一些實施例，如沿著水平截線E-E的鍺濃度和硼摻雜劑濃度圖所示，第二磊晶層806中的摻雜劑濃度可大於在半導體層124和內側間隔物127中的摻雜劑濃度。垂直的截線F-F與第三磊晶層902、第二磊晶層806和磊晶基部704交錯。根據一些實施例，如沿著垂直截線F-F的鍺濃度雜劑濃度圖所示，第三磊晶層902中的摻雜劑濃度可以是最高的且在第二磊晶層806中逐漸降低，以及在磊晶基部704中進一步逐漸降低。例如，第二磊晶層806的鍺原子比例可從頂表面806t的約50%和約60%降低至底表面806b的約20%和約30%。 如沿著垂直截線F-F的硼摻雜劑濃度圖所示，第三磊晶層902和第二磊晶層806的摻雜劑濃度可實質上相同。在一些實施例中，第三磊晶層902的摻雜劑濃度可大於第二磊晶層806的摻雜劑濃度。在一些實施例中，第三磊晶層902的鍺原子比例可介於約30%和約70%之間、介於約35%和約65%之間、介於約40%和約60%之間或任何適合的比例。根據一些實施例，磊晶基部704的硼摻雜劑濃度可低於第二磊晶層806和第三磊晶層902的摻雜劑濃度。
根據一些實施例，參考第1圖的步驟145中，沉積層間介電(inter layer dielectric，ILD)層並執行替代閘極製程。參考第11圖，沉積層間介電層1118在間隔物114之間，且多晶矽閘極結構替換成金屬閘極結構。
層間介電層1118可沉積在源極/汲極區域的第三磊晶層902上和間隔物114之間。層間介電層1118可包括使用適合可流動介電材料(例如，可流動氧化矽、可流動氮化矽、可流動氮氧化矽、可流動碳化矽或可流動碳氧化矽)的沉積方法所沉積的介電材料。例如，可使用可流動CVD(flowable CVD，FCVD)沉積可流動氧化矽。在一些實施例中，介電材料可以是氧化矽。層間介電層1118的其他材料和形成方法也不脫離本公開的範圍和精神。
形成層間介電層1118後可接續使用乾式蝕刻製程(例如反應離子蝕刻)或濕式蝕刻製程移除多晶矽閘極結構112和半導體層124，並暴露部分的半導體層122。暴露的半導體層122可稱為奈米結構(例如奈米導線或奈米 片)。針對PMOS裝置配置，可移除半導體層122，暴露部分的半導體層124(亦可稱為奈米結構)。在一些實施例中，乾式蝕刻製程使用的氣體蝕刻劑可包括氯、氟、溴或上述的組合。在一些實施例中，可使用氫氧化銨(NH4OH)、氫氧化鈉(NaOH)及/或氫氧化鉀(KOH)濕式蝕刻以移除多晶矽閘極結構112和半導體層124，或可使用乾式蝕刻和接續的濕式蝕刻製程。可形成閘極介電層1112在半導體層上。如第11圖中所示，閘極介電層1112可以環繞在暴露的奈米導線形狀的第二半導體層122上。形成閘極介電層1112可包括適合的閘極介電材料層的毯覆沉積製程。在一些實施例中，閘極介電層1112可以由高介電常數介電材料(例如，具有介電常數大於約3.9的介電材料)形成。例如，閘極介電層1112可以由氧化鉿形成。功函數層1114形成在閘極介電層1112上。在一些實施例中，各個功函數層1114可包括一或多個功函數金屬層，並且由相同或不同材料及/或厚度所形成。各個閘極介電層1112和閘極功函數層1114可環繞奈米導線形狀的半導體層122。根據相鄰的半導體層122之間的空間，閘極介電層1112和功函數層1114可環繞半導體層122並填充相鄰的半導體層122之間的空間。在一些實施例中，後續形成的閘極電極材料也可形成於相鄰的半導體層122之間的空間，如下文所述。
根據一些實施例，閘極電極1116可形成在功函數層上。閘極電極1116的導電材料層形成在功函數層1114 上。如放大圖1140中所示，如果相鄰的半導體層122之間的分隔距離足以容納閘極電極材料的厚度，閘極電極1116可形成在相鄰的半導體層122之間和功函數層1114上，使得相鄰的半導體層122之間的空間已填滿。相鄰的半導體層122之間的閘極電極1116和形成在間隔物114之間的閘極電極1116彼此電性耦接。閘極電極1116的導電材料層可包括適合的導電材料，例如鈦、銀、鋁、鎢、銅、釕、鉬、氮化鎢、鈷、鎳、碳化鈦、碳化鋁鈦、錳、鋯、金屬合金和上述的組合。閘極電極1116可由ALD、PVD、CVD或任何其他適合的沉積製程所形成。可持續沉積閘極電極1116直到閘極電極1116填滿相對間隔物114之間的開口。化學機械研磨製程可移除多餘的閘極電極1116，使得閘極電極1116和層間介電層1118的頂表面實質上共平面。在一些實施例中，可形成其他結構，例如阻擋層。在沉積閘極電極1116之前可形成一或多個阻擋層(未示於第11圖中)以避免閘極電極1116的擴散和氧化。
根據一些實施例，參考第1圖的步驟150中，形成源極/汲極接觸和閘極接觸。參考第12圖，形成源極/汲極接觸1204和閘極接觸1206以分別提供電性連接至源極/汲極區域和閘極電極。具體而言，源極/汲極接觸1204和閘極接觸1206可用於在源極/汲極區域和閘極電極以及外部接點(未示於第12圖中)之間傳輸電子訊號。例如，閘極接觸1206可電性耦接至形成在間隔物114之間 和相鄰的半導體層122之間的閘極電極1116。額外的層間介電層可形成在層間介電層1118的頂表面上。例如，介電層1218可形成在層間介電層1118上。在一些實施例中，可使用和層間介電層1118相似的材料形成介電層1218。閘極接觸1206和源極/汲極接觸1204的形成可藉由形成開口在介電層1218、閘極電極1116和層間介電層1118，並且沉積導電材料在開口中。沉積製程可包括沉積金屬層在開口中並執行退火製程以引發沉積金屬層的矽化。形成源極/汲極接觸1204和閘極接觸1206的導電材料可包括鈦、鋁、銀、鎢、鈷、銅、釕、鋯、鎳、氮化鈦、氮化鎢、金屬合金及/或上述的組合。沉積製程可包括ALD、PVD、CVD、任何適合的沉積製程及/或上述的組合。閘極接觸1206和源極/汲極接觸1204可分別連接至閘極電極1116和源極/汲極區域的第三磊晶層902。
平坦化製程可平坦化介電層1218、源極/汲極接觸1204和閘極接觸1206的頂表面，使得這些頂表面實質上共平面。在一些實施例中，閘極接觸1206可延伸進閘極電極1116。在一些實施例中，源極/汲極接觸1204可延伸進源極/汲極區域的第三磊晶層902。在一些實施例中，源極/汲極接觸1204可延伸進第二磊晶層806。矽化物區域可形成在源極/汲極接觸1204和源極/汲極區域的第三磊晶層902之間以減少接觸電阻。例如，矽化物區域1202可形成在源極/汲極接觸1204和第三磊晶層902之間。在一些實施例中，矽化物區域1202可由矽化鈦材料 形成。矽化物區域1202的形成可藉由沉積導電材料層在第三磊晶層902上並執行退火製程。在一些實施例中，導電材料層可以是形成源極/汲極接觸1204的導電材料。在一些實施例中，導電材料層可以是與第三磊晶層902產生化學反應以產生矽化物區域1202的金屬薄膜。在一些實施例中，矽化物區域1202可包括矽化釕、矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鉑、矽化鉺、矽化鈀、任何適合的矽化物材料及/或上述的組合。
後段製程(Back-end-of-line，BEOL)內連結構形成在源極/汲極接觸1204和閘極接觸1206上方。BEOL內連結構可形成在沉積於介電層1218上的介電層1222中。內部連接可形成在介電層1222中。在一些實施例中，內部連接可以是電性連接網路，包括垂直(例如沿著z軸)延伸的通孔1226和橫向(例如沿著x軸)延伸的導線1228。內連結構可提供電性連接至源極/汲極接觸1204和閘極接觸1206。在一些實施例中，適合的被動和主動半導體裝置可形成在介電層1218和1222中，且為了簡單的目的未繪示於圖式中。
本公開的多個實施例描述形成無孔洞磊晶源極/汲極結構和避免半導體裝置的短通道效應的方法。例如，多步驟磊晶源極/汲極的形成製程可使用在形成源極/汲極結構。在一些實施例中，半導體裝置可實現奈米導線和奈米片結構，並具有間隔物形成在相鄰的奈米導線和奈米片之間。多步驟磊晶源極/汲極形成製程可包括形成圍繞奈米導 線或奈米片的末端部分的磊晶末端帽，以減少缺陷和避免短通道效應。額外的磊晶材料配置在磊晶末端帽和間隔物上直到形成源極/汲極結構的塊材。磊晶覆蓋層可形成在額外的磊晶材料的頂表面上以減少源極/汲極結構和後續形成的源極/汲極接觸之間的接觸電阻。本文描述的多步驟磊晶源極/汲極結構提供多種可改善裝置表現、可靠性和產率的益處。
在一些實施例中，一種半導體裝置包括在基板上的奈米結構和接觸奈米結構的源極/汲極區域。源極/汲極區域包括磊晶末端帽，其中各個磊晶末端帽形成在各個奈米結構的端部。源極/汲極區域亦包括接觸磊晶末端帽的磊晶塊體和形成在磊晶塊體上的磊晶頂部覆蓋層。半導體裝置進一步包括形成在奈米結構上的閘極結構。
在一些實施例中，磊晶末端帽包括新月型截面。在一些實施例中，各個奈米結構包括非平坦外側表面，且各個磊晶末端帽包括與非平坦外側表面的輪廓相符的內側表面。在一些實施例中，半導體裝置進一步包括複數個內側間隔物，其中內側間隔物的一者形成在相鄰的奈米結構之間。在一些實施例中，磊晶末端帽的一者接觸內側間隔物。在一些實施例中，半導體裝置進一步包括磊晶基部形成在基板的溝道中，其中磊晶基部和磊晶末端帽使用相同的材料形成。在一些實施例中，磊晶塊體包括第一鍺原子濃度，且磊晶基部包括第二鍺原子濃度小於第一鍺原子濃度。在一些實施例中，磊晶塊體包括第一鍺原子濃度，且磊晶末 端帽包括第二鍺原子濃度小於第一鍺原子濃度。在一些實施例中，磊晶塊體包括第一鍺原子濃度，磊晶末端帽包括第二鍺原子濃度大於第一鍺原子濃度。在一些實施例中，磊晶塊體包括非均勻鍺原子濃度，非均勻鍺原子濃度從磊晶塊體的頂表面減少至磊晶塊體的底表面。
在一些實施例中，一種半導體裝置包括奈米結構，且奈米結構中一者具有非平坦外側表面。半導體裝置亦包括環繞各個奈米結構的閘極介電層，以及配置在閘極介電層上和奈米結構上方的閘極電極。半導體裝置亦包括接觸奈米結構的源極/汲極區域。源極/汲極區域包括磊晶末端帽，其中磊晶末端帽形成在奈米結構的端部並具有第一摻雜劑濃度。源極/汲極區域進一步包括接觸磊晶末端帽的磊晶塊體，且磊晶塊體具有的第二摻雜劑濃度大於第一摻雜劑濃度。
在一些實施例中，半導體裝置進一步包括磊晶頂部覆蓋層形成在磊晶塊體上，其中磊晶頂部覆蓋層包括第三摻雜劑濃度大於第二摻雜劑濃度。在一些實施例中，磊晶末端帽包括新月型截面。在一些實施例中，半導體裝置進一步包括複數個間隔物，其中間隔物的一者接觸磊晶末端帽和奈米結構。在一些實施例中，間隔物接觸磊晶塊體。
在一些實施例中，一種形成半導體裝置的方法包括形成奈米結構在基板上並形成間隔物，其中各個間隔物形成在成對的奈米結構之間。方法亦包括蝕刻基板以形成凹槽。方法進一步包括沉積第一磊晶層在奈米結構的側壁上、 在間隔物的側壁上和在凹槽中。方法亦包括蝕刻第一磊晶層以形成磊晶末端帽和磊晶基部在凹槽中，其中各個磊晶末端帽形成在奈米結構的側壁上，且磊晶基部接觸間隔物。方法亦包括沉積第二磊晶層在磊晶末端帽和磊晶基部上。方法進一步包括蝕刻第二磊晶層和沉積第三磊晶層在經過蝕刻的第二磊晶層上。
在一些實施例中，蝕刻第一磊晶層包括形成各個磊晶末端帽的新月型截面。在一些實施例中，蝕刻第二磊晶層包括在第二磊晶層中佈植摻雜劑，使第二磊晶層的摻雜劑濃度大於第一磊晶層的摻雜劑濃度。在一些實施例中，方法進一步包括蝕刻第三磊晶層、形成矽化物層在經過蝕刻的第三磊晶層上，以及形成源極/汲極接觸在矽化物層上。在一些實施例中，方法進一步包括在第三磊晶層中佈植摻雜劑，使第三磊晶層的摻雜劑濃度大於第二磊晶層的摻雜劑濃度。
前面概述一些實施例的特徵，使得本領域技術人員可更好地理解本公開的觀點。本領域技術人員應該理解，他們可以容易地使用本公開作為設計或修改其他製程和結構的基礎，以實現相同的目的和/或實現與本文介紹之實施例相同的優點。本領域技術人員還應該理解，這樣的等同構造不脫離本公開的精神和範圍，並且在不脫離本公開的精神和範圍的情況下，可以進行各種改變、替換和變更。
106:基板
122,124:半導體層
127:內側間隔物
200:半導體裝置
702:磊晶末端帽
704:磊晶基部
806:第二磊晶層
902:第三磊晶層
1112:閘極介電層
1114:功函數層
1116:閘極電極
1118:層間介電層
1202:矽化物區域
1204:源極/汲極接觸
1206:閘極接觸
1218,1222:介電層
1226:通孔
1228:導線
x,z:軸

Claims (10)

  1. 一種半導體裝置，包括：複數個奈米結構在一基板上；一源極/汲極區域，接觸該些奈米結構，該源極/汲極區域包括：複數個磊晶末端帽，其中各該磊晶末端帽形成在該些奈米結構中一奈米結構的一端部；一磊晶塊體，接觸該些磊晶末端帽；以及一磊晶頂部覆蓋層，形成在該磊晶塊體上；以及一閘極結構，形成在該些奈米結構上。
  2. 如請求項1所述之半導體裝置，其中各該磊晶末端帽包括新月型截面。
  3. 如請求項1所述之半導體裝置，其中各該奈米結構包括一非平坦外側表面，且各該磊晶末端帽包括與該非平坦外側表面的輪廓相符的內側表面。
  4. 如請求項1所述之半導體裝置，進一步包括一磊晶基部形成在該基板的一溝道中，其中該磊晶基部和該些磊晶末端帽使用相同的材料形成。
  5. 如請求項1所述之半導體裝置，其中該磊晶塊體包括一非均勻鍺原子濃度，該非均勻鍺原子濃度從該 磊晶塊體的一頂表面減少至該磊晶塊體的一底表面。
  6. 一種半導體裝置，包括：複數個奈米結構，其中該些奈米結構的一奈米結構包括一非平坦外側表面；一閘極介電層，環繞各該奈米結構；一閘極電極，配置在該閘極介電層和該些奈米結構上；以及一源極/汲極區域，接觸該些奈米結構，該源極/汲極區域包括：複數個磊晶末端帽，其中該些磊晶末端帽的一磊晶末端帽形成在該奈米結構的一端部且具有一第一摻雜劑濃度；以及一磊晶塊體，接觸該磊晶末端帽，該磊晶塊體具有一第二摻雜劑濃度大於該第一摻雜劑濃度。
  7. 如請求項6所述之半導體裝置，進一步包括一磊晶頂部覆蓋層形成在該磊晶塊體上，其中該磊晶頂部覆蓋層包括一第三摻雜劑濃度大於該第二摻雜劑濃度。
  8. 如請求項6所述之半導體裝置，進一步包括複數個間隔物，其中該些間隔物的一間隔物接觸該磊晶末端帽和該奈米結構。
  9. 一種形成半導體裝置的方法，包括：形成複數個奈米結構在一基板上；形成複數個間隔物，其中各該間隔物形成在成對的該些奈米結構之間；蝕刻該基板以形成一凹槽；沉積一第一磊晶層在該些奈米結構的側壁上、該些間隔物的側壁上和該凹槽中；蝕刻該第一磊晶層以形成複數個磊晶末端帽和一磊晶基部在該凹槽中，其中各該磊晶末端帽形成在該些奈米結構中一奈米結構的端部，且該磊晶基部接觸該些間隔物的一間隔物；沉積一第二磊晶層在該些磊晶末端帽和該磊晶基部上；蝕刻該第二磊晶層；以及沉積一第三磊晶層在經過蝕刻的該第二磊晶層上。
  10. 如請求項9所述之方法，進一步包括：蝕刻該第三磊晶層；形成一矽化物層在經過蝕刻的該第三磊晶層上；以及形成一源極/汲極接觸在該矽化物層上。
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