CN113725189A - 包括层叠基板的半导体装置及制造该半导体装置的方法 - Google Patents

包括层叠基板的半导体装置及制造该半导体装置的方法 Download PDF

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CN113725189A
CN113725189A CN202110153230.1A CN202110153230A CN113725189A CN 113725189 A CN113725189 A CN 113725189A CN 202110153230 A CN202110153230 A CN 202110153230A CN 113725189 A CN113725189 A CN 113725189A
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semiconductor substrate
barrier layer
diffusion barrier
substrate body
semiconductor device
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金基范
金钟薰
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SK Hynix Inc
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SK Hynix Inc
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Abstract

本发明提供一种包括层叠基板的半导体装置及制造该半导体装置的方法。一种半导体装置包括垂直层叠在第一半导体基板上的第二半导体基板。第一半导体基板包括覆盖第一半导体基板主体的第一表面的第一扩散阻挡层、以及具有暴露于第一扩散阻挡层的第二表面的第三表面的第一通孔。第二半导体基板包括第二半导体基板主体、直接接合到第一扩散阻挡层的第二表面的第二扩散阻挡层、以及具有比第一通孔的第三表面更小的表面面积并直接接合至第一通孔的第三表面的前焊盘。

Description

包括层叠基板的半导体装置及制造该半导体装置的方法
技术领域
本公开总体上涉及一种半导体封装技术，并且更具体地，涉及一种包括层叠基板的半导体装置及制造该半导体装置的方法。
背景技术
半导体装置被用于各种电子应用中。半导体装置可以用于个人计算机、移动电话、相机等。半导体装置可以通过在半导体基板或半导体晶圆上沉积半导体材料层、导电层、介电层或绝缘层并对这些层进行图案化以形成电路组件和元件的工序、以及将半导体基板或晶圆分成单个晶片并且将单个晶片封装在封装件中的工序来制造。
随着诸如晶体管、电容器和二极管之类的各种电子组件的集成密度增加并且需要更小的封装件，最近已经开发了三维(3D)半导体装置。已经按诸如封装体叠层(PoP)或系统级封装(SiP)之类的封装形式开发了3D半导体装置。
发明内容
本公开的一方面提出了一种半导体装置，其包括第一半导体基板和垂直层叠在第一半导体基板上的第二半导体基板。
第一半导体基板可以包括：第一半导体基板主体；第一扩散阻挡层，其覆盖第一半导体基板主体的第一表面；以及第一通孔，其具有暴露于第一扩散阻挡层的第二表面的第三表面。
第二半导体基板可以包括：第二半导体基板主体，其设置在第一半导体基板主体上；第二扩散阻挡层，其覆盖第二半导体基板主体的面对第一半导体基板主体的第四表面，第二扩散阻挡层的第五表面的一部分直接接合到第一扩散阻挡层的第二表面；以及前焊盘，其具有暴露于第二扩散阻挡层的第五表面的第六表面，第六表面具有比第一通孔的第三表面更小的表面面积，并直接接合至第一半导体基板的第一通孔的第三表面。
本公开的一方面提出了一种半导体装置，其包括第一半导体基板和垂直层叠在第一半导体基板上的第二半导体基板。
第一半导体基板可以包括：第一半导体基板主体；第一扩散阻挡层，其覆盖第一半导体基板主体的第一表面；以及第一通孔，其具有暴露于第一扩散阻挡层的第二表面的第三表面。
第二半导体基板可以包括：第二半导体基板主体，其设置在第一半导体基板主体上；第二扩散阻挡层，其覆盖第二半导体基板主体的面对第一半导体基板主体的第四表面，并且具有局部地且直接地接合到第一扩散阻挡层的第二表面的第五表面；前焊盘，其具有第六表面并且接合至第一通孔的第三表面，第六表面暴露于第二扩散阻挡层的第五表面，具有比第一通孔的第三表面更小的表面面积；以及第二通孔，其电连接到前焊盘并贯穿第二半导体基板主体。
在根据本公开的一方面的制造半导体装置的方法中，第二半导体基板可以层叠在第一半导体基板上。该半导体装置的制造方法可以包括：形成第一半导体基板，该第一半导体基板包括覆盖第一半导体基板主体的第一表面的第一扩散阻挡层和具有暴露于第一扩散阻挡层的第二表面的第三表面的第一通孔；形成第二半导体基板，该第二半导体基板包括覆盖第二半导体基板主体的第四表面的第二扩散阻挡层、以及具有暴露于第二扩散阻挡层的第五表面的第六表面的前焊盘，第六表面具有比第一通孔的第三表面更小的表面面积；以及将第二半导体基板层叠在第一半导体基板上，以将第二扩散阻挡层的第五表面的一部分直接接合到第一扩散阻挡层的第二表面，并且将前焊盘的第六表面直接接合到第一通孔的第三表面。
附图说明
图1是例示了根据实施方式的半导体装置的截面图。
图2是例示了图1的半导体装置的第一半导体基板的截面图。
图3是例示了图1的半导体装置的第二半导体基板的截面图。
图4是例示了图1的第一通孔和前焊盘的放大的接合结构的截面图。
图5是例示了根据比较例的通孔和焊盘的接合结构中的铜污染的截面图。
图6是例示了根据实施方式的半导体装置的截面图。
图7至图10是例示了制造图1的半导体装置的方法的工艺步骤的截面图。
图11是例示了采用包括根据实施方式的封装件的存储卡的电子系统的框图。
图12是例示了包括根据实施方式的封装件的电子系统的框图。
具体实施方式
本文所使用的术语可以对应于考虑了它们在所提出的实施方式中的功能而选择的词语，并且这些术语的含义可以根据实施方式所属领域的普通技术人员而被解释为不同。如果详细定义了术语，则可以根据定义来解释这些术语。除非另有定义，否则本文中使用的术语(包括技术术语和科学术语)具有与实施方式所属领域的普通技术人员通常所理解的含义相同的含义。
将理解，尽管在本文中可以使用术语“第一”、“第二”、“第三”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一元件区分开，而不用于指示元件的特定顺序或数量。
还应理解，当元件或层被称为在另一元件或层“上”、“上方”、“下”、“下方”或“外部”时，该元件或层可以直接接触另一元件或层，或者可以存在中间元件或层。用于描述元件或层之间的关系的其它词语应该以类似方式来解释(例如，“在…之间”与“直接在…之间”或“相邻”与“直接相邻”)。
诸如“在…之下”、“在…下”、“下部”、“在…之上”、“上部”、“顶”、“底”等的空间相对术语可以用于描述元件和/或特征与另一元件和/或特征的关系，例如在附图中所示的。将理解的是，除了附图中描绘的方位之外，空间相对术语还旨在涵盖装置在使用和/或操作中的不同方位。例如，当附图中的装置翻转时，被描述为在另一元件或特征下和/或下方的元件将被定向在另一元件或特征上方。装置可以以其它方式(旋转90度或其它方位)来定向，并相应地解释本文使用的空间相对描述语。
根据各种实施方式，半导体封装件可以包括诸如半导体芯片或半导体晶片之类的电子装置。半导体芯片或半导体晶片可以通过使用划片工艺将诸如晶圆之类的半导体基板分离成多个片而获得。半导体芯片可以对应于存储器芯片、逻辑芯片、专用集成电路(ASIC)芯片、应用处理器(AP)、图形处理单元(GPU)、中央处理单元(CPU)或片上系统(SoC)。存储器芯片可以包括集成在半导体基板上的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型闪存电路、NOR型闪存电路、磁随机存取存储器(MRAM)电路、电阻随机存取存储器(ReRAM)电路、铁电随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)电路。逻辑芯片可以包括集成在半导体基板上的逻辑电路。半导体封装件可以被用在诸如移动电话、与生物技术或医疗健康相关的电子系统或可穿戴电子系统之类的通信系统中。半导体封装件可以适用于物联网(IoT)。
贯穿说明书中，相同的附图标记指代相同的元件。即使参照附图可能没有提及或描述附图标记，也会参照另一附图来提及或描述该附图标记。另外，即使在附图中可能未示出附图标记，也会在另一附图中示出该附图标记。
图1是例示了根据实施方式的半导体装置10的截面图。图2是例示了图1的半导体装置的第一半导体基板的截面图。图3是例示了图1的半导体装置的第二半导体基板200的截面图。
参照图1，半导体装置10可以包括第一半导体基板100和第二半导体基板200。第二半导体基板200可以基本上垂直地层叠在第一半导体基板100上。第一半导体基板100可以具有从半导体晶圆分离出的单个半导体晶片的形状。第二半导体基板200可以具有从半导体晶圆分离出的单个半导体晶片的形状。半导体装置10可以具有其中半导体晶片或半导体基板100和200三维层叠的结构。半导体装置10可以具有其中其它半导体基板在晶圆级被放置于半导体基板上方的结构。在另一实施方式中，第一半导体基板100和第二半导体基板200中的每一个可以具有半导体晶圆形状。
第二半导体基板200可以直接接合至第一半导体基板100。因为第二半导体基板200和第一半导体基板100的相对表面彼此紧密接触，所以第二半导体基板200和第一半导体基板100可以在它们之间没有介入其它分离构件的情况下彼此接合。单独的粘合剂材料或底层填充材料没有被引入到第二半导体基板200与第一半导体基板100直接接合的接合界面上。以这种方式将基板直接接合可以指示混合接合基板的方法。
图2是例示了图1的半导体装置10的第一半导体基板100的截面图。
参照图2和图1，第一半导体基板100可以包括第一半导体基板主体110、第一通孔120和第一扩散阻挡层140。第一半导体基板100可以进一步包括第二多层互连结构131、连接焊盘150和外部连接器160。第一半导体基板100还可以包括第一侧阻挡层126和第一缓冲层125。
第一半导体基板主体110可以包括硅(Si)或其它半导体材料。第一半导体基板主体110可以包括在上下方向上彼此面对的第一表面110B和第七表面110F。第一半导体基板主体110的第七表面110F可以是提供有源区(未示出)的前侧，在该有源区中集成有集成电路元件。第一半导体基板主体110的第一表面110B可以是位于第七表面110F的相对侧的后侧。在第一半导体基板主体110的第一表面110B上未集成有集成电路。
第一扩散阻挡层140可以设置为覆盖第一半导体基板主体110的第一表面110B。第一扩散阻挡层140可以包括介电材料或绝缘材料。第一扩散阻挡层140可以包括能够减少或防止铜(Cu)离子相对于氧化硅扩散的扩散阻挡材料。第一扩散阻挡层140可以包括氮化硅(Si3N4)层。在实施方式中，第一扩散阻挡层140可以包括碳氮化硅(SiCN)层。可以在第一扩散阻挡层140与第一半导体基板主体110的第一表面110B之间进一步引入另一介电层。
可以引入第一通孔120作为在上下方向上基本贯穿第一半导体基板主体110的垂直连接元件。可以引入第一通孔120作为硅通孔(TSV)元件。第一通孔120可以设置为从第一半导体基板主体110的第七表面110F至少延伸到第一表面110B的导电图案。第一通孔120可以延伸以突出在第一半导体基板主体110的第一表面110B上方。第一通孔120可以进一步延伸以基本贯穿第一扩散阻挡层140。
第一通孔120的端部处的第三表面120B可以暴露于第一扩散阻挡层140的第二表面140B。第一通孔120的端部处的第三表面120B和第一扩散阻挡层140的第二表面140B可以具有基本相同的表面高度。第一通孔120的端部处的第三表面120B和第一扩散阻挡层140的第二表面140B可以提供彼此连接而在其间没有台阶的整体上平坦的表面。
第一通孔120可以包括电阻率比铝(Al)或多晶硅更低的铜(Cu)。第一侧阻挡层126可以设置为覆盖第一通孔120的侧表面120S。可以引入第一侧阻挡层126作为有效地防止铜(Cu)离子从第一通孔120的侧表面120S向第一半导体基板主体110扩散的层。第一侧阻挡层126可以通过将第一半导体基板主体110与第一通孔120隔离来有效地防止第一半导体基板主体110被铜(Cu)污染。
第一缓冲层125可以设置在第一侧阻挡层126的一侧上。第一缓冲层125可以设置在第一扩散阻挡层140和第一侧阻挡层126之间以及第一半导体基板主体110与第一侧阻挡层126之间。第一侧阻挡层126可以在将第一半导体基板主体110与第一通孔120基本隔离的同时位于第一扩散阻挡层140和第一通孔120之间。
第一侧阻挡层126可以由防止第一通孔120的铜(Cu)离子扩散的扩散阻挡材料形成。第一侧阻挡层126可以包括氮化钽(TaN)层。可以引入第一缓冲层125作为将第一侧阻挡层126和第一半导体基板主体110隔离的层。可以引入第一缓冲层125作为减轻或减小在第一侧阻挡层126和第一半导体基板主体110之间可能发生的应力的层。可以引入第一缓冲层125作为减轻或减小在第一通孔120和第一半导体基板主体110之间可能涉及的应力的层。第一缓冲层125可以包括由诸如四乙氧基硅烷(TEOS)之类的材料制备的氧化硅(SiO2)层。
第一半导体基板100可以进一步包括电连接到第一通孔120的第二多层互连结构131。第二多层互连结构131可以设置在第一半导体基板主体110的第七表面110F上方。第二多层互连结构131可以包括彼此连接的多个互连层。第二多层互连结构131可以位于第一介电层132中并且可以通过第一介电层132绝缘。第二多层互连结构131的一些部分可以电连接到第一通孔120。第二多层互连结构131的其它部分可以电连接到在第一半导体基板主体110的第七表面110F上方集成的集成电路元件(未示出)。
第一半导体基板100还可以包括设置在第一半导体基板主体110的第七表面110F上方的连接焊盘150。连接焊盘150可以设置为电连接至第二多层互连结构131的导电图案。连接焊盘150可以设置为包括诸如铝(Al)或铜(Cu)之类的金属材料的导电图案。第二介电层180可以设置为在暴露出连接焊盘150的同时覆盖并保护第一介电层132。可以引入第二介电层180作为钝化层。
外部连接器160可以连接至连接焊盘150。可以引入外部连接器160作为将半导体装置10电连接至一个或更多个其它外部电子装置或电子模块或者一个或更多个其它印刷电路板(PCB)的连接元件。可以引入外部连接器160作为诸如导电凸块或焊球之类的连接元件。
图3是例示了图1的半导体装置10的第二半导体基板200的截面图。
参照图3和图1，第二半导体基板200可以包括第二半导体基板主体210、第二扩散阻挡层280和前焊盘260。第二半导体基板200可以进一步包括基焊盘250和第一多层互连结构231。第二半导体基板200可以进一步包括第二通孔220、第二侧阻挡层226和第二缓冲层225。
第二半导体基板主体210可以设置在第一半导体基板主体110上。第二半导体基板主体210可以包括硅(Si)或其它半导体材料。第二半导体基板主体210可以包括在上下方向上彼此面对的第四表面210F和第十表面210B。第二半导体基板主体210的第四表面210F可以是提供有源区(未示出)的前侧，在有源区中集成有集成电路元件(未示出)。第二半导体基板主体210的第十表面210B可以是位于第四表面210F的相对侧的后侧。在第二半导体基板主体210的第十表面210B上未集成有集成电路。
第二扩散阻挡层280可以设置为覆盖第二半导体基板主体210的第四表面210F。第二半导体基板主体210的第四表面210F可以是面对第一半导体基板主体110的表面。可以引入第二扩散阻挡层280作为面对第一扩散阻挡层140的层。第二扩散阻挡层280可以包括面对第一扩散阻挡层140的第二表面140B的第五表面280F。第二扩散阻挡层280的第五表面280F或第五表面280F的一部分可以直接接合到第一扩散阻挡层140的第二表面140B。第一扩散阻挡层140的第二表面140B和第二扩散阻挡层280的第五表面280F可以是通过直接接合而彼此直接接合的表面。没有粘合剂层或其它层介于第二表面140B和第五表面280F之间。为了直接接合，可以将第二扩散阻挡层280和第一扩散阻挡层140作为基本上相同的介电材料的层来引入。
第二扩散阻挡层280可以包括介电材料或绝缘材料。第二扩散阻挡层280可以包括能够减少或防止铜(Cu)离子相对于氧化硅扩散的扩散阻挡材料。第二扩散阻挡层280可以包括氮化硅(Si3N4)层。在实施方式中，第二扩散阻挡层280可以包括碳氮化硅(SiCN)层。可以在第二扩散阻挡层280与第二半导体基板主体210的第四表面210F之间进一步引入一个或更多个其它介电层。
前焊盘260可以设置为被第二扩散阻挡层280暴露。前焊盘260可以是具有暴露于第二扩散阻挡层280的第五表面280F的第六表面260F的导电图案。前焊盘260的第六表面260F和第二扩散阻挡层280的第五表面280F可以具有基本相同的表面高度。前焊盘260的第六表面260F和第二扩散阻挡层280的第五表面280F可以提供彼此连接而在其间没有台阶的整体上平坦的表面。
前焊盘260可以是基本上垂直贯穿第二扩散阻挡层280的导电图案。前焊盘260的第六表面260F可以直接接合到第一半导体基板100的第一通孔120的第三表面120B。前焊盘260的第六表面260F和第一通孔120的第三表面120B可以是通过直接接合而彼此直接接合的表面。在前焊盘260的第六表面260F和第一通孔120的第三表面120B之间没有插置粘合剂层或其它层。为了使前焊盘260的第六表面260F和第一通孔120的第三表面120B彼此直接接合并联接，前焊盘260和第一通孔120可以包括基本上相同的导电材料。前焊盘260和第一通孔120可以均包括含有铜(Cu)的导电层。
为了增加前焊盘260将位于第一通孔120的第三表面120B的区域内而不离开第三表面120B的区域的可能性，前焊盘260的第六表面260F的表面面积A1可以小于第一通孔120的第三表面120B的表面面积A3。前焊盘260可以形成为直径小于第一通孔120的直径的导电图案。因此，当第二半导体基板200垂直层叠在第一半导体基板100上时，可以提高前焊盘260能够位于第一通孔120的第三表面120B的区域内而不离开第一通孔120的第三表面120B的区域的裕度(margin)。可以提高第二半导体基板200相对于第一半导体基板100对齐的对齐裕度。
前焊盘260的第六表面260F的表面面积A1小于第一通孔120的第三表面120B的表面面积A3，使得第二扩散阻挡层280的一些部分能够延伸以覆盖第一通孔120的第三表面120B中的暴露于前焊盘260的第六表面260F外部的部分。因此，通过第二扩散阻挡层280的覆盖部分，能够有效地阻挡或防止铜(Cu)离子从第一通孔120的第三表面120B中的暴露于前焊盘260的第六表面260F外部的部分向其它区域扩散。
前焊盘260可以连接到基焊盘250。可以引入基焊盘250作为支撑前焊盘260的导电图案。基焊盘250可以是具有比前焊盘260的线宽更大的线宽的导电图案。基焊盘250可以包括与前焊盘260相同的导电材料。基焊盘250可以包括含有铜(Cu)的金属焊盘。基焊盘250可以是包含铝(Al)的金属焊盘。
第一多层互连结构231可以电连接到基焊盘250。第一多层互连结构231可以设置在第二半导体基板主体210的第四表面210F上方。第一多层互连结构231可以包括彼此连接的多个互连层。第一多层互连结构231可以位于第二介电层232中，并且可以通过第二介电层232隔离。第一多层互连结构231中的一些部分可以电连接到在第二半导体基板主体210的第四表面210F上方集成的集成电路元件(未示出)。
第一多层互连结构231的其它部分可以电连接到第二通孔220。可以引入第二通孔220作为基本上垂直贯穿第二半导体基板主体210的垂直连接元件。可以引入第二通孔220作为硅通孔(TSV)元件。第二通孔220可以设置为从第二半导体基板主体210的第四表面210F至少延伸到第十表面210B的导电图案。第二通孔220可以延伸以突出在第二半导体基板主体210的第十表面210B上方。第二通孔220可以进一步延伸以基本上垂直贯穿第三扩散阻挡层240。第二通孔220的端部处的第八表面220B可以暴露于第三扩散阻挡层240的第十一表面240B。第二通孔220的端部处的第八表面220B的表面面积A2可以大于前焊盘260的第六表面260F的表面面积A1。第二通孔220的端部处的第八表面220B的表面面积A2可以与图2中的第一通孔120的第三表面120B的表面面积A3基本相同。
第三扩散阻挡层240可以设置为覆盖第二半导体基板主体210的第十表面210B。第三扩散阻挡层240可以设置为包括介电材料或绝缘材料的层。第三扩散阻挡层240可以包括能够减少或防止铜(Cu)离子相对于氧化硅扩散的扩散阻挡材料。第三扩散阻挡层240可以包括氮化硅(Si3N4)层。在实施方式中，第三扩散阻挡层240可以包括碳氮化硅(SiCN)层。
第二通孔220可以包括电阻率比铝(Al)或多晶硅更低的铜(Cu)。第二侧阻挡层226可以设置为覆盖第二通孔220的侧表面220S。可以引入第二侧阻挡层226作为有效防止铜(Cu)离子从第二通孔220的侧表面220S向第二半导体基板主体210扩散的层。第二缓冲层225可以设置在第二侧阻挡层226的侧表面上。第二侧阻挡层226可以由防止第二通孔220的铜(Cu)离子扩散的扩散阻挡材料形成。第二侧阻挡层226可以包括氮化钽(TaN)层。第一缓冲层225可以包括由诸如四乙氧基硅烷(TEOS)之类的材料制备的氧化硅(SiO2)层。
图4是例示了图1的第一通孔120和前焊盘260的放大的接合结构的截面图。图5是例示了根据比较例的通孔12L和焊盘26U的接合结构1R中的铜污染的截面图。
参照图4，第二半导体基板200可以在层叠在第一半导体基板100上的同时直接接合到第一半导体基板100。第一通孔120的第三表面120B的表面面积A3大于前焊盘260的第六表面260F的表面面积A1，使得能够依据第一通孔120的直径和前焊盘260的直径之差，提高前焊盘260相对于第一通孔120的对齐裕度M。第一通孔120的第三表面120B的表面面积A3和前焊盘260的第六表面260F的表面面积A1之间的差越大，第一通孔120的直径和前焊盘260的直径之间的差就越大并且能够增大前焊盘相对于第一通孔的对齐裕度M。对齐裕度M越大，前焊盘260将位于第一通孔120的第三表面120B内的可能性就越高。随着对齐裕度M的增加，前焊盘260与第一通孔120的第三表面120B之外的第一缓冲层125交叠的可能性能够降低。
在根据图5的比较例的通孔12L和焊盘26U的接合结构1R中，上半导体基板1U的焊盘26U的直径D1大于下半导体基板1L的通孔12L的直径D2。在这种情况下，上半导体基板1U的焊盘26U可以与下半导体基板1L的缓冲层15L交叠。当焊盘26U由铜(Cu)形成时，铜(Cu)离子可以通过缓冲层15L的氧化硅从焊盘26U扩散到下半导体基板主体11L。由于铜(Cu)离子的扩散，导致下半导体基板主体11L会被铜(Cu)离子污染。
然而，在图4的第一通孔120和前焊盘260的接合结构中，前焊盘260具有比第一通孔120更小的直径，使得前焊盘260能够位于第一通孔120的第三表面120B内。因此，可以减小前焊盘260与第一缓冲层125交叠的可能性，从而减少或阻止铜(Cu)离子从包含铜(Cu)的前焊盘260扩散到第一半导体基板主体110。因此，可以有效地抑制、防止或减小第一半导体基板主体110中的铜(Cu)污染的发生。
前焊盘260的直径可以是第一通孔120的直径的1/2至1/6倍。前焊盘260的第六表面260F的表面面积A1是第一通孔120的第三表面120B的表面面积A3的1/4至1/36倍。前焊盘260可以具有约1.0μm至2.0μm的直径，而第一通孔120可以具有4.0μm至6.0μm的直径。
图6是例示了根据实施方式的半导体装置30的截面图。
与图4和图5一起参照图6，半导体装置30可以包括这样的结构，在该结构中第三半导体基板200-1直接接合到其中第二半导体基板200直接接合到第一半导体基板100的结构。第二半导体基板200直接接合到第一半导体基板100的结构可以具有与图1的半导体装置10基本相同的结构。第三半导体基板200-1可以具有与参照图1和图3描述的第二半导体基板200基本相同的结构。
第三半导体基板200-1可以包括与第二半导体基板200的前焊盘260相对应的另一前焊盘360。第三半导体基板200-1的前焊盘360的第九表面360F可以直接接合到第二通孔220的端部处的第八表面220B。
图7至图10是例示了制造图1的半导体装置10的方法的工艺步骤的截面图。
参照图7，可以在第二半导体基板200的第二半导体基板主体210的第四表面210F上方形成第一多层互连结构231。基焊盘250可以形成为连接到第一多层互连结构231。可以在第二半导体基板主体210中设置第二通孔220。
参照图8，可以形成第二扩散阻挡层280以覆盖第二半导体基板主体210的第四表面210F。可以形成第二扩散阻挡层280以覆盖使第一多层互连结构231绝缘的第二介电层232。抗蚀剂图案290可以形成在第二扩散阻挡层280的第五表面280F上。抗蚀剂图案290可以在前焊盘(图1中的260)将要位于的部分中具有通孔形状的开口290H。可以通过涂敷、曝光和显影光致抗蚀剂层来形成抗蚀剂图案290。
可以选择性地去除第二扩散阻挡层280中的被抗蚀剂图案290暴露的部分，以形成镶嵌孔280H。可以执行使用抗蚀剂图案290作为蚀刻掩模的选择性蚀刻工艺，以在第二扩散阻挡层280中形成镶嵌孔280H。
参照图9，可以形成导电层260L以填充镶嵌孔280H。可以通过铜(Cu)电镀工艺形成导电层260L。可以部分地去除导电层260L至一定厚度，使得导电层的一部分保留在镶嵌孔280H中。在实施方式中，可以部分地去除导电层260L至预定厚度，使得导电层的一部分保留在镶嵌孔280H中。导电层的其余部分可以被图案化为前焊盘(图3的260)。前焊盘(图3的260)可以被图案化为位于镶嵌孔(图3中的280H)内的导电图案。如本文针对参数所使用的词语“预定”(诸如预定厚度)表示该参数的值在过程或算法中使用该参数之前被确定。对于一些实施方式，在过程或算法开始之前确定参数的值。在其它实施方式中，在过程或算法期间但在过程或算法中使用参数之前确定参数的值。
参照图10，第二半导体基板200可以形成为包括基本上覆盖第二半导体基板主体210的第四表面210F的第二扩散阻挡层280以及前焊盘260，在前焊盘中暴露于第二扩散阻挡层280的第五表面280F的第六表面260F具有比第一通孔120的第三表面120B更小的表面面积Al。
第一半导体基板100可以形成为包括覆盖第一半导体基板主体110的第一表面110B的第一扩散阻挡层140以及第一通孔120，在第一通孔中第三表面120B暴露于第一扩散阻挡层140的第二表面140B。
第二半导体基板200可以层叠在第一半导体基板100上。在将第二扩散阻挡层280的第五表面280F的一部分直接接合到第一扩散阻挡层140的第二表面140B的同时，前焊盘260的第六表面260F可以直接接合到第一通孔120的第三表面120B。因此，由于第一半导体基板100和第二半导体基板200直接接合，所以可以实现包括第一半导体基板100和第二半导体基板200的层叠物的半导体装置10。
图11是例示了包括采用根据实施方式的半导体封装件中的至少一个的存储卡7800的电子系统的框图。存储卡7800包括诸如非易失性存储器装置之类的存储器7810和存储器控制器7820。存储器7810和存储器控制器7820可以存储数据或读出所存储的数据。存储器7810和存储器控制器7820中的至少一个可以包括根据实施方式的半导体封装件中的至少一个。
存储器7810可以包括应用了本公开的实施方式的技术的非易失性存储器装置。存储器控制器7820可以响应于来自主机7830的读/写请求而控制存储器7810以使得读出所存储的数据或对数据进行存储。
图12是例示了包括根据实施方式的半导体封装件中的至少一个的电子系统8710的框图。电子系统8710可以包括控制器8711、输入/输出装置8712和存储器8713。控制器8711、输入/输出装置8712和存储器8713可以通过提供数据移动所通过的路径的总线8715而彼此联接。
在实施方式中，控制器8711可以包括一个或更多个微处理器、数字信号处理器、微控制器和/或能够执行与这些组件相同功能的逻辑器件。控制器8711或存储器8713可以包括根据本公开的实施方式的半导体封装件中的至少一个。输入/输出装置8712可以包括选自小键盘、键盘、显示装置、触摸屏等中的至少一种。存储器8713是用于存储数据的装置。存储器8713可以存储数据和/或控制器8711要执行的命令等。
存储器8713可以包括诸如DRAM之类的易失性存储器装置和/或诸如闪存之类的非易失性存储器装置。例如，闪存可以安装到诸如移动终端或台式计算机之类的信息处理系统。闪存可以组成固态硬盘(SSD)。在这种情况下，电子系统8710可以在闪存系统中稳定地存储大量数据。
电子系统8710可以进一步包括被配置为向通信网络发送数据和从通信网络接收数据的接口8714。接口8714可以是有线类型或无线类型。例如，接口8714可以包括天线、或者有线或无线收发器。
电子系统8710可以被实现为执行各种功能的移动系统、个人计算机、工业计算机或逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统中的任何一种。
如果电子系统8710是能够执行无线通信的设备，则电子系统8710可以用在使用CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强时分多址)、WCDMA(宽带码分多址)、CDMA2000、LTE(长期演进)或Wibro(无线宽带互联网)的技术的通信系统中。
已经结合如上所述的一些实施方式公开了这些概念。本领域技术人员将理解，在不脱离本公开的范围和精神的情况下，可以进行各种修改、添加和替换。因此，不应从限制性的观点而应从示例性的观点来考虑本说明书中公开的实施方式。概念的范围不限于以上描述，而是由所附权利要求书限定，并且等效范围内的所有不同特征全部应解释为被包括在概念中。
相关申请的交叉引用
本申请要求于2020年5月25日提交的韩国申请No.10-2020-0062611的优先权，该韩国申请的全部内容通过引用合并于本文中。

Claims (20)

1.一种半导体装置，该半导体装置包括：
第一半导体基板；以及
第二半导体基板，该第二半导体基板垂直层叠在所述第一半导体基板上，
其中，所述第一半导体基板包括：
第一半导体基板主体；
第一扩散阻挡层，该第一扩散阻挡层覆盖所述第一半导体基板主体的第一表面；以及
第一通孔，该第一通孔具有暴露于所述第一扩散阻挡层的第二表面的第三表面，
其中，所述第二半导体基板包括：
第二半导体基板主体，该第二半导体基板主体设置在所述第一半导体基板主体上；
第二扩散阻挡层，该第二扩散阻挡层覆盖所述第二半导体基板主体的面对所述第一半导体基板主体的第四表面，该第二扩散阻挡层的第五表面的一部分直接接合到所述第一扩散阻挡层的所述第二表面；以及
前焊盘，该前焊盘具有暴露于所述第二扩散阻挡层的所述第五表面的第六表面，所述第六表面具有比所述第一通孔的所述第三表面更小的表面面积，并且直接接合至所述第一半导体基板的所述第一通孔的所述第三表面。
2.根据权利要求1所述的半导体装置，其中，所述第二扩散阻挡层的一部分延伸以覆盖所述第一通孔的所述第三表面的暴露于所述前焊盘的所述第六表面外部的部分。
3.根据权利要求1所述的半导体装置，其中，所述第一通孔延伸以贯穿所述第一扩散阻挡层和所述第一半导体基板主体。
4.根据权利要求2所述的半导体装置，该半导体装置还包括：
第一侧阻挡层，该第一侧阻挡层覆盖所述第一通孔的侧表面；以及
第一缓冲层，该第一缓冲层设置在所述第一扩散阻挡层与所述第一侧阻挡层之间以及在所述第一半导体基板主体与所述第一侧阻挡层之间。
5.根据权利要求4所述的半导体装置，其中，所述第一通孔包含铜Cu，所述第一侧阻挡层包含氮化钽TaN，并且所述第一缓冲层包含氧化硅SiO2。
6.根据权利要求1所述的半导体装置，其中，所述第一扩散阻挡层包含氮化硅Si3N4和碳氮化硅SiCN中的至少一种。
7.根据权利要求1所述的半导体装置，其中，所述第二扩散阻挡层包含氮化硅Si3N4和碳氮化硅SiCN中的至少一种。
8.根据权利要求1所述的半导体装置，其中，所述前焊盘包含铜Cu。
9.根据权利要求1所述的半导体装置，该半导体装置还包括基焊盘，该基焊盘与所述前焊盘连接，
其中，所述基焊盘比所述前焊盘宽。
10.根据权利要求9所述的半导体装置，其中，所述基焊盘包括与所述前焊盘相同的材料。
11.根据权利要求9所述的半导体装置，其中，所述基焊盘包含铜Cu和铝Al中的至少一种。
12.根据权利要求9所述的半导体装置，该半导体装置还包括第一多层互连结构，该第一多层互连结构电连接到所述基焊盘。
13.根据权利要求1所述的半导体装置，该半导体装置还包括：
第二多层互连结构，该第二多层互连结构设置在所述第一半导体基板主体的与所述第一表面相对的第七表面上，并且电连接至所述第一通孔；
连接焊盘，该连接焊盘连接到所述第二多层互连结构；以及
外部连接器，该外部连接器连接到所述连接焊盘。
14.一种半导体装置，该半导体装置包括：
第一半导体基板；以及
第二半导体基板，该第二半导体基板垂直层叠在所述第一半导体基板上，
其中，所述第一半导体基板包括：
第一半导体基板主体；
第一扩散阻挡层，该第一扩散阻挡层覆盖所述第一半导体基板主体的第一表面；以及
第一通孔，该第一通孔具有暴露于所述第一扩散阻挡层的第二表面的第三表面，
其中，所述第二半导体基板包括：
第二半导体基板主体，该第二半导体基板主体设置在所述第一半导体基板主体上；
第二扩散阻挡层，该第二扩散阻挡层覆盖所述第二半导体基板主体的面对所述第一半导体基板主体的第四表面，所述第二扩散阻挡层的第五表面的一部分直接接合到所述第一扩散阻挡层的所述第二表面；
前焊盘，该前焊盘具有暴露于所述第二扩散阻挡层的所述第五表面的第六表面，所述第六表面具有比所述第一通孔的所述第三表面更小的表面面积，并直接接合至所述第一半导体基板的所述第一通孔的所述第三表面；以及
第二通孔，该第二通孔电连接到所述前焊盘并贯穿所述第二半导体基板主体。
15.根据权利要求14所述的半导体装置，该半导体装置还包括：
基焊盘，该基焊盘连接至所述前焊盘，所述基焊盘比所述前焊盘宽；
第一多层互连结构，该第一多层互连结构电连接到所述基焊盘，
其中，所述第二通孔电连接至所述第一多层互连结构。
16.根据权利要求15所述的半导体装置，该半导体装置还包括第三半导体基板，该第三半导体基板包括另一前焊盘，所述另一前焊盘具有与所述第二通孔的端部处的第八表面直接接合的第九表面。
17.根据权利要求14所述的半导体装置，该半导体装置还包括：
第二多层互连结构，该第二多层互连结构设置在所述第一半导体基板主体的与所述第一表面相对的第七表面上，并电连接至所述第一通孔；
连接焊盘，该连接焊盘连接到所述第二多层互连结构；以及
外部连接器，该外部连接器连接到所述连接焊盘。
18.根据权利要求14所述的半导体装置，其中，所述第二扩散阻挡层的一部分延伸以覆盖所述第一通孔的所述第三表面的暴露于所述前焊盘的所述第六表面外部的部分。
19.一种制造半导体装置的方法，该方法包括以下步骤：
形成第一半导体基板，该第一半导体基板包括覆盖第一半导体基板主体的第一表面的第一扩散阻挡层和具有暴露于所述第一扩散阻挡层的第二表面的第三表面的第一通孔；
形成第二半导体基板，该第二半导体基板包括覆盖第二半导体基板主体的第四表面的第二扩散阻挡层和具有暴露于所述第二扩散阻挡层的第五表面的第六表面的前焊盘，所述第六表面具有比所述第一通孔的所述第三表面更小的表面面积；以及
将所述第二半导体基板层叠在所述第一半导体基板上，以将所述第二扩散阻挡层的所述第五表面的一部分直接接合到所述第一扩散阻挡层的所述第二表面并且将所述前焊盘的所述第六表面直接接合到所述第一通孔的所述第三表面。
20.根据权利要求19所述的方法，其中，通过以下步骤形成所述前焊盘：
在所述第二扩散阻挡层的所述第五表面上形成抗蚀剂图案；
选择性地去除所述第二扩散阻挡层中的被所述抗蚀剂图案暴露的部分以形成镶嵌孔；
形成导电层以填充所述镶嵌孔；以及
去除所述导电层至预定厚度以将所述导电层图案化为位于所述镶嵌孔中的所述前焊盘。
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