CN113678265A - Method for manufacturing solar cell, semi-finished solar cell substrate and solar cell - Google Patents

Method for manufacturing solar cell, semi-finished solar cell substrate and solar cell Download PDF

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CN113678265A
CN113678265A CN202080024664.5A CN202080024664A CN113678265A CN 113678265 A CN113678265 A CN 113678265A CN 202080024664 A CN202080024664 A CN 202080024664A CN 113678265 A CN113678265 A CN 113678265A
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layer
semiconductor layer
conductivity type
peeling
solar cell
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CN113678265B (en
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阿部祐介
吉田航
日野将志
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Kaneka Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

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Abstract

The invention provides a method for manufacturing a solar cell, a semi-finished solar cell substrate, and a solar cell, which are easy to produce in large quantities and have a good yield compared with the prior art. The method comprises the following steps: a 1 st semiconductor layer forming step of forming a reverse conductivity type semiconductor layer (16) on a 1 st principal surface side of a semiconductor substrate (5), a peeling layer forming step of forming a peeling layer (50) containing silicon oxide or silicon nitride as a main component on the reverse conductivity type semiconductor layer (16), a 2 nd semiconductor layer forming step of forming a one conductivity type semiconductor layer (11) so as to have a portion overlapping with the peeling layer (50) when the semiconductor substrate (5) is viewed in plan, and a peeling step of dissolving the peeling layer (50) with a peeling solution to remove the overlapping portion of the one conductivity type semiconductor layer (11); in the release layer forming step, a 1 st reaction gas is blown at a film forming temperature of 150 ℃ or lower to form a release layer (50).

Description

Method for manufacturing solar cell, semi-finished solar cell substrate and solar cell
Technical Field
The invention relates to a method for manufacturing a solar cell, a semi-finished solar cell substrate and a solar cell.
Background
In recent years, a back contact type solar cell in which an electrode layer is provided only on the back surface side of a semiconductor substrate has been developed (patent document 1).
In this back contact type solar cell, the pair of electrode layers or the semiconductor layers of different conductivity types are disposed in close proximity to each other, and therefore, the pair of electrode layers or the semiconductor layers of different conductivity types must be patterned with high accuracy.
Therefore, as a method for patterning with high accuracy, patent document 1 discloses a method for patterning a semiconductor layer by lift-off.
Documents of the prior art
Patent document
Patent document 1 Japanese patent laid-open publication No. 2013-120863
Disclosure of Invention
However, in order to reduce the manufacturing cost of the solar cell, a large number of solar cells need to be formed at the same time. Therefore, the present inventors tried a back contact type solar cell by forming a peeling layer on a plurality of substrates simultaneously with a silicon oxide layer by using a large-area (1200 mm in length × 1000mm in width) plasma CVD apparatus with reference to the peeling method of patent document 1.
However, in the case of the trial-produced peeling method, a solar cell of good quality can be obtained even when the film is formed in a small area, but when the film is formed in a large area, there are problems such as an increase in film thickness distribution between substrates, variation in quality, and poor yield.
Accordingly, an object of the present invention is to provide a method for manufacturing a solar cell and a solar cell, which are easy to mass-produce and have a good yield as compared with the conventional art.
It is another object of the present invention to provide a semi-finished solar cell substrate which can be efficiently peeled off to improve the manufacturing efficiency, compared to the prior art, when manufacturing a solar cell.
One embodiment of the present invention for solving the above problems is a method for manufacturing a solar cell, the solar cell including a first conductive type semiconductor layer, an opposite conductive type semiconductor layer, a 1 st electrode layer, and a 2 nd electrode layer on a 1 st main surface side of a semiconductor substrate, the first conductive type semiconductor layer being interposed between the semiconductor substrate and the 1 st electrode layer, and the opposite conductive type semiconductor layer being interposed between the semiconductor substrate and the 2 nd electrode layer; the manufacturing method includes a 1 st semiconductor layer forming step of forming the reverse conductivity type semiconductor layer on a 1 st main surface side of the semiconductor substrate, a peeling layer forming step of forming a peeling layer containing silicon oxide or silicon nitride as a main component on the reverse conductivity type semiconductor layer, a 2 nd semiconductor layer forming step of forming the one conductivity type semiconductor layer so that a part thereof has an overlapping portion with the peeling layer in a plan view of the semiconductor substrate, and a peeling step of dissolving the peeling layer with a peeling solution to remove the overlapping portion of the one conductivity type semiconductor layer; in the step of forming the release layer, a 1 st reaction gas is blown at a film forming temperature of 150 ℃ or lower to form the release layer.
The term "one conductivity type" as used herein means n-type or p-type, and the term "reverse conductivity type" means a conductivity type opposite to the one conductivity type, i.e., p-type in the case where the one conductivity type is n-type, and n-type in the case where the one conductivity type is p-type.
The term "main component" as used herein means a component which accounts for 50% or more of the total components.
According to this embodiment, the peeling layer can be dissolved with a peeling solution to enable patterning of the one-conductivity type semiconductor layer, and therefore, the semiconductor device can be manufactured at low cost as compared with a conventional method in which patterning is performed with a photoresist.
According to this embodiment, since the peeling layer containing silicon oxide or silicon nitride as a main component is formed at a deposition temperature of 150 ℃ or lower, the peeling layer having a uniform in-plane film thickness distribution and a large density can be formed even in a large-area deposition apparatus. Therefore, it is possible to easily form a release layer having a high etching rate in a release solution while mass production is possible.
The preferred mode is as follows: the method includes a protective layer forming step of forming a protective layer on the peeling layer, the protective layer containing silicon oxide or silicon nitride as a main component and having a higher density than the peeling layer.
The preferred mode is as follows: a resist layer forming step of forming a resist layer having a predetermined shape on an outer side of the reverse conductivity type semiconductor layer with reference to the semiconductor substrate, an etching step of removing a part of the reverse conductivity type semiconductor layer with an etching solution, and a resist layer removing step of removing the resist layer; in the resist layer forming step, a non-overlapping portion that does not overlap with the resist layer exists in the reverse conductivity type semiconductor layer when the semiconductor substrate is viewed in plan, and in the etching step, a part or all of the non-overlapping portion of the reverse conductivity type semiconductor layer is removed.
However, in the case of forming a silicon oxide layer at a high temperature (for example, 180 ℃ or higher), hydrogen atoms incorporated into the film increase if the raw material gas is diluted with hydrogen. Therefore, the inventors consider that: when the film is formed at a low temperature (150 ℃ or lower), a sparse film can be formed if the raw material gas is diluted with hydrogen. However, when a silicon oxide layer is actually formed at a low temperature using a hydrogen-diluted source gas, a dense film is formed contrary to the expectation.
The preferred way to derive from this result is: a protective layer forming step of forming a protective layer containing silicon oxide as a main component on the peeling layer; in the protective layer forming step, a 2 nd reaction gas is blown at a temperature of 150 ℃ or lower to form the protective layer; the 2 nd reaction gas contains silane gas, carbon dioxide and hydrogen.
According to this embodiment, since the 2 nd reaction gas diluted with hydrogen is used to form the protective layer at a low temperature, a dense protective layer can be easily formed.
The preferred mode is as follows: the flow ratio of the hydrogen gas to the silane gas in the 2 nd reaction gas is 50 or more.
However, in the case where a plurality of layers are continuously formed in the same film forming chamber, if film formation is performed under high temperature conditions (for example, 180 ℃ or higher) and then film formation is performed under low temperature conditions (for example, 150 ℃ or lower), cooling is necessary until the temperature in the film forming chamber reaches the low temperature conditions. Similarly, in the case of film formation under a high temperature condition after film formation under a low temperature condition, heating is required until the temperature of the film forming chamber reaches the high temperature condition.
In the film forming apparatus, the time for raising the temperature from the low temperature condition to the high temperature condition is generally shorter than the time for lowering the temperature from the high temperature condition to the low temperature condition.
Therefore, a preferred mode is: the film forming temperature of the protective layer in the protective layer forming step is substantially equal to or higher than the film forming temperature of the release layer in the release layer forming step, and the temperature difference from the film forming temperature of the release layer in the release layer forming step is 50 ℃ or lower.
The phrase "the film formation temperature of the protective layer is substantially equal to or higher than the film formation temperature of the release layer" as used herein means that slight temperature fluctuations (for example, 3 ℃) are allowed in the film formation temperature due to the outside air, the device performance, and the like. For example, the film forming temperature of the protective layer is not less than (the film forming temperature of the release layer-3 ℃ C.).
According to this embodiment, the film can be efficiently and continuously formed.
One embodiment of the present invention is a method for manufacturing a solar cell, the method including providing a first conductivity type semiconductor layer, a reverse conductivity type semiconductor layer, a 1 st electrode layer, and a 2 nd electrode layer on a 1 st main surface side of a semiconductor substrate, the first conductivity type semiconductor layer being interposed between the semiconductor substrate and the 1 st electrode layer, and the reverse conductivity type semiconductor layer being interposed between the semiconductor substrate and the 2 nd electrode layer; the manufacturing method includes a 1 st semiconductor layer forming step of forming the reverse conductivity type semiconductor layer on a 1 st main surface side of the semiconductor substrate; a separation layer forming step of forming a separation layer containing silicon oxide or silicon nitride as a main component on the reverse conductivity type semiconductor layer; a protective layer forming step of forming a protective layer containing silicon oxide or silicon nitride as a main component and having a higher density than the peeling layer on the peeling layer; a 2 nd semiconductor layer forming step of forming the one conductivity type semiconductor layer so as to have a portion overlapping with the peeling layer in a plan view of the semiconductor substrate; and a peeling step of dissolving the peeling layer with a peeling solution to remove the overlapped portion of the one conductivity type semiconductor layer; the peeling step is performed after the protective layer forming step, in which a 2 nd reaction gas is blown at a temperature of 150 ℃ or lower to form the protective layer, the 2 nd reaction gas contains silane gas, carbon dioxide, and hydrogen gas, and the flow ratio of hydrogen gas to silane gas is 50 or more.
According to this embodiment, the peeling layer can be dissolved with a peeling solution to pattern the one-conductivity-type semiconductor layer, and therefore, compared with a conventional method in which patterning is performed using a photoresist, the manufacturing process can be simplified, and the manufacturing can be performed at low cost.
According to this embodiment, since the protective layer is formed using the 2 nd reaction gas obtained by diluting the silane gas with hydrogen gas at 150 ℃ or lower in the protective layer forming step, a dense protective layer can be formed.
Here, in a recent manufacturing process of a solar cell, the solar cell is sometimes manufactured not only at one place but at a plurality of places. That is, there are cases where: a semi-finished solar cell substrate, which is a semi-finished product of a solar cell, is manufactured at one place, and a solar cell is manufactured using the semi-finished solar cell substrate at another place. Therefore, not only the structure of the finished product but also the structure of the semi-finished solar cell substrate as a semi-finished product is important for mass production of solar cells.
One embodiment of the present invention is a semi-finished solar cell substrate including a first conductivity type semiconductor layer and an opposite conductivity type semiconductor layer on a 1 st principal surface side of a semiconductor substrate, the semiconductor substrate being a reference, a peeling layer being provided on an outer side of the opposite conductivity type semiconductor layer, the peeling layer including the first conductivity type semiconductor layer laminated on an outer side of the semiconductor substrate, the first conductivity type semiconductor layer having a portion overlapping the peeling layer when the semiconductor substrate is viewed in plan, the peeling layer being capable of being immersed in a peeling solution to dissolve and remove the overlapping portion of the first conductivity type semiconductor layer, the peeling layer being composed mainly of silicon oxide, and having an etching rate of 5nm/s or more when immersed in 2 wt% hydrofluoric acid.
According to this embodiment, peeling can be efficiently performed, and manufacturing efficiency can be improved.
The preferred mode is as follows: the peeling layer has a protective layer containing silicon oxide or silicon nitride as a main component and having a higher density than the peeling layer.
However, the present inventors have conducted repeated studies and found the following. That is, the refractive index tends to increase as the density of silicon oxide increases, and to decrease as the density decreases. In addition, the following tendency also exists in silicon oxide: if the density is increased, the etching rate in hydrofluoric acid is increased, and if the density is decreased, the etching rate in hydrofluoric acid is decreased.
Therefore, the present inventors have studied the correlation between the refractive index in silicon oxide and the etching rate in hydrofluoric acid, and as a result, have found that: it can be seen that there is a certain correlation between the refractive index and the etching rate in hydrofluoric acid, and by setting the refractive index to a certain range, good etching is possible and peeling can be performed efficiently.
The preferred mode is as follows: the peeling layer has a protective layer containing silicon oxide as a main component and having a refractive index higher than that of the peeling layer.
According to this embodiment, the etching rate of the protective layer can be made slower than that of the release layer.
One embodiment of the present invention is a semi-finished solar cell substrate including a conductive semiconductor layer on a 1 st principal surface side of a semiconductor substrate; on the outer side of the conductive semiconductor layer, a peeling layer containing silicon oxide as a main component and having an etching rate of 5nm/s or more when immersed in 2 wt% hydrofluoric acid and a protective layer containing silicon oxide or silicon nitride as a main component and having a higher density than the peeling layer are sequentially stacked.
According to this embodiment, peeling can be efficiently performed, and manufacturing efficiency can be improved.
The preferred mode is as follows: the outermost surface of the semiconductor substrate on the 2 nd principal surface side is covered with a 2 nd protective layer, and the etching rate of the 2 nd protective layer when immersed in 2 wt% hydrofluoric acid is lower than that of the peeling layer.
In the above aspect, the outermost surface of the 2 nd main surface side of the semiconductor substrate may be coated with a 2 nd protective layer, and the 2 nd protective layer may have resistance to the stripping liquid.
One embodiment of the present invention is a solar cell including a first conductive type semiconductor layer, an opposite conductive type semiconductor layer, a 1 st electrode layer, and a 2 nd electrode layer on a 1 st main surface side of a semiconductor substrate, the first conductive type semiconductor layer being interposed between the semiconductor substrate and the 1 st electrode layer, and the opposite conductive type semiconductor layer being interposed between the semiconductor substrate and the 2 nd electrode layer; the semiconductor device includes an intrinsic semiconductor layer interposed between the semiconductor substrate, the one-conductivity-type semiconductor layer, and the reverse-conductivity-type semiconductor layer, and interposed between the one-conductivity-type semiconductor layer and the reverse-conductivity-type semiconductor layer in the expansion direction of the 1 st main surface of the semiconductor substrate, wherein the intrinsic semiconductor layer is exposed in a direction perpendicular to the 1 st main surface from between the one-conductivity-type semiconductor layer and the reverse-conductivity-type semiconductor layer.
According to this embodiment, the intrinsic semiconductor layer can prevent contact between the electrode layers and the semiconductor layer having a different conductivity type, and thus a solar cell having excellent safety can be obtained.
According to this embodiment, the substrate can be formed by the above-described manufacturing method, and mass production is facilitated.
The preferred mode is as follows: the intrinsic semiconductor layer is composed of a 1 st intrinsic layer and a 2 nd intrinsic layer, the 1 st intrinsic layer is interposed between the semiconductor substrate and the reverse conductive semiconductor layer, the 2 nd intrinsic layer is interposed between the semiconductor substrate and the one conductive semiconductor layer, and the 2 nd intrinsic layer is not covered outside the reverse conductive semiconductor layer with respect to the semiconductor substrate.
More preferred is: the 2 nd intrinsic layer is located on the same plane as or inside the outer side surface of the reverse conductivity type semiconductor layer with respect to the semiconductor substrate.
According to the method for manufacturing a solar cell and the solar cell of the present invention, mass production is facilitated and the yield is high as compared with the conventional art.
According to the semi-finished solar cell substrate, compared with the prior art, the semi-finished solar cell substrate can be effectively stripped during the manufacture of the solar cell, and the manufacture efficiency is improved.
Drawings
Fig. 1 is a perspective view schematically showing a solar cell according to embodiment 1 of the present invention.
Fig. 2 is a cross-sectional view a-a of the solar cell of fig. 1, with hatching omitted for ease of understanding.
Fig. 3 is an explanatory view of the solar cell of fig. 1, and is an exploded perspective view of the solar cell being exploded into a 1 st electrode layer and a 2 nd electrode layer.
Fig. 4 is an explanatory view of the method for manufacturing the solar cell of fig. 1, wherein (a) is a sectional view in the step of forming the 1 st intrinsic semiconductor layer, and (b) is a sectional view in the step of forming the 1 st semiconductor layer. Only the layers formed in the respective steps are shown by hatching, and the remaining hatching is omitted.
Fig. 5 is an explanatory view of the steps in fig. 4 following the method for manufacturing the solar cell in fig. 1, wherein (a) is a sectional view in the release layer forming step, (b) is a sectional view in the 1 st protective layer forming step, and (c) is a sectional view in the 2 nd protective layer forming step. Only the layers formed in the respective steps are shown by hatching, and the remaining hatching is omitted.
Fig. 6 is an explanatory view of the steps in fig. 5 following the method for manufacturing the solar cell in fig. 1, wherein (a) is a sectional view in the resist layer forming step, (b) is a sectional view in the etching step, and (c) is a sectional view in the resist layer removing step. Only the layers formed in the respective steps are shown by hatching, and the remaining hatching is omitted.
Fig. 7 is an explanatory view of the steps in fig. 6 following the method for manufacturing the solar cell in fig. 1, wherein (a) is a sectional view in the step of forming the 2 nd intrinsic semiconductor layer, (b) is a sectional view in the step of forming the 2 nd semiconductor layer, and (c) is a sectional view in the peeling step. Only the layers formed in the respective steps are shown by hatching, and the remaining hatching is omitted.
Fig. 8 is an explanatory view of the steps in fig. 7 following the method for manufacturing the solar cell in fig. 1, wherein (a) is a sectional view in the antireflection layer forming step, (b) is a sectional view in the transparent electrode layer forming step, and (c) is a sectional view in the metal electrode layer forming step. Only the layers formed in the respective steps are shown by hatching, and the remaining hatching is omitted.
Fig. 9 is an explanatory view of a tray used for measurement of examples and comparative examples of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail. The front surface and the back surface are defined as the light receiving surface side and the opposite side.
The solar cell 1 according to embodiment 1 of the present invention is a back contact type solar cell, and as shown in fig. 1, the pair of electrode layers 2 and 3 are formed on the back surface side main surface 26 (1 st main surface) side of the semiconductor substrate 5 as a support substrate, and the electrode layers 2 and 3 are not formed on the front surface side main surface 25 (2 nd main surface) side. The solar cell 1 of the present embodiment may be an hit (heterojunction with intrinsic thin) type solar cell.
In the solar cell 1, as shown in fig. 1, the 1 st intrinsic semiconductor layer 6 and the antireflection layer 7 are stacked in this order on the front side main surface 25 side of the semiconductor substrate 5.
In the solar cell 1, the 2 nd intrinsic semiconductor layer 10 (the 2 nd intrinsic layer), the one conductivity type semiconductor layer 11, and the 1 st electrode layer 2 are sequentially stacked on a portion of the semiconductor substrate 5 on the back side main surface 26 side, and the 3 rd intrinsic semiconductor layer 15 (the 1 st intrinsic layer), the reverse conductivity type semiconductor layer 16, and the 2 nd electrode layer 3 are sequentially stacked on the other portion of the semiconductor substrate 5 on the back side main surface 26 side.
In the solar cell 1, as shown in fig. 2, the 2 nd intrinsic semiconductor layer 10 is interposed between the one-conductivity-type semiconductor layer 11 and the reverse-conductivity-type semiconductor layer 16 in the longitudinal direction Y.
As shown in fig. 1, the solar cell 1 is substantially quadrangular and has four sides perpendicular to each other. That is, the solar cell 1 includes lateral sides extending in the lateral direction X and vertical sides extending in the vertical direction Y.
As shown in fig. 3, the electrode layers 2 and 3 are collectors for taking out electricity from the semiconductor layers 11 and 16, and are comb-shaped in a rear view, and are embedded in each other.
That is, the 1 st electrode layer 2 includes a 1 st bus electrode portion 40 and a 1 st finger electrode portion 41, and the 1 st finger electrode portion 41 extends from the 1 st bus electrode portion 40 in a direction perpendicular to the 1 st bus electrode portion 40.
Similarly, the 2 nd electrode layer 3 includes a 2 nd bus electrode portion 45 and a 2 nd finger electrode portion 46, and the 2 nd finger electrode portion 46 extends from the 2 nd bus electrode portion 45 in a direction perpendicular to the 2 nd bus electrode portion 45.
The bus bar electrode portions 40 and 45 extend in the longitudinal direction Y along the longitudinal sides and are parallel to the transverse direction X when they are viewed from the rear.
The finger electrode portions 41 and 46 are embedded in each other and extend in the lateral direction X.
That is, the 1 st finger electrode portion 41 extends linearly in the transverse direction X from the 1 st bus electrode portion 40 toward the 2 nd bus electrode portion 45, and the 2 nd finger electrode portion 46 extends linearly in the transverse direction X from the 2 nd bus electrode portion 45 toward the 1 st bus electrode portion 40. The finger electrode portions 41 and 46 are alternately arranged in the longitudinal direction Y.
As shown in fig. 2, the electrode layers 2 and 3 have a multilayer structure in which transparent electrode layers 20 and 21 and metal electrode layers 22 and 23 are stacked in this order from the semiconductor substrate 5 side. The electrode layers 2 and 3 may have a single-layer structure including only the metal electrode layers 22 and 23, or may have a single-layer structure including only the transparent electrode layers 20 and 21.
As shown in fig. 3, the semiconductor layers 11 and 16 serve as bases for the electrode layers 2 and 3, and are both comb-shaped and embedded in each other in the rear view, as in the case of the electrode layers 2 and 3.
In a back view, a meandering separation groove 35 is formed between the one-conductivity type semiconductor layer 11 and the reverse-conductivity type semiconductor layer 16, and the 2 nd intrinsic semiconductor layer 10 as a base of the one-conductivity type semiconductor layer 11 is filled in the separation groove 35. That is, the one-conductivity-type semiconductor layer 11 and the reverse-conductivity-type semiconductor layer 16 are electrically insulated from each other by the 2 nd intrinsic semiconductor layer 10 in the expansion direction of the semiconductor substrate 5.
The 2 nd intrinsic semiconductor layer 10 is exposed in the thickness direction (the direction perpendicular to the rear surface side main surface 26 of the semiconductor substrate 5) from between the one conductivity type semiconductor layer 11 and the reverse conductivity type semiconductor layer 16. That is, the one-conductivity-type semiconductor layer 11 does not overlap the reverse-conductivity-type semiconductor layer 16 in the thickness direction of the semiconductor substrate 5, and the reverse-conductivity-type semiconductor layer 16 does not overlap the one-conductivity-type semiconductor layer 11.
Next, a method for manufacturing the solar cell 1 of the present embodiment will be described. Note that, the same contents as those of the related art will be omitted.
The solar cell 1 of the present embodiment is manufactured at one or more manufacturing points.
The solar cell 1 of the present embodiment is manufactured through the 1 st and 2 nd semi-finished solar cell substrates 99 and 100.
First, as shown in fig. 4(a), the 1 st intrinsic semiconductor layer 6 is formed on the front-side main surface 25 of the semiconductor substrate 5, and the 3 rd intrinsic semiconductor layer 15 is formed on the rear-side main surface 26, using a plasma CVD apparatus (1 st intrinsic semiconductor forming step).
Next, as shown in fig. 4 b, the reverse conductivity type semiconductor layer 16 is formed on the 3 rd intrinsic semiconductor layer 15 by using the same or different plasma CVD apparatus as in the above-described step (1 st semiconductor layer forming step).
Next, as shown in fig. 5 a, a first reaction gas is blown onto the reverse conductivity type semiconductor layer 16 by using a plasma CVD apparatus which is the same as or different from the above-described step to form a peeling layer 50 (peeling layer forming step).
The thickness of the release layer 50 formed in the release layer forming step is preferably 10nm to 150 nm.
Within this range, the resin composition can be easily impregnated with a stripping etchant, which will be described later, and can be easily stripped.
In addition, as the film forming conditions in this case, the following conditions are preferably satisfied.
The substrate temperature (film forming temperature) is 150 ℃ or lower, preferably 100 to 140 ℃.
The pressure is preferably 180Pa to 220 Pa.
The power density is preferably 0.01W/cm2～1.00W/cm2。
The composition of the 1 st reaction gas is preferably: containing silane gas (SiH)4) Carbon dioxide (CO)2)，CO2And SiH4Flow rate ratio (SiH)4CO when the flow rate of (2) is 12The flow ratio) of 10 to 400.
The peeling layer 50 is preferably formed so as to overlap with the entire reverse conductivity type semiconductor layer 16 in a plan view of the semiconductor substrate 5.
The peeling layer 50 is preferably formed in a range of 90% or more of the area of the semiconductor substrate 5 when the semiconductor substrate 5 is viewed in plan.
Next, as shown in fig. 5(b), in succession to the peeling layer forming step, a 2 nd reaction gas is blown onto the peeling layer 50 in the film forming chamber of the same plasma CVD apparatus to form a 1 st protective layer 51 (1 st protective layer forming step).
The thickness of the 1 st protective layer 51 formed in the 1 st protective layer forming step is larger than the thickness of the release layer 50, and is preferably 200nm to 400 nm.
Within this range, the resist removing solution described later can be prevented from dissolving the peeling layer 50.
In addition, as the film forming conditions in this case, the following conditions are preferably satisfied.
The substrate temperature (film forming temperature) is 150 ℃ or lower, preferably 100 to 140 ℃.
The film formation temperature at the time of forming the 1 st protective layer 51 is preferably substantially equal to or higher than the film formation temperature of the release layer 50.
The temperature difference between the film formation temperature of the 1 st protective layer 51 and the film formation temperature of the release layer 50 is preferably 50 ℃ or less, more preferably 20 ℃ or less, and particularly preferably 5 ℃ or less.
If the temperature is within this range, the temperature can be rapidly raised, and therefore, continuous deposition can be performed in the same deposition chamber of the plasma CVD apparatus.
The pressure is preferably 180Pa to 220 Pa.
The power density is preferably 0.01W/cm2～1.00W/cm2。
The 2 nd reaction gas is preferably: containing silane gas (SiH)4) Carbon dioxide (CO)2) And hydrogen (H)2)，CO2And SiH4Flow rate ratio (SiH)4CO at 12Flow ratio of) 1 to 100, H2And SiH4Flow rate ratio (SiH)4H when set to 12The flow ratio) of 50 to 300.
If it is within this range, a dense 1 st protective layer 51 can be formed.
The 1 st protective layer 51 is preferably formed so as to overlap the entire peeling layer 50 in a plan view of the semiconductor substrate 5.
The 1 st protective layer 51 is preferably formed over 90% or more of the area of the semiconductor substrate 5 in a plan view of the semiconductor substrate 5.
Next, as shown in fig. 5 c, in succession to the peeling layer forming step, a 3 rd reaction gas is blown onto the 1 st intrinsic semiconductor layer 6 in the film forming chamber of the same plasma CVD apparatus to form a 2 nd protective layer 52 (2 nd protective layer forming step).
That is, in the 2 nd protective layer forming step, the 2 nd protective layer 52 is formed on the outermost surface on the front surface side, and the 1 st semi-finished solar cell substrate 99 is formed.
The thickness of the 2 nd protective layer 52 formed in the 2 nd protective layer forming step is larger than the thickness of the release layer 50, and is preferably 10nm to 200 nm.
In addition, as the film forming conditions in this case, the following conditions are preferably satisfied.
The substrate temperature (film forming temperature) is 150 ℃ or lower, preferably 100 to 140 ℃.
The film formation temperature at the time of forming the 2 nd protective layer 52 is preferably substantially equal to or higher than the film formation temperature of the release layer 50.
The temperature difference between the deposition temperature at the time of depositing the 2 nd protective layer 52 and the deposition temperature at the time of depositing the 1 st protective layer 51 is preferably 50 ℃ or less, more preferably 20 ℃ or less, and particularly preferably 5 ℃ or less.
If the temperature is within this range, the temperature can be quickly adjusted, and therefore, continuous deposition can be performed in the deposition chamber of the same plasma CVD apparatus.
The pressure is preferably 180Pa to 220 Pa.
The power density is preferably 0.01W/cm2～1.00W/cm2。
The 3 rd reaction gas is preferably: containing silane gas (SiH)4) Carbon dioxide (CO)2) And hydrogen (H)2)，CO2And SiH4Flow rate ratio (SiH)4CO at 12Flow ratio of (1) to (400), H2And SiH4Flow rate ratio (SiH)4H when set to 12The flow rate ratio) is more than 0 and 300 or less.
The 2 nd protective layer 52 is preferably formed over a range of 90% or more of the area of the semiconductor substrate 5 in a plan view of the semiconductor substrate 5.
Then, the 1 st semi-finished solar cell substrate 99 is moved to another place (for example, another building or another room) as necessary, and as shown in fig. 6(a), a liquid resist material patterned in a comb shape is applied to the 1 st protective layer 51 of the 1 st semi-finished solar cell substrate 99 by screen printing or the like, a liquid resist material is applied to the 2 nd protective layer 52, and the substrate having both surfaces coated with the resist material is subjected to heat treatment and dried to form the resist layers 55 and 56 (resist layer forming step).
At this time, on the 1 st protective layer 51, there are a portion (resist forming region 60) where the resist material is applied and the resist layer 55 is formed, and a portion (non-resist forming region 61) where the resist material is not applied and the resist layer 55 is not formed. That is, the substrate after the resist layer forming step includes an overlapping portion (resist forming region 60) where the resist layer 55 is overlapped on the reverse conductivity type semiconductor layer 16 and a non-overlapping portion (non-resist forming region 61) where the resist layer 55 is not overlapped in the thickness direction.
As shown in fig. 6 b, the substrate on which the resist layers 55 and 56 are formed is immersed in a resist etching solution (etching solution), and the 3 rd intrinsic semiconductor layer 15, the reverse conductivity type semiconductor layer 16, the peeling layer 50, and the 1 st protective layer 51 are removed from a part or all of the non-overlapping portion (non-resist forming region 61) where the resist layer 55 is not formed (etching step).
As the etching liquid for the resist used at this time, for example, a mixed solution of hydrofluoric acid and nitric acid (fluoronitric acid), a solution containing ozone and hydrofluoric acid, or the like can be used.
At this time, a peeled region 62 where the layer on the rear surface side main surface 26 side is peeled is formed on the non-resist forming region 61 in the semiconductor substrate 5.
As shown in fig. 6 c, the resist layers 55 and 56 are removed using a resist removing solution, and the substrate is cleaned with hydrofluoric acid as necessary (resist layer removing step).
At this time, since the peeling layer 50 is protected by the 1 st protective layer 51, it is not substantially dissolved, and only the resist layers 55 and 56 are peeled. Further, even when the substrate is cleaned with hydrofluoric acid, the release layer 50 is not substantially dissolved.
Next, as shown in fig. 7 a, the 2 nd intrinsic semiconductor layer 10 is formed on the entire back-side main surface by using a plasma CVD apparatus (2 nd intrinsic semiconductor layer forming step).
That is, in the 2 nd intrinsic semiconductor layer forming step, the 2 nd intrinsic semiconductor layer 10 is formed outside the exfoliation layer 50 with respect to the semiconductor substrate 5 so as to overlap with the exfoliation layer 50 in a plan view of the semiconductor substrate 5.
At this time, as shown in fig. 7(a), the 2 nd intrinsic semiconductor layer 10 is partially formed from the 1 st protective layer 51a (51) across the peeling region 62a (62) of the adjacent semiconductor substrate 5, and partially formed from the peeling region 62a across the adjacent 1 st protective layer 51 b.
As shown in fig. 7(b), a semiconductor layer 11 of one conductivity type is formed on the intrinsic semiconductor layer 10 of the 2 nd conductivity type by using the same or a different plasma CVD apparatus, thereby forming a semi-finished solar cell substrate 100 of the 2 nd conductivity type (the 2 nd semiconductor layer forming step).
That is, in the 2 nd semiconductor layer forming step, the one-conductivity-type semiconductor layer 11 is formed outside the 2 nd intrinsic semiconductor layer 10 with respect to the semiconductor substrate 5 so as to overlap with the exfoliation layer 50 in a plan view of the semiconductor substrate 5.
The 2 nd semi-finished solar cell substrate 100 is moved to another place (for example, another building or another room) as necessary, and the 2 nd semi-finished solar cell substrate 100 is immersed in an etching solution for peeling (peeling solution), and as shown in fig. 7(c), the peeling layer 50 is dissolved and peeled off, and the layer on the peeling layer 50 is removed (peeling step).
As the etching liquid for stripping used in the stripping step, for example, hydrofluoric acid or the like can be used.
At this time, in the 2 nd semi-finished solar cell substrate 100, all the layers in contact with the peeling layer 50 are dissolved or peeled off on the back side main surface 26 side of the semiconductor substrate 5, and the 2 nd protective layer 52 is also dissolved or peeled off from the 1 st intrinsic semiconductor layer 6 on the front side main surface 25 side of the semiconductor substrate 5.
In this case, the 2 nd intrinsic semiconductor layer 10 is left only in the portion inside the peeling layer 50, and does not cover the reverse conductivity type semiconductor layer 16 with respect to the semiconductor substrate 5.
The 2 nd intrinsic semiconductor layer 10 is located on the same plane as or inside the outer side surface of the reverse conductive semiconductor layer 16 with respect to the semiconductor substrate 5.
At this time, the stripping layer 50 is etched by the stripping etchant at a higher etching rate than the one-conductivity-type semiconductor layer 11.
In addition, the 2 nd protective layer 52 has an etching rate faster than that of the 1 st intrinsic semiconductor layer 6.
As shown in fig. 8 a, an anti-reflection layer 7 is formed on the 1 st intrinsic semiconductor layer 6 by using a plasma CVD apparatus (anti-reflection layer forming step).
The reaction gas used in the antireflective layer forming step preferably contains silane gas (SiH)4) Ammonia (NH)3)。
Next, the electrode layers 2 and 3 are formed on the one-conductivity-type semiconductor layer 11 and the reverse-conductivity-type semiconductor layer 16.
Specifically, as shown in fig. 8 b, first, transparent electrode layers 20 and 21 are formed on the first conductivity type semiconductor layer 11 and the reverse conductivity type semiconductor layer 16 (transparent electrode layer forming step).
In the transparent electrode layer forming step, the transparent electrode layers 20 and 21 are patterned by a photoresist method, a mask method, or the like, and the transparent electrode layer 20 is formed only on the one conductivity type semiconductor layer 11 and the transparent electrode layer 21 is formed only on the reverse conductivity type semiconductor layer 16. That is, the transparent electrode layer 20 does not extend over the reverse conductivity type semiconductor layer 16, and the transparent electrode layer 21 does not extend over the one conductivity type semiconductor layer 11.
Next, as shown in fig. 8 c, metal electrode layers 22 and 23 are formed on the transparent electrode layers 20 and 21 by screen printing or the like (metal electrode layer forming step).
In the metal electrode layer forming step, the metal electrode layer 22 is formed only on the transparent electrode layer 20 and the metal electrode layer 23 is formed only on the transparent electrode layer 21 by a photoresist method, a mask method, or the like. The transparent electrode layer 21 and the metal electrode layer 22 may be patterned at the same time.
Then, wiring members such as interconnectors are mounted on the electrode layers 2 and 3 as necessary, thereby completing the solar cell 1.
Next, the detailed configuration of each part constituting the solar cell 1 will be described.
The semiconductor substrate 5 is a semiconductor substrate having one of n-type and p-type conductivity.
The semiconductor substrate 5 of the present embodiment is a one-conductivity-type semiconductor substrate having the same conductivity type as the one-conductivity-type semiconductor layer 11, specifically, an n-type single crystal silicon substrate.
The average thickness of the semiconductor substrate 5 is preferably 120 to 250 μm, and more preferably 160 to 200 μm.
The semiconductor substrate 5 may have a textured structure on the front-side main surface 25 and/or the back-side main surface 26, as necessary.
The intrinsic semiconductor layers 6, 10, and 15 are layers whose surfaces are passivated by suppressing diffusion of impurities into the semiconductor substrate 5. The intrinsic semiconductor layers 6, 10, and 15 are i-type semiconductor layers and substantially contain no conductive impurities.
The phrase "substantially free of conductive impurities" as used herein includes not only the case where the conductive impurities such as n-type impurities and p-type impurities are not contained at all, but also the case where a trace amount of conductive impurities is contained within a range where the function of the intrinsic layer can be maintained.
The intrinsic semiconductor layers 6, 10, and 15 are not particularly limited as long as they suppress diffusion of impurities into the semiconductor substrate 5 and have a function of performing passivation on the surface. The intrinsic semiconductor layers 6, 10, and 15 may be, for example, amorphous silicon semiconductor layers or hydrogenated amorphous silicon semiconductor layers.
The average thickness of the intrinsic semiconductor layers 6, 10, 15 is preferably 2nm to 20nm, more preferably 5nm to 10 nm. Within this range, the semiconductor device can function well as a passivation layer for the semiconductor substrate 5 and can suppress the resistance to be low.
The one-conductivity-type semiconductor layer 11 is a semiconductor layer having n-type or p-type conductivity, and is a semiconductor layer having the same conductivity as the semiconductor substrate 5.
The one-conductivity-type semiconductor layer 11 of the present embodiment is an n-type semiconductor layer, specifically, an n-type amorphous silicon layer, in which an n-type dopant (phosphorus or the like) is added to the same semiconductor as the intrinsic semiconductor layers 6, 10, and 15.
The average thickness of the one-conductivity type semiconductor layer 11 is preferably 2nm to 20nm, more preferably 5nm to 15 nm.
The reverse conductivity type semiconductor layer 16 is a semiconductor layer having an n-type or p-type conductivity type, and is a semiconductor layer having a conductivity type different from that of the semiconductor substrate 5 and the one conductivity type semiconductor layer 11.
The reverse conductivity type semiconductor layer 16 of the present embodiment is a p-type semiconductor layer, specifically, a p-type amorphous silicon layer, in which a p-type dopant (boron or the like) is added to the same semiconductor as the intrinsic semiconductor layers 6, 10, and 15.
The average thickness of the reverse conductivity type semiconductor layer 16 is preferably 2nm to 20nm, more preferably 5nm to 15 nm.
The anti-reflection layer 7 is a low-reflection layer having light transmittance and suppressing reflection of light.
The antireflection layer 7 may be formed of, for example, a metal oxide such as silicon oxide, zinc oxide, or titanium oxide, a metal nitride such as silicon nitride, or the like.
The anti-reflection layer 7 is preferably formed of silicon nitride from the viewpoint of the light confinement effect of incident light.
The transparent electrode layers 20 and 21 may be formed of a transparent conductive oxide such as zinc oxide, Indium Tin Oxide (ITO), titanium oxide, tin oxide, tungsten oxide, or molybdenum oxide.
The average thickness of the transparent electrode layers 20 and 21 is preferably 20nm to 200nm, and more preferably 50nm to 150 nm.
The metal electrode layers 22 and 23 have a resistivity smaller than that of the transparent electrode layers 20 and 21, and function as auxiliary electrode layers of the transparent electrode layers 20 and 21.
The metal electrode layers 22 and 23 may be formed of a metal such as gold, silver, copper, platinum, aluminum, nickel, palladium, or an alloy containing these metals.
The average thickness of the metal electrode layers 22 and 23 is preferably 1 to 80 μm.
Next, the detailed structure of each part constituting the semi-finished solar cell substrates 99 and 100 will be described. Note that, description of the configuration に overlapping with the solar cell 1 will be omitted.
The release layer 50 is a layer dissolved in a release etchant.
The peeling layer 50 preferably contains silicon nitride or silicon oxide as a main component, and preferably contains silicon nitride or silicon oxide in an amount of 90% or more of the total component. The peeling layer 50 of the present embodiment is a silicon oxide layer containing silicon oxide as a main component.
When a silicon oxide layer is used as the peeling layer 50, the refractive index is preferably 1.42 to 1.50.
The "refractive index" referred to herein means a refractive index when 550nm of light is irradiated.
If the amount is within this range, the etching rate of the etching solution for stripping increases, and the etching solution is easily stripped.
When a silicon oxide layer is used as the release layer 50, the etching rate when immersed in 2 wt% hydrofluoric acid is preferably 3nm/s or more, more preferably 5nm/s or more, and still more preferably 7nm/s or more.
The 1 st protective layer 51 is a layer for protecting the peeling layer 50 from the etching solution for resist and hydrofluoric acid used for cleaning before the 2 nd intrinsic semiconductor layer forming step. The 1 st protective layer 51 preferably contains silicon nitride or silicon oxide as a main component, and preferably contains silicon nitride or silicon oxide in an amount of 90% or more of the total composition.
The 1 st protective layer 51 of this embodiment is a silicon oxide layer containing silicon oxide as a main component, similarly to the peeling layer 50.
The refractive index in the case of using a silicon oxide layer as the 1 st protective layer 51 is higher than that of the peeling layer 50, and preferably exceeds 1.50.
If the amount is within this range, the etching rate of the etching solution for resists and hydrofluoric acid is low and the solutions are not easily dissolved.
The 2 nd protective layer 52 has resistance to the resist etchant and the stripping etchant compared to the stripping layer 50, and protects the 1 st intrinsic semiconductor layer 6 from the resist etchant and the stripping etchant.
The 2 nd protective layer 52 preferably contains silicon nitride or silicon oxide as a main component, and preferably contains silicon nitride or silicon oxide in an amount of 90% or more of the total composition.
The 2 nd protective layer 52 of the present embodiment is a silicon oxide layer containing silicon oxide as a main component, similarly to the peeling layer 50 and the 1 st protective layer 51.
The refractive index in the case of using a silicon oxide layer as the 2 nd protective layer 52 is higher than that of the peeling layer 50, and preferably exceeds 1.50.
According to the method of manufacturing the solar cell 1 of the present embodiment, the one-conductivity-type semiconductor layer 11 is formed so that a part thereof overlaps the peeling layer 50, and the peeling layer 50 is dissolved in the peeling solution, so that the one-conductivity-type semiconductor layer 11 on the peeling layer 50 can be removed, and patterning of the one-conductivity-type semiconductor layer 11 can be performed. Therefore, the method can be manufactured at low cost as compared with the conventional method of patterning with a photoresist.
According to the method for manufacturing the solar cell 1 of the present embodiment, since the peeling layer 50 can be formed at the film forming temperature of 150 ℃. Therefore, mass production can be achieved.
According to the method of manufacturing the solar cell 1 of the present embodiment, the density of the 1 st protective layer 51 is higher than that of the peeling layer 50, and the resistance to the resist etchant is also higher. Therefore, in the etching step, when the peeling layer 50 is immersed in the etching solution for resist, the peeling layer 50 is less likely to be dissolved than in the case where the peeling layer 50 is immersed directly in the etching solution for resist, and the peeling of the layer on the outer side of the peeling layer 50 due to the dissolution of the peeling layer 50 by the etching solution can be prevented.
According to the method of manufacturing the solar cell 1 of the present embodiment, the resist layer 55 patterned in the comb shape is formed on the 1 st protective layer 51, and when the semiconductor substrate 5 is viewed in plan, a portion not overlapping with the resist layer 55 of the reverse conductivity type semiconductor layer 16 is dissolved and removed with the resist etchant, and patterning is performed. Therefore, even if a mask or the like is not provided at the time of forming the reverse conductivity type semiconductor layer 16, the reverse conductivity type semiconductor layer 16 can be patterned.
According to the method for manufacturing the solar cell 1 of the present embodiment, in the protective layer forming step, the 1 st protective layer 51 containing silicon oxide as a main component is formed by blowing the 2 nd reaction gas containing silane gas, carbon dioxide, and hydrogen gas at a temperature of 150 ℃. That is, since the 2 nd reaction gas diluted with hydrogen is blown at a low concentration to form a film at a low temperature, the 1 st protective layer 51 can be formed densely.
According to the method for manufacturing the solar cell 1 of the present embodiment, the temperature difference between the film formation temperature of the release layer 50 in the release layer forming step and the film formation temperature of the 1 st protective layer 51 in the 1 st protective layer forming step is 50 ℃ or less. Therefore, the release layer 50 and the 1 st protective layer 51 can be continuously formed by quickly adjusting the temperature.
Further, since the temperature difference between the deposition temperature of the 1 st protective layer 51 in the 1 st protective layer forming step and the deposition temperature of the 2 nd protective layer 52 in the 2 nd protective layer forming step is 50 ℃ or less, temperature adjustment can be performed quickly, and deposition of the 1 st protective layer 51 and the 2 nd protective layer 52 can be performed continuously.
According to the semi-finished solar cell substrates 99 and 100 of the present embodiment, since the peeling layer 50 contains silicon oxide as a main component and has an etching rate of 5nm/s or more when immersed in 2 wt% hydrofluoric acid, the peeling layer 50 can be peeled off quickly.
According to the semi-finished solar cell substrate 100 of the 2 nd embodiment, the exfoliation layer 50 is dissolved by immersing in the exfoliation removal solution, and when the semiconductor substrate 5 is viewed in plan, the portion overlapping with the exfoliation layer 50 of the one-conductivity type semiconductor layer 11 can be removed, and the exfoliation layer 50 contains silicon oxide as a main component and has a refractive index of 1.42 to 1.50. Therefore, the etching rate can be increased at the time of peeling, and the one conductivity type semiconductor layer 11 can be easily patterned.
According to the 2 nd semi-finished solar cell substrate 100 of the present embodiment, the outermost surface of the semiconductor substrate 5 on the front side main surface 25 side is covered with the 2 nd protective layer 52, and the 2 nd protective layer 52 has a stronger resistance to the stripping solution than the stripping layer 50. Therefore, damage to each layer on the 2 nd main surface side of the semiconductor substrate 5 due to the stripping liquid in the etching step can be suppressed.
According to the solar cell 1 of the present embodiment, the first conductivity type semiconductor layer 11 and the reverse conductivity type semiconductor layer 16 do not overlap in the thickness direction, and the intrinsic semiconductor layers 10 and 15 can prevent contact between the electrode layers 2 and 3 and the semiconductor layers 11 and 16 having different conductivity types, and therefore, a solar cell having excellent safety can be obtained.
In the above embodiment, the reverse conductivity type semiconductor layer 16 is a p-type semiconductor layer, and the first conductivity type semiconductor layer 11 is an n-type semiconductor layer, but the present invention is not limited thereto. The reverse conductive type semiconductor layer 16 may be an n-type semiconductor layer, and the one conductive type semiconductor layer 11 may be a p-type semiconductor layer.
In the above embodiment, the semiconductor substrate 5 is an n-type semiconductor substrate, but the present invention is not limited thereto. The semiconductor substrate 5 may be a p-type semiconductor substrate.
In the above embodiment, the peeling layer 50, the 1 st protective layer 51, and the 2 nd protective layer 52 were formed in the same film forming chamber of the plasma CVD apparatus, but the present invention is not limited thereto. The film formation may be performed in a different film forming chamber.
In the above embodiment, the 1 st protective layer 51 and the 2 nd protective layer 52 are formed in different steps, but the present invention is not limited thereto. The 1 st protective layer 51 and the 2 nd protective layer 52 may be formed simultaneously.
In the above embodiment, the release layer 50 and the 1 st protective layer 51 may be formed of the same material, but the present invention is not limited thereto. The peeling layer 50 and the 1 st protective layer 51 may be formed of different materials.
In the above embodiment, the peeling layer 50, the 1 st protective layer 51, and the 2 nd protective layer 52 are each formed of a silicon oxide layer, but the present invention is not limited thereto. The separation layer 50, the 1 st protective layer 51, and the 2 nd protective layer 52 may be formed of a silicon nitride layer containing silicon nitride as a main component.
In the above embodiment, the release layer 50 is formed as one layer, but the present invention is not limited thereto. The release layer 50 may be formed of a laminate of a plurality of layers.
In the above embodiment, the 1 st protective layer 51 and the 2 nd protective layer 52 are formed as one layer, but the present invention is not limited thereto. The 1 st protective layer 51 and the 2 nd protective layer 52 may be formed of a laminate of a plurality of layers.
In the above embodiments, each constituent member may be freely substituted or added between the embodiments as long as the constituent member is included in the technical scope of the present invention.
Examples
The present invention will be described in detail with reference to examples. The present invention is not limited to the following examples, and can be implemented with appropriate modifications within a scope not changing the gist of the present invention.
(example 1)
First, as shown in fig. 9, 30 pieces (nos. 1 to 30 shown in fig. 9) of mirror-polished silicon wafers (longitudinal and transverse 156.75mm) each having a length of 5 pieces and a width of 6 pieces were arranged in a vertical and horizontal checkerboard shape on a pallet having a length of 998mm and a width of 1200mm, and a silicon oxide layer was formed on these silicon wafers by using a plasma CVD apparatus. This was defined as example 1.
The conditions for forming the silicon oxide layer in example 1 were as follows: substrate temperature 100 ℃, distance 10mm from electrode to substrate, pressure 200Pa, gas flow rate ratio SiH4：CO2Is 25: 4900. the power density is 0.22W/cm2。
(example 2)
Example 2 was performed in the same manner as example 1 except that the substrate temperature was set to 140 ℃.
Comparative example 1
Comparative example 1 was prepared in the same manner as in example 1, except that the substrate temperature was set to 180 ℃.
(example 3)
A silicon oxide layer was formed on a mirror-polished silicon wafer set on a tray similar to that of example 1 using a plasma CVD apparatus, and this was defined as example 3.
Film formation of silicon oxide layer in example 3The conditions were: substrate temperature 140 ℃, distance from electrode to substrate 10mm, pressure 200Pa, gas flow rate ratio SiH4：CO2：H2Is 150: 4900: 9800. the power density is 0.37W/cm2. Namely, the film is formed by diluting with hydrogen gas.
Comparative example 2
Comparative example 2 was prepared in the same manner as in example 3, except that the dilution with hydrogen gas was not performed. That is, in comparative example 2, the gas flow rate ratio SiH4：CO2Is 150: 4900A film is formed.
The refractive index of the silicon oxide on the silicon wafer when irradiated with light of 550nm was measured for examples 1 to 3 and comparative examples 1 and 2 using an ellipsometer manufactured by j.a. woollam. Thereafter, the silicon oxide layer was dissolved in 2 wt% hydrofluoric acid, and the refractive index at 550nm of light irradiation was measured again with an ellipsometer to calculate the etching rate. In each of silicon wafers nos. 1 to 30 mounted on the tray, the in-plane distribution was calculated from the difference between the thickest film thickness (maximum film thickness Max) and the thinnest film thickness (minimum film thickness Min) of the silicon oxide layer on the silicon wafer using the following formula (1).
{(Max-Min)/Min}×100···(1)
In addition, as the evaluation of the peelability, the degree of peeling of the silicon oxide layer when rinsed with the rinse solution was evaluated by immersing the silicon oxide layer in the etching solution for 15 minutes. Specifically, the degree of peeling was evaluated as B when the peeling was 50% or more and less than 90% by visual observation, and as a when the peeling was 90% or more.
The measurement results of examples 1, 2 and 3 and comparative examples 1 and 2 are shown in tables 1 and 2.
[ Table 1]
Figure BDA0003280023410000201
[ Table 2]
Figure BDA0003280023410000202
As shown in table 1, in examples 1 and 2 formed at a low temperature, the etching rate was higher at a lower temperature than in comparative example 1 formed at a high temperature.
In this case, the silicon oxide layers of examples 1 and 2 can be formed to have a uniform thickness even when the film is formed on a tray having an in-plane distribution of 10% or less and a large area.
It is also found that the peeling properties of examples 1 and 2 are good at 50% or more, and particularly the peeling properties of example 1 are still good as compared with example 2.
As shown in table 2, the silicon oxide layer of example 3 in which hydrogen was diluted had a lower etching rate and was less soluble in hydrofluoric acid than comparative example 2 in which hydrogen was not diluted.
As shown in tables 1 and 2, the etching rate of the silicon oxide layer of example 1 was about 9 times as high as that of example 3, and the etching rate of the silicon oxide layer of example 2 was about 6 times as high as that of example 3.
From this result, it is understood that the silicon oxide layers of examples 1 and 2 are much more easily dissolved by hydrofluoric acid than the silicon oxide layer of example 3.
From the above results, it was found that by performing deposition with the substrate temperature being 140 ℃ or lower, a silicon oxide layer having a uniform in-plane distribution and controlled at a desired etching rate can be formed even in a large-area deposition apparatus.
It is also known that when the same deposition conditions are set except for the substrate temperature, a silicon oxide layer having a low refractive index and a high etching rate can be deposited by performing deposition at a substrate temperature of 140 ℃.
It is also known that a dense silicon oxide layer can be formed even when the substrate temperature is 140 ℃ or lower by diluting the source gas with hydrogen.
From the above, it is also known that the silicon oxide layer of example 1 or example 2 is used as the release layer, and the silicon oxide layer of example 3 is used as the protective layer, whereby the same plasma CVD apparatus can be used for continuous film formation.
Description of the reference numerals
1 solar cell
2 st electrode layer
3 the 2 nd electrode layer
5 semiconductor substrate
6 th intrinsic semiconductor layer
10 the 2 nd intrinsic semiconductor layer (intrinsic semiconductor layer, 2 nd intrinsic layer)
11 a conductive semiconductor layer
15 the 3 rd intrinsic semiconductor layer (intrinsic semiconductor layer, 1 st intrinsic layer)
16 reverse conductive semiconductor layer
25 front surface (2 nd main surface)
26 rear side principal surface (1 st principal surface)
50 peeling layer
51 st protective layer
52 nd protective layer
55. 56 resist layer
60 resist formation region
61 non-resist forming region
62 peeling area
99 st 1 semi-finished solar cell substrate
100 nd 2 nd semi-finished solar cell substrate

Claims (15)

1. A method for manufacturing a solar cell, the solar cell comprising a semiconductor layer of one conductivity type, a semiconductor layer of an inverse conductivity type, a 1 st electrode layer and a 2 nd electrode layer on a 1 st main surface side of a semiconductor substrate, the semiconductor layer of the one conductivity type being interposed between the semiconductor substrate and the 1 st electrode layer, and the semiconductor layer of the inverse conductivity type being interposed between the semiconductor substrate and the 2 nd electrode layer;
the manufacturing method comprises the following steps:
a 1 st semiconductor layer forming step of forming the reverse conductivity type semiconductor layer on a 1 st main surface side of the semiconductor substrate,
a peeling layer forming step of forming a peeling layer containing silicon oxide or silicon nitride as a main component on the reverse conductivity type semiconductor layer,
a 2 nd semiconductor layer forming step of forming the one conductivity type semiconductor layer so that a part of the one conductivity type semiconductor layer and the peeling layer have an overlapping portion when the semiconductor substrate is viewed in plan, and
a peeling step of dissolving the peeling layer with a peeling solution to remove the overlapped portion of the one conductivity type semiconductor layer;
in the release layer forming step, a 1 st reaction gas is blown at a film forming temperature of 150 ℃ or lower to form the release layer.
2. The method for manufacturing a solar cell according to claim 1, comprising a protective layer forming step of forming a protective layer on the release layer,
the protective layer contains silicon oxide or silicon nitride as a main component, and has a density higher than that of the peeling layer.
3. The method for manufacturing a solar cell according to claim 1 or 2, comprising:
a resist layer forming step of forming a resist layer having a predetermined shape on the outer side of the reverse conductivity type semiconductor layer with respect to the semiconductor substrate,
an etching step of removing a part of the reverse conductive semiconductor layer with an etchant, and
a resist layer removing step of removing the resist layer;
in the resist layer forming step, a non-overlapping portion that does not overlap with the resist layer exists in the reverse conductivity type semiconductor layer when the semiconductor substrate is viewed in plan,
in the etching step, a part or all of the non-overlapping portion of the reverse conductivity type semiconductor layer is removed.
4. The method for manufacturing a solar cell according to any one of claims 1 to 3, comprising: a protective layer forming step of forming a protective layer containing silicon oxide as a main component on the peeling layer;
in the protective layer forming step, the protective layer is formed by blowing a 2 nd reaction gas at a temperature of 150 ℃ or lower,
the 2 nd reaction gas comprises silane gas, carbon dioxide and hydrogen gas.
5. The method for manufacturing a solar cell according to claim 4, wherein a flow ratio of hydrogen gas to silane gas in the 2 nd reaction gas is 50 or more.
6. The method for manufacturing a solar cell according to claim 4 or 5, wherein a film formation temperature of the protective layer in the protective layer forming step is substantially equal to or higher than a film formation temperature of the release layer in the release layer forming step, and a temperature difference from the film formation temperature of the release layer in the release layer forming step is 50 ℃ or lower.
7. A method for manufacturing a solar cell, the solar cell comprising a semiconductor layer of one conductivity type, a semiconductor layer of an inverse conductivity type, a 1 st electrode layer and a 2 nd electrode layer on a 1 st main surface side of a semiconductor substrate, the semiconductor layer of the one conductivity type being interposed between the semiconductor substrate and the 1 st electrode layer, and the semiconductor layer of the inverse conductivity type being interposed between the semiconductor substrate and the 2 nd electrode layer;
the manufacturing method comprises the following steps:
a 1 st semiconductor layer forming step of forming the reverse conductivity type semiconductor layer on a 1 st main surface side of the semiconductor substrate,
a peeling layer forming step of forming a peeling layer containing silicon oxide or silicon nitride as a main component on the reverse conductivity type semiconductor layer,
a protective layer forming step of forming a protective layer containing silicon oxide or silicon nitride as a main component and having a higher density than the peeling layer on the peeling layer,
a 2 nd semiconductor layer forming step of forming the one conductivity type semiconductor layer so as to have a portion overlapping with the peeling layer in a plan view of the semiconductor substrate, and
a peeling step of dissolving the peeling layer with a peeling solution to remove the overlapped portion of the one conductivity type semiconductor layer;
the peeling step is performed after the protective layer forming step,
in the protective layer forming step, the protective layer is formed by blowing a 2 nd reaction gas at a temperature of 150 ℃ or lower,
the 2 nd reaction gas contains silane gas, carbon dioxide and hydrogen, and the flow ratio of the hydrogen to the silane gas is more than 50.
8. A semi-finished solar cell substrate is provided with a one-conductivity type semiconductor layer and an inverse-conductivity type semiconductor layer on the 1 st main surface side of a semiconductor substrate,
a peeling layer provided on the outer side of the reverse conductive semiconductor layer with respect to the semiconductor substrate,
the peeling layer is formed by laminating the semiconductor layer of one conductivity type on the outer side of the semiconductor substrate,
the one-conductivity-type semiconductor layer has an overlapping portion with the peeling layer in a plan view of the semiconductor substrate,
the peeling layer can remove the overlapping portion of the one conductivity type semiconductor layer by being dissolved by being immersed in a peeling solution,
the peeling layer contains silicon oxide as a main component, and has an etching rate of 5nm/s or more when immersed in 2 wt% hydrofluoric acid.
9. The semi-finished solar cell substrate of claim 8, wherein there is a protective layer on the release layer,
the protective layer contains silicon oxide or silicon nitride as a main component, and has a density higher than that of the peeling layer.
10. The semi-finished solar cell substrate according to claim 8 or 9, wherein a protective layer is provided on the release layer,
the protective layer contains silicon oxide as a main component, and has a refractive index higher than that of the peeling layer.
11. A semi-finished solar cell substrate is provided with a conductive semiconductor layer on the 1 st main surface side of a semiconductor substrate,
a peeling layer and a protective layer are sequentially stacked on the outer side of the conductive semiconductor layer with respect to the semiconductor substrate,
the stripping layer contains silicon oxide as main component, and has an etching rate of 5nm/s or more when immersed in 2 wt% hydrofluoric acid,
the protective layer contains silicon oxide or silicon nitride as a main component, and has a density higher than that of the peeling layer.
12. The semi-finished solar cell substrate according to any one of claims 8 to 11, wherein an outermost surface on the 2 nd principal surface side of the semiconductor substrate is covered with a 2 nd protective layer, and an etching rate of the 2 nd protective layer when immersed in 2 wt% hydrofluoric acid is slower than that of the peeling layer.
13. A solar cell includes a semiconductor layer of one conductivity type, a semiconductor layer of an opposite conductivity type, a 1 st electrode layer, and a 2 nd electrode layer on a 1 st main surface side of a semiconductor substrate, the semiconductor layer of the one conductivity type being interposed between the semiconductor substrate and the 1 st electrode layer, and the semiconductor layer of the opposite conductivity type being interposed between the semiconductor substrate and the 2 nd electrode layer;
and, having an intrinsic semiconductor layer,
the intrinsic semiconductor layer is interposed between the semiconductor substrate and the one conductive type semiconductor layer and the reverse conductive type semiconductor layer, respectively, and is further interposed between the one conductive type semiconductor layer and the reverse conductive type semiconductor layer in the expanding direction of the 1 st main surface of the semiconductor substrate,
the intrinsic semiconductor layer is exposed in a direction perpendicular to the 1 st main surface from between the one conductivity type semiconductor layer and the reverse conductivity type semiconductor layer.
14. The solar cell of claim 13, wherein the intrinsic semiconductor layer is comprised of a 1 st intrinsic layer and a 2 nd intrinsic layer,
the 1 st intrinsic layer is interposed between the semiconductor substrate and the reverse conductive type semiconductor layer,
the 2 nd intrinsic layer is interposed between the semiconductor substrate and the one conductive type semiconductor layer,
the 2 nd intrinsic layer does not cover the outside of the reverse conductive semiconductor layer with respect to the semiconductor substrate.
15. The solar cell according to claim 14, wherein the 2 nd intrinsic layer is located on one surface of the semiconductor substrate or inside the semiconductor substrate with respect to an outer surface of the reverse conductivity type semiconductor layer.
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