TW201937748A - Method for producing solar cell - Google Patents

Abstract

This method involves: a step for forming a first semiconductor layer (13p) of a first conductive type on one principal surface of a crystal substrate (11); a step for layering a first lift-off layer (LF1) and a second lift-off layer (LF2) which contain silicon and have different densities on the first semiconductor layer; a step for selectively removing the first and second lift-off layers and the first semiconductor layer; a step for forming a second semiconductor layer (13n) of a second conductive type on the one principal surface containing the first and second lift-off layers and the first semiconductor layer; and a step for removing the second semiconductor layer which covers the second lift-off layer by removing the first and second lift-off layers using a first etching solution. The etching speeds of the first semiconductor layer and the first and second lift-off layers when subjected to the first etching solution satisfy formula (1): first semiconductor layer etching speed < second lift-off layer etching speed < first lift-off layer etching speed.

Description

Solar cell manufacturing method

The present invention relates to a method of manufacturing a solar cell.

In the prior art, a solar cell is generally a double-sided electrode type battery in which electrodes are disposed on two main faces (light receiving face and back face) of a semiconductor substrate. In recent years, a back contact (back electrode) type solar cell in which electrodes are disposed only on the back side has been developed, which does not cause Shielding Loss due to electrodes.

In the back contact solar cell, it is necessary to form a semiconductor layer pattern such as a p-type semiconductor layer and an n-type semiconductor layer with high precision on the back surface, and the manufacturing method is more complicated than the double-sided electrode type solar cell. As a technique for simplifying the manufacturing method, as disclosed in Patent Document 1, for example, there is a technique of forming a semiconductor layer pattern by a lift-off method.

That is, a method of patterning technology is being developed, with a silicon oxide-based (SiO _x) or silicon nitride is formed abscission lift (also referred to as a mask layer or sacrificial layer), removing the separation layer lift, the lift is formed and removed The semiconductor layer on the layer is separated, thereby forming a semiconductor layer pattern.

[Patent Document]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2013-120863

However, in the case where a high-precision semiconductor layer pattern is formed by the lift-off method, if the solubility of the germanium separation layer and the semiconductor layer are similar, sometimes the layer which is unintentionally removed may be Will be removed, which may cause a decrease in pattern accuracy or a decrease in productivity.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to efficiently manufacture a high-output back contact solar cell.

In order to achieve the object, an aspect of the present invention includes a process of forming a first semiconductor layer of a first conductivity type on a main surface of two main faces opposed to each other in a semiconductor substrate, on the first semiconductor layer a process of selectively removing the second ruthenium layer, the first ruthenium layer, and the first semiconductor layer by sequentially laminating processes of the first ruthenium layer and the second ruthenium layer containing lanthanide film materials having different densities Forming a second semiconductor layer of the second conductivity type on a main surface including the second separation layer, the first separation layer, and the first semiconductor layer, and removing the first separation by using the first etching solution And a second delamination layer to remove the second semiconductor layer covering the second delamination layer. The etching rate of the first etching solution to the first semiconductor layer, the first germanium layer, and the second germanium layer satisfies the following relationship (1): etching rate of the first semiconductor layer <etching of the second germanium layer Rate <etch rate to the first delamination layer (1).

According to the present invention, it is possible to efficiently manufacture a high-output back contact solar cell.

10‧‧‧ solar cells

11‧‧‧Crystal substrate (semiconductor substrate)

12‧‧‧Intrinsic semiconductor layer

13‧‧‧ Conductive semiconductor layer

13p‧‧‧p type semiconductor layer [first semiconductor layer of the first conductivity type / second semiconductor layer of the second conductivity type]

13n‧‧‧n type semiconductor layer [second semiconductor layer of second conductivity type / first semiconductor layer of first conductivity type]

15‧‧‧electrode layer

17‧‧‧Transparent electrode layer

18‧‧‧Metal electrode layer

LF‧‧‧ separation layer

LF1‧‧‧ first detachment

LF2‧‧‧Second separation

1 is a partial schematic cross-sectional view showing a solar cell of an embodiment.

2 is a plan view showing a main surface on the back side of a crystal substrate constituting a solar cell according to an embodiment.

3 is a partial schematic cross-sectional view showing a process in a method of manufacturing a solar cell according to an embodiment.

4 is a diagram showing a method of manufacturing a solar cell according to an embodiment. A partial schematic cross-sectional view of the process.

Fig. 5 is a partial schematic cross-sectional view showing a process in a method of manufacturing a solar cell according to an embodiment.

Fig. 6 is a partial schematic cross-sectional view showing a process of a method of manufacturing a solar cell according to an embodiment.

Fig. 7 is a partial schematic cross-sectional view showing a process in a method of manufacturing a solar cell according to an embodiment.

Fig. 8 is a partial schematic cross-sectional view showing a process of a method of manufacturing a solar cell according to an embodiment.

Fig. 9 is a partial schematic cross-sectional view showing a process in a method of manufacturing a solar cell according to an embodiment.

Fig. 10 is a photograph of a transmission electron microscope (TEM) showing a part of the separation layer used in the method of manufacturing a solar cell according to an embodiment.

Embodiments of the present invention will be described in detail below based on the drawings. The description of the preferred embodiments below is merely an essential example and is not intended to limit the invention, its application, or its use. In addition, the dimensional ratio of each component in the drawing is only a ratio for convenience of illustration, and does not necessarily represent an actual ratio.

(One embodiment)

An embodiment of the present invention will be described with reference to the drawings.

Fig. 1 is a cross-sectional view showing a part of a solar cell of the present embodiment. As shown in FIG. 1, the solar cell 10 of the present embodiment is made of a germanium (Si) crystal substrate 11. The crystal substrate 11 has two main faces 11S (11SU, 11SB) opposed to each other. Here, the principal surface on which light is incident is referred to as a front surface main surface 11SU, and the principal surface on the opposite side is referred to as a back surface main surface 11SB. For the sake of convenience, the surface side main surface 11SU is positively received by the back side main surface 11SB. One side is set as the light receiving side, and the side of the back side main surface 11SB that does not actively receive light is defined as the non-light receiving side.

The solar cell 10 of the present embodiment is a so-called twinned heterojunction solar cell, and is a back contact type (back electrode type) solar cell in which an electrode layer is disposed on the back side main surface 11SB.

The solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (p type semiconductor layer 13p, n type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 (transparent electrode layer 17, metal electrode layer) 18).

Hereinafter, for the sake of convenience, "p" may be indicated at the end of the reference symbol of the member corresponding to the p-type semiconductor layer 13p, or "n" may be indicated at the end of the reference symbol corresponding to the member of the n-type semiconductor layer 13n. Further, since the conductivity type is different, if there is a p-type or an n-type, one conductivity type may be referred to as a "first conductivity type", and another conductivity type may be referred to as a "second conductivity type".

The crystal substrate 11 may be a semiconductor substrate formed of single crystal germanium or a semiconductor substrate formed of polycrystalline germanium. Hereinafter, a single crystal germanium substrate will be described as an example.

The conductivity type of the crystal substrate 11 may be an n-type single crystal germanium substrate or a p-type single crystal germanium substrate. Wherein, the n-type single crystal germanium substrate is doped with impurities (for example, phosphorus (P) atoms) for supplying electrons to germanium atoms; and the p-type single crystal germanium substrate is doped with impurities for supplying holes to germanium atoms ( For example, boron (B) atoms are the main ones. Hereinafter, an n-type single crystal substrate having a long lifetime of a recognized carrier will be described as an example.

Further, from the viewpoint of blocking the received light, the surface of the two principal faces 11S of the crystal substrate 11 may have a texture structure TX (first texture structure) composed of a peak (convex) and a valley (concave). Further, the texture structure TX (concave-convex surface) can be formed, for example, by anisotropic etching using a difference in which the etching rate and the crystal plane of the crystal face of the crystal substrate 11 having a crystal plane direction of (100) are obtained. The difference in etching rate of the crystal face of the direction (111).

The size of the bump in the texture structure TX can be defined, for example, by the number of vertices (peaks). In the present embodiment, from the viewpoint of light acquisition and productivity, it is preferably in the range of 50,000/mm ² or more and 100000 pieces/mm ² or less, and particularly preferably in the range of 70,000 pieces/mm ² or more and 85,000 pieces/mm ² or less. range.

The thickness of the crystal substrate 11 may be 250 μm or less. Further, the measurement direction when the thickness is measured is a direction perpendicular to the average surface of the crystal substrate 11 (the average surface refers to the surface of the entire substrate which is not dependent on the texture structure TX). Then, the vertical direction, that is, the direction in which the thickness is measured, is thereafter defined as the thickness direction.

When the thickness of the crystal substrate 11 is 250 μm or less, the amount of use of ruthenium can be reduced, so that the cost of the ruthenium substrate can be easily saved, and the cost can be reduced. Further, the back surface contact type structure in which the hole and the electron generated by the photoexcitation in the germanium substrate are recovered only on the back side is preferably the thickness from the viewpoint of the free path of each exciton.

Further, when the thickness of the crystal substrate 11 is too small, the mechanical strength is lowered, or external light (sunlight) is not sufficiently absorbed, and the short-circuit current density is reduced. Therefore, the thickness of the crystal substrate 11 is preferably 50 μm or more, and more preferably 70 μm or more. When the texture structure TX is formed on the main surface of the crystal substrate 11, the thickness of the crystal substrate 11 is represented by the distance between the straight lines connecting the convex vertices in the uneven structure on the light receiving side, and the connection. A straight line formed by the convex apex in the uneven structure on the back side.

The intrinsic semiconductor layer 12 (12U, 12p, 12n) covers the two main faces 11S (11SU, 11SB) of the crystal substrate 11, thereby suppressing diffusion of impurities to the crystal substrate 11, and protecting the surface thereof. Further, "intrinsic (i type)" is not limited to the absolute intrinsic property of not containing conductive impurities, and includes a substantially intrinsic layer of "weak n-type" or "weak p-type", which is substantially intrinsic. In the layer, a trace amount of an n-type impurity or a p-type impurity is contained in the range in which the lanthanide layer can function as an intrinsic layer.

Further, the intrinsic semiconductor layer 12 (12U, 12p, 12n) is not essential, and may be formed as appropriate.

The material of the intrinsic semiconductor layer 12 is not particularly limited, and may be an amorphous lanthanoid material or a hydrogenated amorphous lanthanum film (a-Si:H film) containing ruthenium and hydrogen as a film. Further, the amorphous state referred to herein means a long-range disordered structure, that is, not only a completely disordered structure but also a short-term ordered structure.

Further, the thickness of the intrinsic semiconductor layer 12 is not particularly limited, and may be 2 nm or more and 20 nm or less. The reason is that when the thickness is 2 nm or more, the effect of protecting the protective layer of the crystal substrate 11 is increased, and when the thickness is 20 nm or less, the deterioration of the conversion characteristics due to the increase in resistance can be suppressed.

The method of forming the intrinsic semiconductor layer 12 is not particularly limited, and a plasma enhanced chemical Vapor Deposition method can be used. According to this method, it is possible to suppress the diffusion of impurities into the single crystal germanium and to effectively protect the surface of the substrate.

According to the plasma CVD method, by changing the hydrogen concentration in the intrinsic semiconductor layer 12 in the thickness direction thereof, it is also possible to form an energy gap distribution which is advantageous for recovering carriers.

Further, the film formation conditions for forming the thin film by the plasma CVD method may be, for example, a substrate temperature of 100 ° C or more and 300 ° C or less, a pressure system of 20 Pa or more and 2600 Pa or less, and a high frequency power density of 0.003 W/cm ² or more and 0.5 W/cm ^{2 .} the following.

Further, in the case of the intrinsic semiconductor layer 12, the material gas for forming the thin film may be a helium-containing gas such as methane (SiH ₄ ) or ethane (Si ₂ H ₆ ) or the like and hydrogen (H ₂ ) Mixed gas.

Further, a gas containing a different element such as methane (CH ₄ ), ammonia (NH ₃ ) or formane (GeH ₄ ) may be added to the gas to form tantalum carbide (SiC), silicon nitride (SiN _x ) or A ruthenium compound such as SIG (SIGe), whereby the energy gap of the film is appropriately changed.

The conductive semiconductor layer 13 has, for example, a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 1, the p-type semiconductor layer 13p is formed on a part of the back surface side main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12p. The n-type semiconductor layer 13n is formed on the other portion of the back surface side main surface of the crystal substrate 11 via the intrinsic semiconductor layer 12n. That is, the intrinsic semiconductor layer 12 exists between the p-type semiconductor layer 13p and the crystal substrate 11, and between the n-type semiconductor layer 13n and the crystal substrate 11, and the intrinsic semiconductor layer 12 functions as an intermediate layer.

The thickness of each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is not particularly limited, and may be 2 nm or more and 20 nm or less. The reason is that when the thickness is 2 nm or more, the effect of protecting the protective layer of the crystal substrate 11 is increased, and when the thickness is 20 nm or less, the deterioration of the conversion characteristics due to the increase in resistance can be suppressed.

The p-type semiconductor layer 13p and the n-type semiconductor layer 13n are disposed on the back side of the crystal substrate 11 to ensure that the p-type semiconductor layer 13p is electrically isolated from the n-type semiconductor layer 13n. The width of the conductive semiconductor layer 13 may be 50 μm or more and 3000 μm or less, or may be 80 μm or more and 500 μm or less. (The width of the semiconductor layer and the width of the electrode layer to be described later are, for example, patterned into a linear shape unless otherwise specified. The length of the pattern in which the extending direction is orthogonal to the direction).

When the photoexcitons (carriers) generated in the crystal substrate 11 are taken out through the conductive semiconductor layer 13, the effective mass of the holes is larger than the effective mass of the electrons. Therefore, the width of the p-type semiconductor layer 13p can be smaller than the width of the n-type semiconductor layer 13n from the viewpoint of reducing transmission loss. For example, the width of the p-type semiconductor layer 13p may be 0.5 times or more and 0.9 times or less the width of the n-type semiconductor layer 13n, or may be 0.6 times or more and 0.8 times or less.

The p-type semiconductor layer 13p is a germanium layer to which a p-type dopant (boron or the like) is added, and may be made of amorphous germanium from the viewpoint of suppressing impurity diffusion or suppressing series resistance. form. On the other hand, the n-type semiconductor layer 13n is a germanium layer to which an n-type impurity (phosphorus or the like) is added. Like the p-type semiconductor layer 13p, the n-type semiconductor layer 13n may be formed of an amorphous germanium layer.

As the material gas of the conductive semiconductor layer 13, a helium-containing gas or a mixed gas of a lanthanide gas and hydrogen (H ₂ ) can be used. Among them, the ruthenium-containing gas is methane (SiH ₄ ) or ethane hydride (Si ₂ H ₆ ). As the dopant gas, the p-type semiconductor layer 13p can be formed using diborane (B ₂ H ₆ ) or the like, and an n-type semiconductor layer can be formed using phosphorus (PH ₃ ) or the like. Further, since the amount of impurities such as boron (B) or phosphorus (P) may be a small amount, a mixed gas obtained by diluting the dopant gas with the material gas may be used.

Further, in order to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, it is also possible to add a substance such as methane (CH ₄ ), carbon dioxide (CO ₂ ), ammonia (NH ₃ ) or formane (GeH ₄ ). A gas of a different element is used to effect compounding of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n.

The low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10. The material of the low-reflection layer 14 is not particularly limited as long as it is a light-transmitting material that transmits light, and examples thereof include cerium oxide (SiO _x ), cerium nitride (SiN _x ), zinc oxide (ZnO), or titanium oxide (TiO _{x ).} ). Further, in the method of forming the low reflection layer 14, for example, the low reflection layer 14 can be formed by coating a resin material in which nanoparticles of oxide such as zinc oxide or titanium oxide are dispersed.

The electrode layer 15 covers the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, respectively, and is electrically connected to each of the conductive semiconductor layers 13. Thereby, the electrode layer 15 functions as a transport layer that guides carriers generated in the semiconductor layer 13p or the n-type semiconductor layer 13n.

Further, the electrode layer 15 may be formed only of a highly conductive metal. Further, from the viewpoint of electrical connection of each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, Alternatively, from the viewpoint of suppressing diffusion of atoms into the two semiconductor layers 13p and 13n which are metal materials, the metal electrode layer and the p-type semiconductor layer 13p and the metal electrode layer and the n-type semiconductor layer 13n may be provided. An electrode layer 15 formed of a transparent conductive oxide is formed between each.

In the present embodiment, the electrode layer 15 formed of a transparent conductive oxide is referred to as a transparent electrode layer 17, and the metal electrode layer 15 is referred to as a metal electrode layer 18. Further, as shown in a plan view of the back surface side main surface 11SB of the crystal substrate 11 shown in FIG. 2, the p-type semiconductor layer 13p and the n-type semiconductor layer 13n each having a comb-tooth shape are sometimes formed on the comb ridge. The electrode layer of the portion is referred to as a bus bar portion, and the electrode layer formed on the comb portion is referred to as a sub-gate portion.

The material of the transparent electrode layer 17 is not particularly limited, and examples thereof include zinc oxide (ZnO), indium oxide (InO _x ), or transparent conductive obtained by adding various metal oxides to the indium oxide at a concentration of 1% by weight or more and 10% by weight or less. As the oxide, the metal oxide is, for example, titanium oxide (TiO _x ), tin oxide (SnO), tungsten oxide (WO _x ) or molybdenum oxide (MoO _x ).

The thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less. A method for forming the thickness of the transparent electrode layer is, for example, a physical vapor deposition (PVD) method such as a sputtering method, or a metal organic chemical vapor deposition using a reaction of a metal organic compound with oxygen or water. Method (MOCVD: Metal-Organic Chemical Vapor Daposition) and the like.

The material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), or nickel (Ni).

The thickness of the metal electrode layer 18 may be 1 μm or more and 80 μm or less. A method of forming the metal electrode layer 18 suitable for this thickness is, for example, a printing method or a plating method using inkjet printing or screen printing using a material slurry. However, it is not limited thereto, and if a vacuum process is employed, an evaporation method or a sputtering method may be employed.

Further, the width of the comb tooth portion of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be equal to the width of the metal electrode layer 18 formed on the comb tooth portion. However, the width of the metal electrode layer 18 may also be narrower than the width of the comb tooth portion. Further, if a configuration for preventing leakage current between the metal electrode layers 18 is employed, the width of the metal electrode layer 18 may be wider than the width of the comb tooth portions.

In the present embodiment, the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are laminated on the back surface side main surface 11SB of the crystal substrate 11, and a predetermined annealing treatment is performed. In order to protect the respective bonding faces, generation of a defect level at the conductive semiconductor layer 13 and its interface is suppressed, and crystallization of the transparent conductive oxide in the transparent electrode layer 17 is achieved.

The annealing treatment in the present embodiment is, for example, an annealing treatment in which the crystal substrate 11 on which the respective layers have been formed is placed in an oven heated to 150 ° C or higher and 200 ° C or lower. In this case, the gaseous environment in the oven can be an atmospheric environment. Further, if a hydrogen gas or a nitrogen atmosphere is used, the annealing treatment can be performed more efficiently. Further, the annealing treatment may be an RTA (Rapid Thermal Annealing) treatment in which the crystal substrate 11 on which the respective layers have been formed is irradiated with infrared rays by an infrared heater.

[Method of Manufacturing Solar Cell]

Hereinafter, a method of manufacturing the solar cell 10 of the present embodiment will be described with reference to FIGS. 3 to 9.

First, as shown in FIG. 3, the crystal substrate 11 having the texture structure TX is prepared on both the front side main surface 11SU and the back side main surface 11SB.

Next, as shown in FIG. 4, for example, an intrinsic semiconductor layer 12U is formed on the front surface side main surface 11SU of the crystal substrate 11. Next, an anti-reflection layer 14 is formed on the formed intrinsic semiconductor layer 12U. From the viewpoint of blocking the light confinement effect of the incident light, the antireflection layer 14 is made of silicon nitride (SiN _x ) or yttrium oxide (SiO _x ) having a suitable light absorption coefficient and a suitable refractive index.

Then, as shown in FIG. 5, on the back surface side main surface 11SB of the crystal substrate 11, for example, an intrinsic semiconductor layer 12p formed of an i-type amorphous germanium is formed. Next, a p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12p. Thereby, the p-type semiconductor layer 13p is formed on the one main surface of the crystal substrate 11, that is, the back surface side main surface 11SB, with the intrinsic semiconductor layer 12p interposed therebetween.

Thereafter, a plurality of layers of the delamination layer LF (the first separation layer LF1 and the second separation layer LF2) are formed on the formed p-type semiconductor layer 13p. Specifically, the first separation layer LF1 and the second separation layer LF2 containing the ruthenium-based thin film materials having different densities from each other are sequentially laminated on the p-type semiconductor layer 13p. Thereby, the first detachment layer LF1 is formed on the p-type semiconductor layer 13p, and the second detachment layer LF2 is formed on the first detachment layer LF1.

Then, as shown in FIG. 6, the second detachment layer LF2, the first detachment layer LF1, and the p-type semiconductor layer 13p are patterned on the back surface side main surface 11SB of the crystal substrate 11. Thereby, the p-type semiconductor layer 13p is selectively removed, and a non-formation region NA in which the p-type semiconductor layer 13p is not formed is generated. On the other hand, at least the second detachment layer LF2, the first detachment layer LF1, and the p-type semiconductor layer 13p remain in the region where the back surface side main surface 11SB of the crystal substrate 11 is not etched.

These patterning processes are carried out as follows: by photolithography, for example, a photoresist film (not shown) having a predetermined pattern is formed on the second barrier layer LF2, and the etching is masked by the formed photoresist film. The area you can get up. In the case shown in FIG. 6, the main surface 11SB of the back surface side of the crystal substrate 11 is patterned by patterning each layer of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, the first germanium layer LF1, and the second germanium layer LF2. A part of the area generates the non-formation area NA, that is, the exposed area of the back side main surface 11SB. Further, the details of the non-formation region NA will be described later.

The etching solution used in the process shown in FIG. 6 is, for example, a mixed solution of hydrofluoric acid and an oxidizing solution (for example, fluoronitric acid) or a solution obtained by dissolving ozone in hydrofluoric acid. Solution (hereinafter referred to as ozone/hydrofluoric acid solution). The etching solution at this time corresponds to the second etching solution. In addition, the etchant that assists in etching the delamination layer LF is hydrogen fluoride. Moreover, the patterning here is not limited to wet etching using an etching solution. For example, patterning may be performed by dry etching, or pattern printing may be performed using an etching paste or the like to realize patterning.

Then, as shown in FIG. 7, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are sequentially formed not only on the second germanium layer LF2, the first germanium layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p. The intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are sequentially formed on the back surface side main surface 11SB of the crystal substrate 11. Thereby, a laminated film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed on the non-formation region NA, on the surface and the side surface (end surface) of the second separation layer LF2, and the first separation layer LF1, p-type semiconductor The layer 13p and the side surface (end surface) of the intrinsic semiconductor layer 12p.

Then, as shown in FIG. 8, the stacked first germanium layer LF1 and the second germanium layer LF2 are removed by an etching solution, thereby removing the n-type semiconductor layer deposited on the second germanium layer LF2 from the crystal substrate 11. 13n and intrinsic semiconductor layer 12n. The etching solution at this time corresponds to the first etching solution. Further, the etching solution used for the patterning is, for example, hydrofluoric acid.

In addition, in the process of removing the n-type semiconductor layer (second conductivity type semiconductor layer) 13n covering the germanium layer LF shown in FIG. 8 (hereinafter referred to simply as the lift-off process), the etching solution is applied to the p-type semiconductor layer 13p, The etching rate of the separation layer LF1 and the second separation layer LF2 satisfies the following relation (1).

Etching rate to the p-type semiconductor layer 13p <etching rate to the second germanium layer LF2 <etching rate to the first germanium layer LF1... (1)

Then, as shown in FIG. 9, on the back surface side main surface 11SB of the crystal substrate 11, for example, a p-type semiconductor layer 13p and an n-type half are used, for example, by a sputtering method using a mask. On the conductor layer 13n, transparent electrode layers 17 (17p, 17n) are respectively formed to form the isolation trenches 25. Further, the transparent electrode layer 17 (17p, 17n) may be formed by the following method instead of the sputtering method. For example, a transparent conductive oxide film may be formed on the entire surface of the back surface main surface 11SB without using a mask, and then etched by photolithography to leave residues on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, respectively. There is a transparent conductive oxide film. Here, by forming the isolation trench 25 which insulates the p-type semiconductor layer 13p and the n-type semiconductor layer 13n from each other, it is difficult to generate a leak current.

Thereafter, a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17, for example, using a mesh (not shown) having an opening.

The back contact type solar cell 10 is formed by the above process.

(summary and effect)

From the above manufacturing method of the solar cell 10, the following conclusion can be drawn.

First, the separation layer LF is composed of at least two layers and has a density difference from each other, and the above relation (1) is satisfied due to the existence of the density difference. That is, the first detachment layer LF1 having a faster etching rate is disposed closer to one side of the crystal substrate 11 than the second delamination layer LF2 having a slower etching rate. Thus, the etching accuracy of each of the processes shown in FIG. 6 and the process shown in FIG. 8 is improved by the difference in etching rates in the germanium separation layer LF.

In order to prevent an undesired short circuit or leakage current in the solar cell 10, it is important that the etching precision, that is, the conductive semiconductor layer 13 or the electrode layer 15 is formed with high precision. In the process shown in FIG. 6, that is, in the process of selectively removing the p-type semiconductor layer (first conductivity type semiconductor layer) 13p (hereinafter simply referred to as a p-type semiconductor layer patterning process), a part of the germanium layer LF is removed. The masking function prevents the etching solution from adhering to the p-type semiconductor layer 13p of the formation region. Therefore, the width of the patterned p-type semiconductor layer 13p depends on the residual detachment The width of the layer LF. That is, although it is required to etch a pattern having a width of about several hundred μm with high precision in the p-type semiconductor layer patterning process, the accuracy in the thickness direction is not so important.

Therefore, if the etching rate of the etching solution to the delamination layer LF is too fast, the delamination layer LF is easily over-etched in the width direction (the width becomes narrower than the desired width). Therefore, the pattern accuracy of the detachment layer LF may be lowered. Thus, the etching rate of the etching liquid (second etching solution) to the delamination layer LF is too fast.

On the other hand, in the detachment process shown in FIG. 8, the n-type semiconductor layer 13n covers not only the second delamination layer LF2 remaining in the p-type semiconductor layer patterning process, but also at the desired position (with residual p An n-type semiconductor layer 13n is further formed on the non-molding region NA) adjacent to the semiconductor layer 13p. Next, while leaving the n-type semiconductor layer 13n at the desired position as a pattern, the upper surface and the side surface (end surface) of the second separation layer LF2, the first separation layer LF1, the p-type semiconductor layer 13p, and the present are removed. The n-type semiconductor layer 13n on the side surface (end surface) of the semiconductor layer 12p is etched. Therefore, it is preferable that the etching rate of the etching liquid (first etching solution) to the germanium layer LF is larger than the etching rate of the p-type semiconductor layer 12p. For example, it is required to completely etch in a region having a width of several tens of nm to several hundreds of nm, but there is no requirement for accuracy in the width direction. Further, from the viewpoint of productivity, it is preferred that the etching rate is faster, and the processing time is shortened.

Thus, it is required that the p-type semiconductor layer patterning process and the etch-off process have opposite etching characteristics to the germanium isolation layer LF. This characteristic can be realized by using the difference in density between the separation layer LF1 and the separation layer LF2 to satisfy the relationship (1).

If the relationship (1) is satisfied in the p-type semiconductor layer patterning process, the first delamination layer LF1 dissolves fastest in the non-molding region NA, and the second detachment layer LF2 thereon is also easily detached from the crystal substrate 11. (At this time, the second detachment layer LF2 is not only detached and dissolved), and the p-type semiconductor layer 13p exposed from the first detachment layer LF1 Also began to dissolve.

More specifically, for example, as shown in FIG. 6, in the p-type semiconductor layer patterning process, even if the first delamination layer LF1 under the second delamination layer LF2 passes through the layers remaining due to lamination (second The side surface SE of the delamination layer LF2, the first detachment layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p) is etched and etched, and the first delamination layer LF1 which is not etched away remains. Therefore, the second detachment layer LF2 connected thereto will remain. Thereby, the remaining second detachment layer LF2 functions as the detachment layer LF in the separation process. Further, since the p-type semiconductor layer 13p forming the region must be left, the etching rate is slower than that of the first barrier layer LF1 and the second barrier layer LF2.

In addition, in the separation process, if the lower layer, that is, the first separation layer LF1 is completely removed, the n-type semiconductor layer 13n is even if the second separation layer LF2 on the first separation layer LF1 remains. Remove. That is, the second conductive type semiconductor layer LF2 or even the n-type semiconductor layer 13n thereon may be removed.

As described above, the plurality of layers of the LF layer are desired to be almost completely removed in the lift-off process shown in FIG. 8, but the process up to here (for example, the p-type semiconductor layer patterning process shown in FIG. 6) In order not to over-etch, the etching rate is designed to satisfy the etching rate of the p-type semiconductor layer 13p <the etching rate of the second germanium layer LF2 <the first germanium layer LF1 (using the density difference of the germanium isolation layers LF1, LF2) Relationship (1)). In addition, as in the p-type semiconductor layer patterning process, in the lift-off process, since the p-type semiconductor layer 13p of the formation region must be left, the etching rate of the p-type semiconductor layer 13p is higher than that of the first separation layer LF1 and The etching rate of the two-layer LF2 is slow.

As described above, when the p-type semiconductor layer 13p and the lift-off layer LF satisfying the relationship (1) are used, for example, in the lift-off process, the n-type semiconductor layer 13n is patterned without etching with a photoresist film. That is, if the solar cell 10 described above is used According to the manufacturing method, the patterning process is simplified, and the back contact solar cell 10 can be manufactured efficiently. Further, since the pattern accuracy is improved, it is also possible to prevent a short circuit or a leakage current from occurring in the solar cell 10. As a result, a high output can be obtained from the solar cell 10.

Further, the number of layers of the separation layer LF may be two or more, and two layers may be used from the viewpoint of productivity.

Further, in the process shown in FIG. 5, a plurality of layers of the delamination layer LF are formed on the p-type semiconductor layer 13p which is formed first. In the process shown in FIG. 6, the germanium layer LF is patterned by, for example, etching. Thereafter, in the process shown in FIG. 8, the germanium layer LF is removed together with the n-type semiconductor layer 13n. Therefore, it is preferable that the separation layer LF is formed of a material dissolved in an etching solution used in the two processes shown in FIGS. 6 and 8. For example, it may be a plurality of layers of leaching layer LF containing cerium oxide as a main component.

Further, from the design point of view, the delamination layer LF is a layer which is almost completely removed in the detachment process shown in FIG. 8, but in the process up to here (for example, the process shown in FIG. 6), in order not to over-etch, When the etching rate is designed, it is preferable to satisfy the above relationship (1): the etching rate of the p-type semiconductor layer 13p < the etching rate of the second germanium layer LF2 < the etching rate of the first germanium layer LF1. .(1).

If the p-type semiconductor layer 13p, the second separation layer LF2, and the first separation layer LF1 satisfy the above relationship (1), the first separation layer LF1 dissolves rapidly. Therefore, the various layers deposited on the first release layer LF1 are easily detached from the crystal substrate 11. As a result, the patterning process is simplified, so that the back contact solar cell 10 can be manufactured efficiently.

Thus, in order to achieve different etch rates, for example, there is a design method that has a density difference between the first delamination layer LF1 and the second delamination layer LF2. Specifically, for example, the main components of the first detachment layer LF1 and the second delamination layer LF2 are cerium oxide, and their density is varied in order to control the etching rate. The reason is Thus, the lower the density of the layer, the greater the etch rate of the layer.

Specifically, it is preferable that the first detachment layer LF1 and the second detachment layer LF2 have yttrium oxide as a main component, and the density of the first detachment layer LF1 and the second detachment layer LF2 satisfy the following relationship (2) ): density of the second detachment layer LF1 > density of the first 掀 separation layer LF1... (2)

Further, as shown in FIG. 10, the cross section of the solar cell 10 is observed using a transmission electron microscope (TEM), and it can be seen that, corresponding to the density of each of the detachment layers LF1 and LF2, the first separation layer LF1 and In the second detachment layer LF2, there is a difference in the density in the layer (that is, depending on whether there is a gap on the TEM image of the section, the density of the detachment layer LF1, LF2 can be judged). .

The term "dense" as used herein includes not only a small (micro) density of microscopic density derived from the arrangement of atoms forming a layer, but also a macroscopic situation in which there are (疎) no (closed) minute voids in the layer. Therefore, the first detachment layer LF1 may have a configuration in which the entire layer has a void. The relationship that the above density is low and the etching rate is large depends largely on the dense structure.

Further, the density can be determined based on the magnitude of the refractive index of each layer of the separation layers LF1 and LF2. That is, the large refractive index corresponds to a large density; the small refractive index corresponds to a small density.

Further, from the viewpoint of the composition of the delamination layer LF, in the case where the LF layer is a film mainly composed of cerium oxide, SiO _x represents the first detachment layer and SiO _y represents the second detachment layer. In the layer, it is preferred that the values of the respective components x and y of oxygen satisfy the following relation (3) and relation (4).

y>x......(3)

1.0<x<2.2,0.5<y<2.2......(4)

Preferably, the size relationship is designed within the above ranges.

Also, here, the upper limit of the value of the component ratio x is greater than the general stoichiometric value. (x=2.0). The reason is that in the film formation process of the delamination layer LF, excessive oxygen is sometimes contained.

In the case of film formation by the CVD method, it is easy to obtain a sparse structure by controlling the dense structure of the ruthenium oxide by pressure, for example, by setting the pressure to be low.

The film thickness of the detachment layer LF is preferably 20 nm or more and 600 nm or less, and particularly preferably the film thickness of the iridium layer LF is 50 nm or more and 450 nm or less. Within this range, it is preferred that the second barrier layer LF2 is thicker than the first barrier layer LF1.

Further, from the viewpoint of preferentially considering the light acquisition efficiency, the texture structure TX is also formed on the back surface side of the crystal substrate 11, and since it is affected by the scattering due to the texture structure, the patterning process using the laser light may be somewhat difficult.

Further, in the p-type semiconductor layer patterning process shown in FIG. 6, the intrinsic semiconductor layer 12p can be etched to expose a part of the crystal substrate 11. As a result, it is sometimes possible to suppress the lifetime of carriers from being shortened by photoelectric conversion.

Further, an n-type semiconductor layer 13n is formed in the n-type semiconductor layer forming process shown in FIG. The n-type semiconductor layer 13n is formed on the entire surface of the back surface side main surface 11SB of the crystal substrate 11. That is, the n-type semiconductor layer 13n is formed not only on a part of the exposed surface of the crystal substrate 11 where the p-type semiconductor layer 13p is not formed but also on the lift-off layer LF. Further, the intrinsic semiconductor layer 12n may be formed between the crystal substrate 11 and the n-type semiconductor layer 13n.

Further, before the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in the process shown in FIG. 7, a cleaning process is provided to clean the surface of the crystal substrate 11 exposed in the p-type semiconductor layer patterning process shown in FIG. . Further, the cleaning process is intended to remove defects or impurities generated on the surface of the crystal substrate 11 in the process shown in Fig. 6, for example, treatment with hydrofluoric acid.

In addition, in the separation process shown in FIG. 8, if the etching solution is used to remove the plural When the layer is separated from the layer LF, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n deposited on the germanium layer LF are also simultaneously removed from the crystal substrate 11 (so-called separation). This process does not require a photoresist coating process and a development process used in photolithography as compared with the case of photolithography in the process shown in FIG. Therefore, it is easy to pattern the n-type semiconductor layer 13n. Further, if the delamination layer LF is a film containing cerium oxide as a main component, the etching liquid in the process shown in Fig. 8 is preferably hydrofluoric acid. In this case, the etchant used to etch the germanium layer is hydrogen fluoride.

Further, it is preferable that the crystal substrate 11 has a texture structure TX, and each surface of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n formed on the back surface side main surface 11SB of the crystal substrate 11 contains a texture reflecting the texture structure TX Construction (second texture construction).

If the conductive semiconductor layer 13 is a semiconductor layer having a texture structure TX on its surface, the etching solution is likely to penetrate into the semiconductor layer 13 due to the unevenness of the texture structure TX. Therefore, the conductive semiconductor layer 13 is easily removed, that is, the conductive semiconductor layer 13 is easily patterned.

Further, in the present embodiment, the texture structure TX (first texture structure) is formed on both the main surface 11S of the crystal substrate 11, that is, on the front surface main surface 11SU and the back surface main surface 11SB, but it is also possible The texture construct TX is formed on only one main surface. That is, in the case where the texture structure TX is formed on the surface side main surface 11SU, the acquisition effect and the blocking effect of the received light are improved. On the other hand, in the case where the texture structure TX is formed on the back side main surface 11SB, the light acquisition effect is improved, and the patterning of the conductive semiconductor layer 13 is facilitated. Therefore, the texture structure TX of the crystal substrate 11 may be formed on at least one of the main faces 11S. Further, in the present embodiment, the texture structure TX of the two main faces 11S has the same structure. However, the present invention is not limited thereto, and the size of the unevenness of the texture structure TX of the front side main surface 11SU may be different from that of the back side main surface 11SB.

Further, in the p-type semiconductor layer patterning process shown in FIG. 6, the back side main surface 11SB of the crystal substrate 11 is exposed in the non-formation region NA, but is not limited thereto. In other words, the intrinsic semiconductor layer 12p may remain in the non-formation region NA of the back side main surface 11SB. It is important that the p-type semiconductor layer 13p is selectively removed in a part of the back surface side main surface 11SB of the crystal substrate 11, and the region in which the p-type semiconductor layer 13p has been removed is used as the non-formation region NA.

In this case, it is possible to omit the process of forming the intrinsic semiconductor layer 12n on the remaining second germanium layer LF2 and the non-formation region NA before depositing the n-type semiconductor layer 13n.

Further, it is preferable that the etching solution (first etching solution) used in the separation process shown in FIG. 8 contains an etching agent concentration in the etching solution used in the p-type semiconductor layer patterning process shown in FIG. The second etching solution) has an etchant concentration or lower.

As a result, in the process shown in FIG. 6, a part of the delamination layer LF is left, but in the process shown in FIG. 8, the delamination layer LF is removed, and the desired patterning can be easily performed. However, the concentration of the etchant of the first etching solution and the second etching solution may be the same. Moreover, the composition of the etchant of the two solutions is not necessarily different, and the components may be the same.

The present invention is not limited to the above embodiments, and various changes can be made within the scope of the claims. In other words, the technical means appropriately changed within the scope indicated by the claims are combined, and the embodiments obtained thereby are also included in the technical scope of the present invention.

For example, the semiconductor layer used in the semiconductor layer forming process shown in FIG. 5 is the p-type semiconductor layer 13p, but is not limited thereto, and may be the n-type semiconductor layer 13n. Further, the conductivity type of the crystal substrate 11 is not particularly limited, and may be either p-type or n-type.

[Examples]

Hereinafter, the present invention will be specifically described based on examples. However, the invention is not limited to such embodiments. The examples and comparative examples were produced as follows (see [Table 1]).

[Crystal substrate]

First, the crystal substrate was a single crystal germanium substrate having a thickness of 200 μm. Anisotropic etching is performed on both main faces of the single crystal germanium substrate. Thereby, a pyramid-shaped texture structure is formed on the crystal substrate.

[Intrinsic Semiconductor Layer]

Then, the crystal substrate was placed in a CVD apparatus, and an intrinsic semiconductor layer (thickness: 8 nm) formed of tantalum was formed on both main surfaces of the crystal substrate to be placed. The film formation conditions were a substrate temperature of 150 ° C, a pressure system of 120 Pa, a flow ratio of SiH ₄ /H ₂ of 3/10, and a power density of 0.011 W/cm ² .

[p-type semiconductor layer (first conductivity type semiconductor layer)]

A crystal substrate having two intrinsic semiconductor layers formed on the main surface thereof is placed in a CVD apparatus, and a p-type hydrogenated amorphous lanthanide film (film thickness) is formed on the intrinsic semiconductor layer on the main surface of the back surface side of the crystal substrate. 10nm).

The substrate temperature was 150 ° C, the pressure was 60 Pa, the flow ratio of SiH ₄ /B ₂ H ₆ was 1/3, and the power density was 0.01 W/cm ² . Deposition conditions: Further, the flow coefficient B ₂ H ₆ gas flow rate is H diluent gas to the diluted 5000ppm ₂ B ₂ H _6.

[掀层]

CVD apparatus used, on the p-type hydrogenated amorphous silicon-based thin film, are sequentially formed a silicon oxide (SiO _x) as a main component of the first lift and the second lift separation layer delamination.

The film formation conditions of the first separation layer were as follows: substrate temperature was 180 ° C, pressure system was 50 Pa, SiH ₄ /CO ₂ flow ratio was 1/5, and power density was 0.01 W/cm ² . Further, the film formation conditions of the second ruthenium layer were the same as those of the first ruthenium layer except that the flow ratio of SiH ₄ /CO ₂ was 1/7 and the power density was 0.3 W/cm ² . The film formation time of the two delamination layers is adjusted to ensure that they reach the specified film thickness.

[Patterning of the germanium and p-type semiconductor layers]

A photosensitive photoresist film is formed on both main faces of the crystal substrate on which the p-type semiconductor layer is formed. Forming the formed photosensitive photoresist film by photolithography to remove a portion of the back side main surface from the second germanium layer, the first germanium layer, and the p-type semiconductor layer, thereby forming a p-type semiconductor layer The removed non-formed region, on the other hand, retains at least the p-type semiconductor layer, the first germanium layer, and the second germanium layer on the remaining portion of the back side main surface.

At this time, the crystal substrate on which the plurality of layers are formed is immersed in the water-nitrogen mixed acid to remove the first separation layer and the second separation layer. The water-added nitric acid mixed acid is an etchant and contains hydrogen fluoride at a concentration of 1% by weight. Thereafter, the p-type semiconductor layer exposed by the removal of the first germanium layer and the second germanium layer and the intrinsic semiconductor layer directly under it are removed. That is, the non-formation region in the main surface on the back surface side of the crystal substrate is exposed.

Further, in Example 4, a water-containing nitrate-containing mixed acid containing hydrogen fluoride at a concentration of 5% by weight was used, and the immersion time was shorter than that of the other examples.

[n-type semiconductor layer (second conductive type semiconductor layer)]

After the p-type semiconductor layer patterning process, the exposed portion of the back side main surface has been washed with a hydrofluoric acid having a concentration of 2% by weight in a CVD apparatus to be in contact with the first intrinsic semiconductor layer. The same film formation conditions form an intrinsic semiconductor layer (film thickness: 8 nm) on the main surface of the back surface side. Next, an n-type hydrogenated amorphous lanthanoid thin film (film thickness: 10 nm) was formed on the formed intrinsic semiconductor layer.

The substrate temperature was 150 ° C, the pressure system was 60 Pa, the flow ratio of SiH ₄ /PH ₃ was 1/2, and the power density was 0.01 W/cm ² . Further, the flow rate of the PH ₃ gas is the flow rate of the dilution gas after the PH ₃ is diluted with H ₂ to 5000 ppm.

[Removal of the germanium and n-type semiconductor layers (deviation)]

The crystal substrate on which the n-type semiconductor layer is formed is immersed in hydrofluoric acid. The hydrofluoric acid is an etchant and contains hydrogen fluoride at a concentration of 3% by weight. Thereby, the germanium layer, the n-type semiconductor layer covering the germanium layer, and the intrinsic semiconductor layer between the germanium layer and the n-type semiconductor layer are removed together.

[electrode layer, low reflection layer]

An oxide film (film thickness: 100 nm) to be a transparent electrode layer was formed on the conductive semiconductor layer of the crystal substrate by a magnetron sputtering apparatus. Further, a tantalum nitride layer as a low reflection layer is formed on the light-receiving surface side of the crystal substrate. Indium oxide (ITO) is used as the transparent conductive oxide, and the indium oxide (ITO) is a target. Among them, the tin oxide contains tin oxide in a concentration of 10% by weight. A mixed gas of argon (Ar) and oxygen (O ₂ ) was introduced into the chamber of the sputtering apparatus, and the pressure in the chamber was set to 0.6 Pa. The mixing ratio of argon to oxygen is conditioned on the lowest resistivity (so-called bottom). Further, a film was formed at a power density of 0.4 W/cm ² using a direct current power source.

Then, etching is performed by photolithography to leave only the transparent conductive oxide film on the conductive semiconductor layer (p-type semiconductor layer and n-type semiconductor layer), and the transparent conductive oxide film is formed into a transparent electrode layer. The transparent electrode layer formed by the etching can prevent conduction between the transparent conductive oxide film on the p-type semiconductor layer and the transparent conductive oxide film on the n-type semiconductor layer.

Further, the silver paste (manufactured by Fujikura Kasei Co., Ltd.: DOTITE FA-333) was not diluted, and the silver paste was directly printed on the transparent electrode layer by screen printing, and was carried out in an oven at a temperature of 150 ° C. Sub-heat treatment. Thereby, a metal electrode layer is formed.

Next, a method of evaluating the back contact solar cell will be described. The evaluation results are referred to [Table 1].

[Evaluation of film thickness and etching property]

The film thickness of the ruthenium layer and the etching state of the ruthenium layer were evaluated by an optical microscope (BX51: manufactured by OLYMPUS CORPORATION) and SEM (field emission scanning electron microscope S4800: manufactured by Hitachi High-Technologies Corporation). The case where the etching is performed in accordance with the design pattern removal region after the p-type semiconductor layer patterning process is described as "○"; the case where the germanium separation layer is excessively etched and adversely affects the solar cell characteristics is referred to as "×". .

The situation in which the separation layer is removed during the separation process will be recorded as "○", and the situation in which the separation layer remains in the separation process will be recorded as "X". In Comparative Example 2, the germanium layer was removed in the p-type semiconductor layer patterning process, and the situation after the separation process could not be evaluated again, so it was denoted as "-".

[The secret evaluation of the separation layer]

The cross section of the solar cell was observed by a transmission electron microscope (TEM). According to whether there is a gap in the cross-sectional TEM image, it is judged whether the cross-sectional structure of the first crucible layer is sparse and whether the structure of the second crucible layer is dense.

[Evaluation of conversion efficiency]

Using a solar simulator, the reference solar light of AM (air mass) 1.5 was irradiated with a light amount of 100 mW/cm ² , and the conversion efficiency (Eff (%)) of the solar cell was measured. The conversion efficiency (solar cell characteristics) of Example 1 was set to 1.00, and the relative value thereof was disclosed in [Table 1].

In each of the examples and the comparative examples, the etching rate of the first ruthenium layer of the hydrofluoric acid having a concentration of 3% by weight was 6.5 nm/s, and the etching rate for the second ruthenium layer was 0.3 nm/s. On the other hand, the etching rate of the p-type semiconductor layer is 0.1 nm/s or less.

The patterning accuracy and solar cell characteristics of Examples 1 to 4 were all good. In Example 2, in which the thickness of the first ruthenium layer was large, the time required for removing the ruthenium layer in the detachment process was short, and the productivity was excellent.

Further, in Examples 1 to 3, a water-nitrocide mixed acid containing hydrogen fluoride having a concentration of 1% by weight was used in the p-type semiconductor layer patterning process. For Examples 1 to 3, the pattern after the patterning process of the p-type semiconductor layer was observed with an optical microscope, and as a result, the pattern accuracy was good. Wherein the thickness of the first detachment layer of Embodiment 3 is the smallest, and the thickness of the first detachment layer is smaller than the thickness of the second detachment layer, the pattern precision of the embodiment 3 is particularly good.

Compared with Example 1, the pattern of Example 4 was slightly inferior from the viewpoint of uniformity in the battery, but did not adversely affect the characteristics of the solar cell.

The results are summarized as follows: Compared with the comparative example, the crucible layer in the embodiment has a laminated structure, and thus the solar cell characteristics are good. The reason for this is that the p-type semiconductor layer patterning process can be patterned uniformly and accurately, and the etching can be performed uniformly and accurately in the lift-off process, whereby the first conductive type semiconductor layer and the second conductive can be formed. The arrangement of the semiconductor layers or the electrical contact between the first conductive semiconductor layer and the second conductive semiconductor layer and the electrode layer is good (the series resistance is suppressed).

In particular, in the case where the ruthenium layer is formed only of the high refractive index layer (Comparative Example 1), there is a residue of the ruthenium layer in the detachment process, so that sufficient solar cell characteristics cannot be obtained; In the case where the refractive index layer is formed (Comparative Example 2), the ruthenium separation layer is almost always mixed with the p-type semiconductor layer to form a water-added nitric acid mixed acid. It is removed, so that sufficient solar cell characteristics cannot be obtained.

Claims (6)

A method of manufacturing a solar cell, comprising: forming a first semiconductor layer of a first conductivity type on one main surface of two main faces opposite to each other in a semiconductor substrate, on the first semiconductor layer, in turn a process of laminating a first separation layer and a second separation layer containing lanthanide film materials having different densities, and selectively removing the processes of the second separation layer, the first separation layer, and the first semiconductor layer, Forming a second semiconductor layer of the second conductivity type on the one main surface including the second separation layer, the first separation layer, and the first semiconductor layer, and removing the first portion by using the first etching solution a process of removing the foregoing second semiconductor layer covering the second germanium layer; the first etching solution is opposite to the first semiconductor layer, the first germanium layer, and the second germanium layer The etching rate satisfies the following relation (1): the etching rate to the first semiconductor layer <the etching rate to the second germanium layer < the etching rate to the first germanium layer (1). The method of manufacturing a solar cell according to claim 1, wherein the first detachment layer and the second detachment layer are mainly composed of cerium oxide, and the density of each layer satisfies the following relationship (2): the second detachment layer Density > density of the first 掀 separation layer (2). The method of manufacturing a solar cell according to claim 1 or 2, wherein the first detachment layer has a structure that is sparse than the second detachment layer. The method of manufacturing a solar cell according to claim 1 or 2, wherein the semiconductor substrate has a first texture structure on the two main faces, The first semiconductor layer and the second semiconductor layer formed on the one main surface of the semiconductor substrate have a second texture structure reflecting the first texture structure. The method of manufacturing a solar cell according to claim 1 or 2, wherein, in the process of selectively removing the first semiconductor layer, a part of the one main surface of the semiconductor substrate is exposed. The method of manufacturing the solar cell of claim 1 or 2, wherein the forming the first semiconductor layer comprises: forming a first intrinsic semiconductor on the one main surface of the semiconductor substrate before forming the first semiconductor layer The process of selectively removing the first semiconductor layer includes: after the first semiconductor layer, selectively removing the process of the first intrinsic semiconductor layer; the process of forming the second semiconductor layer includes: Before the forming the second semiconductor layer, a process of forming a second intrinsic semiconductor layer on the one main surface of the semiconductor substrate including the second germanium layer, the first germanium layer and the first semiconductor layer; The process of the second semiconductor layer includes: a process of selectively removing the second intrinsic semiconductor layer after the second semiconductor layer.