WO2020203227A1 - Method for manufacturing solar cell, in-process solar cell substrate, and solar cell - Google Patents

Abstract

The present invention provides a method for manufacturing a solar cell in which mass production is facilitated and yield is improved compared to the past, an in-process solar cell substrate, and a solar cell.　The method includes: a first semiconductor layer formation step for forming a reverse conductivity-type semiconductor layer 16 on the first main surface side of a semiconductor substrate 5; a liftoff layer formation step for forming a liftoff layer 50 having silicon oxide or silicon nitride as the main component on the reverse conductivity-type semiconductor layer 16; a second semiconductor layer formation step for forming a first conductivity-type semiconductor layer 11 so as to have a portion overlapping with the liftoff layer 50 when the semiconductor substrate 5 is viewed in plan view; and a liftoff step for dissolving the liftoff layer 50 with a liftoff liquid and thereby removing the overlapping portion of the first conductivity-type semiconductor layer 11. In the liftoff layer formation step, a first reaction gas is blown at a film formation temperature of 150°C or below and the gas refrigerant introduction pipe 50 is formed.

Description

Solar cell manufacturing method, in-process solar cell substrate, and solar cell

The present invention relates to a method for manufacturing a solar cell, a work-in-process solar cell substrate, and a solar cell.

In recent years, a back contact type solar cell in which an electrode layer is provided only on the back surface side of a semiconductor substrate has been developed (Patent Document 1).
In this back contact type solar cell, since a pair of electrode layers and different conductive type semiconductor layers are arranged at close positions, it is necessary to pattern the pair of electrode layers and different conductive type semiconductor layers with high accuracy. ..

Therefore, as a method of patterning with high accuracy, Patent Document 1 discloses a method of patterning a semiconductor layer by using lift-off.

Japanese Unexamined Patent Publication No. 2013-128063

By the way, in order to reduce the manufacturing cost of solar cells, it is necessary to form a large number of solar cells at the same time. Therefore, the present inventor, referring to the lift-off method of Patent Document 1, simultaneously forms a lift-off layer with a silicon oxide layer on a plurality of substrates by a plasma CVD apparatus having a large area (length 1200 mm × width 1000 mm). A back contact type solar cell was prototyped.
However, with the prototype lift-off method, although good quality solar cells can be obtained when forming a film in a small area, the film thickness distribution between substrates becomes large when forming a film in a large area, resulting in quality. There was a problem that the yield was poor due to the bias.

Therefore, an object of the present invention is to provide a method for manufacturing a solar cell and a solar cell, which are easier to mass-produce than the conventional ones and have a good yield.
An object of the present invention is to provide a work-in-process solar cell substrate that can be lifted off more efficiently and the manufacturing efficiency can be improved as compared with the conventional case in manufacturing a solar cell.

One aspect of the present invention for solving the above-mentioned problems is provided with a monoconductive semiconductor layer, a reverse conductive semiconductor layer, a first electrode layer, and a second electrode layer on the first main surface side of the semiconductor substrate. A method for manufacturing a solar cell, in which the monoconductive semiconductor layer is interposed between the semiconductor substrate and the first electrode layer, and the reverse conductive semiconductor layer is interposed between the semiconductor substrate and the second electrode layer. The first semiconductor layer forming step of forming the reverse conductive semiconductor layer on the first main surface side of the semiconductor substrate and the lift-off containing silicon oxide or silicon nitride as a main component on the reverse conductive semiconductor layer. A lift-off layer forming step of forming a layer, and a second semiconductor layer forming step of forming the monoconductive semiconductor layer so that a part of the semiconductor substrate overlaps with the lift-off layer when viewed in a plan view. The lift-off step of removing the overlapping portion of the monoconductive semiconductor layer by dissolving the lift-off layer with a lift-off liquid is included, and in the lift-off layer forming step, the first reaction gas is applied at a film forming temperature of 150 ° C. or lower. This is a method for manufacturing a solar cell, in which the lift-off layer is formed by spraying.

The "uniconductive type" here means an n-type or a p-type, and the "reverse conductive type" is a conductive type opposite to the one-conductive type, that is, when the one-conductive type is an n-type. It refers to a p-type, and when the one-conductive type is a p-type, it refers to an n-type.
The "main component" here means a component that accounts for 50% or more of all components.

According to this aspect, since the monoconductive semiconductor layer can be patterned by dissolving the lift-off layer with the lift-off liquid, it can be manufactured at a lower cost than the conventional method of patterning with a photoresist.
According to this aspect, since a lift-off layer containing silicon oxide or silicon nitride as a main component is formed at a film forming temperature of 150 ° C. or less, the in-plane film thickness distribution is uniform even in a large-area film forming apparatus. Can form a coarse lift-off layer. Therefore, mass production is possible, and a lift-off layer having a high etching rate by the lift-off liquid can be easily formed.

A preferable aspect includes a protective layer forming step of forming a protective layer on the lift-off layer, and the protective layer contains silicon oxide or silicon nitride as a main component and has a higher density than the lift-off layer.

Preferred aspects are a resist layer forming step of forming a resist layer having a predetermined shape on the outside of the reverse conductive semiconductor layer with reference to the semiconductor substrate, and etching for removing a part of the reverse conductive semiconductor layer with an etching solution. In the resist layer forming step, which includes a step and a resist layer removing step of removing the resist layer, when the semiconductor substrate is viewed in a plan view, a non-overlapping portion that does not overlap with the resist layer is formed on the reverse conductive semiconductor layer. Yes, in the etching step, a part or all of the non-superimposed portion of the reverse conductive semiconductor layer is removed.

By the way, when the silicon oxide layer is usually formed at a high temperature (for example, 180 ° C. or higher), when the raw material gas is diluted with hydrogen, the number of hydrogen atoms taken into the film increases. Therefore, the present inventor thought that a sparse film would be formed by diluting the raw material gas with hydrogen even when the film was formed at a low temperature (150 ° C. or lower). However, when the silicon oxide layer was actually formed at a low temperature with a hydrogen-diluted raw material gas, a dense film was unexpectedly formed.

A preferable aspect derived from this result includes a protective layer forming step of forming a protective layer containing silicon oxide as a main component on the lift-off layer, and in the protective layer forming step, a second reaction is carried out at a temperature of 150 ° C. or lower. The protective layer is formed by spraying a gas, and the second reaction gas contains silane gas, carbon dioxide, and hydrogen gas.

According to this aspect, since the protective layer is formed at a low temperature using the second reaction gas diluted with hydrogen gas, a dense protective layer can be easily formed.

The preferred aspect is that the second reaction gas has a flow rate ratio of hydrogen gas to silane gas of 50 or more.

By the way, when a plurality of layers are continuously formed in the same film forming chamber, the film is formed by forming a film under high temperature conditions (for example, 180 ° C. or higher) and then under low temperature conditions (for example, 150 ° C. or lower). It needs to be cooled until the temperature of the membrane chamber reaches low temperature conditions. Similarly, when the film is formed under the high temperature condition after the film is formed under the low temperature condition, it is necessary to heat the film until the temperature of the film forming chamber reaches the high temperature condition.
Here, in the film forming apparatus, the time for raising the temperature from the low temperature condition to the high temperature condition is generally shorter than the time for lowering the temperature from the high temperature condition to the low temperature condition.

Therefore, the preferred aspect is that the film forming temperature of the protective layer in the protective layer forming step is substantially equal to or higher than the film forming temperature of the lift-off layer in the lift-off layer forming step, and the film forming temperature of the protective layer is substantially higher than that in the lift-off layer forming step. The temperature difference from the film forming temperature of the lift-off layer is 50 ° C. or less.

Here, "the film forming temperature of the protective layer is substantially equal to or higher than the film forming temperature of the lift-off layer" means a slight temperature fluctuation of the film forming temperature during film forming due to the outside air, the performance of the device, etc. (for example, 3). ℃) is allowed. For example, it includes the case where the film forming temperature of the protective layer becomes (the film forming temperature of the lift-off layer -3 ° C) or higher.

According to this aspect, film formation can be performed efficiently and continuously.

One aspect of the present invention includes a one-conductive semiconductor layer, a reverse conductivity type semiconductor layer, a first electrode layer, and a second electrode layer on the first main surface side of the semiconductor substrate, and the semiconductor substrate and the first electrode layer are provided. A method for manufacturing a solar cell in which the one conductive semiconductor layer is interposed between the electrode layers and the reverse conductive semiconductor layer is interposed between the semiconductor substrate and the second electrode layer. A first semiconductor layer forming step of forming the reverse conductive semiconductor layer on the first main surface side, and a lift-off layer forming step of forming a lift-off layer containing silicon oxide or silicon nitride as a main component on the reverse conductive semiconductor layer. A protective layer forming step of forming a protective layer containing silicon oxide or silicon nitride as a main component on the lift-off layer and having a density higher than that of the lift-off layer, and the lift-off layer when the semiconductor substrate is viewed in a plan view. A second semiconductor layer forming step of forming the one-conductive semiconductor layer so as to have an overlapping portion with the above, and a lift-off for removing the overlapping portion of the one-conductive semiconductor layer by dissolving the lift-off layer with a lift-off liquid. The lift-off step includes a step, and the lift-off step is performed after the protective layer forming step. In the protective layer forming step, a second reaction gas is sprayed at a temperature of 150 ° C. or lower to form the protective layer. The second reaction gas is a method for producing a solar cell, which comprises silane gas, carbon dioxide, and hydrogen gas, and has a flow rate ratio of hydrogen gas to silane gas of 50 or more.

According to this aspect, since the monoconductive semiconductor layer can be patterned by dissolving the lift-off layer with the lift-off liquid, the manufacturing process can be simplified and the cost is low as compared with the conventional method of patterning with a photoresist. Can be manufactured at.
According to this aspect, in the protective layer forming step, the protective layer is formed with the second reaction gas at 150 ° C. or lower and the silane gas is diluted with hydrogen gas, so that a dense protective layer can be formed.

Here, in the manufacturing process of solar cells in recent years, it may be manufactured not only at one base but at multiple bases. That is, there is a case where a work-in-process solar cell substrate, which is a work-in-process product of a solar cell, is manufactured at one base, and a solar cell is manufactured using the work-in-process solar cell board at another base. Therefore, not only the structure of the finished product but also the structure of the work-in-process solar cell substrate, which is a work-in-process, is important for mass production of solar cells.

One aspect of the present invention is a work-in-progress solar cell substrate provided with a monoconductive semiconductor layer and a reverse conductive semiconductor layer on the first main surface side of the semiconductor substrate, and the reverse of the semiconductor substrate is used as a reference. The lift-off layer has a lift-off layer on the outside of the conductive semiconductor layer, and the one-conductive semiconductor layer is laminated on the outside of the lift-off layer with the semiconductor substrate as a reference, and the one-conductive semiconductor layer is the semiconductor substrate. There is an overlapping portion with the lift-off layer when viewed in a plan view, and the lift-off layer can be dissolved and removed from the overlapping portion of the monoconductive semiconductor layer by immersing the lift-off layer in the lift-off liquid. This is a work-in-process solar cell substrate containing silicon oxide as a main component and having an etching rate of 5 nm / s or more when immersed in 2% by weight of hydrofluoric acid.

According to this aspect, it is possible to lift off efficiently and improve manufacturing efficiency.

A preferable aspect is that the protective layer has a protective layer on the lift-off layer, and the protective layer contains silicon oxide or silicon nitride as a main component and has a higher density than the lift-off layer.

By the way, as a result of repeated studies by the present inventor, the following was discovered. That is, the refractive index of silicon oxide tends to increase as the density increases, and the refractive index tends to decrease as the density decreases. Further, the etching rate of silicon oxide tends to increase as the density increases, and the etching rate of hydrofluoric acid tends to decrease as the density decreases.
Therefore, when the present inventor examined the correlation between the refractive index and the etching rate of hydrofluoric acid in silicon oxide, a certain correlation was found between the refractive index and the etching rate of hydrofluoric acid. It was discovered that by setting the refractive index in the range, it is etched well and can be lifted off efficiently.

A preferable aspect is that the protective layer has a protective layer on the lift-off layer, and the protective layer contains silicon oxide as a main component and has a refractive index higher than that of the lift-off layer.

According to this aspect, the etching rate of the protective layer can be made slower than the etching rate of the lift-off layer.

One aspect of the present invention is a working solar cell substrate provided with a conductive semiconductor layer on the first main surface side of the semiconductor substrate, and a lift-off layer outside the conductive semiconductor layer with the semiconductor substrate as a reference. The protective layer is laminated in this order, and the lift-off layer contains silicon oxide as a main component and has an etching rate of 5 nm / s or more when immersed in 2% by weight of hydrofluoric acid. , Silicon oxide or silicon nitride as a main component, and has a higher density than the lift-off layer.

According to this aspect, it is possible to lift off efficiently and improve manufacturing efficiency.

A preferred aspect is that the outermost surface of the semiconductor substrate on the second main surface side is coated with a second protective layer having a slower etching rate when immersed in 2% by weight of hydrofluoric acid than the lift-off layer. is there.

Further, in the above aspect, the outermost surface of the semiconductor substrate on the second main surface side may be coated with a second protective layer having more resistance to the lift-off liquid than the lift-off layer.

One aspect of the present invention includes a one-conductive semiconductor layer, a reverse-conductivity semiconductor layer, a first electrode layer, and a second electrode layer on the first main surface side of the semiconductor substrate, and the semiconductor substrate and the first electrode layer are provided. A solar cell in which the one-conducting semiconductor layer is interposed between the electrode layers and the reverse-conducting semiconductor layer is interposed between the semiconductor substrate and the second electrode layer, and has an intrinsic semiconductor layer. The intrinsic semiconductor layer is interposed between the semiconductor substrate, the monoconductive semiconductor layer and the reverse conductive semiconductor layer, respectively, and further, in the spreading direction of the first main surface of the semiconductor substrate, the one. It is also interposed between the conductive semiconductor layer and the reverse conductive semiconductor layer, and the intrinsic semiconductor layer is formed in a direction orthogonal to the first main surface from between the monoconductive semiconductor layer and the reverse conductive semiconductor layer. It is a solar cell that is exposed to.

According to this aspect, the intrinsic semiconductor layer can prevent the contact between the electrode layers and the semiconductor layers having different conductive types, so that the solar cell has excellent safety.
According to this aspect, mass production is easy because it can be formed by the manufacturing method of the above-mentioned aspect.

In a preferred aspect, the intrinsic semiconductor layer is composed of a first intrinsic layer and a second intrinsic layer, and the first intrinsic layer is interposed between the semiconductor substrate and the reverse conductive semiconductor layer. The second intrinsic layer is interposed between the semiconductor substrate and the monoconductive semiconductor layer, and the second intrinsic layer covers the outside of the reverse conductive semiconductor layer with reference to the semiconductor substrate. That is not the case.

A more preferable aspect is that the second intrinsic layer is located flush with the outer surface of the reverse conductive semiconductor layer or inside the outer surface with respect to the semiconductor substrate.

According to the method for manufacturing a solar cell and the solar cell of the present invention, mass production is easier and the yield is better than before.
According to the in-process solar cell substrate of the present invention, in manufacturing a solar cell, it is possible to lift off more efficiently and improve the manufacturing efficiency as compared with the conventional case.

It is a perspective view which shows typically the solar cell of 1st Embodiment of this invention. It is the AA sectional view of the solar cell of FIG. 1, and the hatching is omitted for easy understanding. It is explanatory drawing of the solar cell of FIG. 1, and is the exploded perspective view which disassembled the 1st electrode layer and the 2nd electrode layer from the solar cell. It is explanatory drawing of the manufacturing method of the solar cell of FIG. 1, (a) shows the cross-sectional view in the 1st intrinsic semiconductor layer forming step, and (b) shows the cross-sectional view in the 1st semiconductor layer forming step. In addition, only the layer formed in each step is shown by hatching, and the remaining hatching is omitted. It is explanatory drawing of the process which follows each process of FIG. 4 of the manufacturing method of the solar cell of FIG. 1, (a) shows the sectional view in the lift-off layer forming process, (b) is the sectional view in the 1st protective layer forming process. (C) represents a cross-sectional view in the second protective layer forming step. In addition, only the layer formed in each step is shown by hatching, and the remaining hatching is omitted. It is explanatory drawing of the process which follows each process of FIG. 5 of the manufacturing method of the solar cell of FIG. 1, (a) shows the sectional view in the resist layer forming process, (b) shows the sectional view in the etching process, (a). c) represents a cross-sectional view in the resist layer removing step. In addition, only the layer formed in each step is shown by hatching, and the remaining hatching is omitted. It is explanatory drawing of the process which follows each process of FIG. 6 of the manufacturing method of the solar cell of FIG. 1, (a) shows the sectional view in the 2nd intrinsic semiconductor layer forming process, (b) is the 2nd semiconductor layer forming process. (C) represents a cross-sectional view in the lift-off process. In addition, only the layer formed in each step is shown by hatching, and the remaining hatching is omitted. It is explanatory drawing of the process which follows each process of FIG. 7 of the manufacturing method of the solar cell of FIG. 1, (a) shows the sectional view in the antireflection layer forming process, (b) is the sectional view in the transparent electrode layer forming process. (C) represents a cross-sectional view in the metal electrode layer forming step. In addition, only the layer formed in each step is shown by hatching, and the remaining hatching is omitted. It is explanatory drawing of the tray used for the measurement of the Example and the comparative example of this invention.

Hereinafter, embodiments of the present invention will be described in detail. Regarding the front and back, the light receiving surface side is the front side and the opposite side is the back side.

The solar cell 1 of the first embodiment of the present invention is a back contact type solar cell, and as shown in FIG. 1, a pair on the back side main surface 26 (first main surface) side of the semiconductor substrate 5 serving as a support substrate. The electrode layers 2 and 3 are formed, and the electrode layers 2 and 3 are not formed on the front main surface 25 (second main surface) side. The solar cell 1 of the present embodiment is also a heterojunction type solar cell.

In the solar cell 1, as shown in FIG. 1, the first intrinsic semiconductor layer 6 and the antireflection layer 7 are laminated in this order on the front main surface 25 side of the semiconductor substrate 5.
In the solar cell 1, a second intrinsic semiconductor layer 10 (second intrinsic layer), a monoconductive semiconductor layer 11, and a first electrode layer 2 are laminated on a part of the back side main surface 26 side of the semiconductor substrate 5, and the semiconductor is a semiconductor. The third intrinsic semiconductor layer 15 (first intrinsic layer), the reverse conductive semiconductor layer 16, and the second electrode layer 3 are laminated on the other portion on the back side main surface 26 side of the substrate 5.
In the solar cell 1, as shown in FIG. 2, the second intrinsic semiconductor layer 10 is interposed between the monoconductive semiconductor layer 11 and the inverse conductive semiconductor layer 16 in the vertical direction Y.

As shown in FIG. 1, the solar cell 1 has a substantially square shape and has four sides orthogonal to each other. That is, the solar cell 1 has a horizontal side extending in the horizontal direction X and a vertical side extending in the vertical direction Y.

As shown in FIG. 3, the electrode layers 2 and 3 are collector electrodes that extract electricity from the semiconductor layers 11 and 16, and both have a comb shape when viewed from the back surface and have an intricate shape.
That is, the first electrode layer 2 includes a first bus bar electrode portion 40 and a first finger electrode portion 41, and the first finger electrode portion 41 with respect to the first bus bar electrode portion 40 to the first bus bar electrode portion 40. Extends in the direction orthogonal to each other.
Similarly, the second electrode layer 3 includes a second bus bar electrode portion 45 and a second finger electrode portion 46, and the second finger electrode portion 46 relates to the second bus bar electrode portion 45 to the second bus bar electrode portion 45. Extends in the direction orthogonal to each other.

The bus bar electrode portions 40 and 45 extend in the vertical direction Y along the vertical side and are parallel to each other in the horizontal direction X when viewed from the back surface.
The finger electrode portions 41 and 46 extend intricately with each other in the lateral direction X.
That is, the first finger electrode portion 41 extends linearly in the lateral direction X from the first bus bar electrode portion 40 toward the second bus bar electrode portion 45, and the second finger electrode portion 46 extends from the second bus bar electrode portion 45. It extends linearly in the lateral direction X toward the first bus bar electrode portion 40. The finger electrode portions 41 and 46 are alternately arranged in the vertical direction Y.

As shown in FIG. 2, the electrode layers 2 and 3 have a multilayer structure in which transparent electrode layers 20 and 21 and metal electrode layers 22 and 23 are laminated in this order from the semiconductor substrate 5 side. The electrode layers 2 and 3 may have a single layer structure consisting of only the metal electrode layers 22 and 23, or may have a single layer structure containing only the transparent electrode layers 20 and 21.

As shown in FIG. 3, the semiconductor layers 11 and 16 form a base for the electrode layers 2 and 3, and when viewed from the back surface, they are both comb-shaped and have an intricate shape like the electrode layers 2 and 3. ing.
When viewed from the back side, a meandering separation groove 35 is formed between the monoconductive semiconductor layer 11 and the reverse conductive semiconductor layer 16, and a second intrinsic semiconductor layer serving as a base for the monoconductive semiconductor layer 11 is formed. 10 is filled in the separation groove 35. That is, the monoconductive semiconductor layer 11 and the reverse conductive semiconductor layer 16 are electrically insulated by the second intrinsic semiconductor layer 10 in the spreading direction of the semiconductor substrate 5.
The second intrinsic semiconductor layer 10 is exposed from between the monoconductive semiconductor layer 11 and the reverse conductive semiconductor layer 16 in the thickness direction (orthogonal direction with respect to the back side main surface 26 of the semiconductor substrate 5). That is, the monoconductive semiconductor layer 11 does not overlap with the reverse conductive semiconductor layer 16 in the thickness direction of the semiconductor substrate 5, and the reverse conductive semiconductor layer 16 also does not overlap with the monoconductive semiconductor layer 11.

Subsequently, the manufacturing method of the solar cell 1 of the present embodiment will be described. The description of the same as the conventional one will be omitted.

The solar cell 1 of the present embodiment is manufactured at one or more manufacturing bases.
The solar cell 1 of the present embodiment is manufactured via the first work-in-process solar cell substrate 99 and the second work-in-process solar cell substrate 100.

First, as shown in FIG. 4A, the first intrinsic semiconductor layer 6 is formed on the front side main surface 25 of the semiconductor substrate 5 by the plasma CVD apparatus, and the third intrinsic semiconductor layer 15 is formed on the back side main surface 26. Film formation (first intrinsic semiconductor forming step).

Subsequently, as shown in FIG. 4B, the reverse conductive semiconductor layer 16 is formed on the third intrinsic semiconductor layer 15 by the same or different plasma CVD apparatus as the above step (first semiconductor layer forming step).

Subsequently, as shown in FIG. 5A, the lift-off layer 50 is formed by spraying the first reaction gas onto the reverse conductive semiconductor layer 16 by the same or different plasma CVD apparatus as in the above step (lift-off layer forming step). ).

The film thickness of the lift-off layer 50 formed in the lift-off layer forming step is preferably 10 nm or more and 150 nm or less.
Within this range, the lifting-off etching solution described later is likely to be impregnated and lift-off is likely to occur.
Further, as the film forming conditions at this time, it is preferable to satisfy the following conditions.
The substrate temperature (film formation temperature) is 150 ° C. or lower, preferably 100 ° C. or higher and 140 ° C. or lower.
The pressure is preferably 180 Pa or more and 220 Pa or less.
Power density is preferably 0.01 W / cm ² or more 1.00 W / cm ² or less.
Components of the first reaction gas, silane gas and (SiH _4), carbon dioxide (CO ₂₎ comprises, (flow ratio of CO ₂ when the flow rate of SiH ₄ and 1) flow rate ratio of CO ₂ with respect to SiH ₄ is It is preferably 10 or more and 400 or less.
The lift-off layer 50 is preferably formed so as to overlap the entire reverse conductive semiconductor layer 16 when the semiconductor substrate 5 is viewed in a plan view.
The lift-off layer 50 is preferably formed in a range of 90% or more of the area of the semiconductor substrate 5 when the semiconductor substrate 5 is viewed in a plan view.

Subsequently, as shown in FIG. 5B, the second reaction gas is sprayed onto the lift-off layer 50 to form the first protective layer 51 in the film-forming chamber of the same plasma CVD apparatus continuously from the lift-off layer forming step. (First protective layer forming step).

The film thickness of the first protective layer 51 formed in the first protective layer forming step is thicker than the film thickness of the lift-off layer 50, and is preferably 200 nm or more and 400 nm or less.
Within this range, it is possible to prevent the lift-off layer 50 from being dissolved in the resist removing solution described later.
Further, as the film forming conditions at this time, it is preferable to satisfy the following conditions.
The substrate temperature (film formation temperature) is 150 ° C. or lower, preferably 100 ° C. or higher and 140 ° C. or lower.
It is preferable that the film-forming temperature of the first protective layer 51 at the time of film-forming is substantially equal to or higher than the film-forming temperature of the lift-off layer 50.
Further, the film forming temperature of the first protective layer 51 at the time of film formation preferably has a temperature difference of 50 ° C. or less from the film formation temperature of the lift-off layer 50 at the time of film formation, and more preferably 20 ° C. or less. It is preferably 5 ° C. or lower, and particularly preferably 5 ° C. or lower.
Within this range, the temperature can be raised quickly, so that film can be continuously formed in the film forming chamber of the same plasma CVD apparatus.
The pressure is preferably 180 Pa or more and 220 Pa or less.
Power density is preferably 0.01 W / cm ² or more 1.00 W / cm ² or less.
The second reaction gas, a silane gas (SiH _4), and carbon dioxide (CO _2), and includes a hydrogen gas (H _2), flow ratio of CO ₂ with respect to SiH ₄ (SiH ₄ to 1 and the of CO ₂ when flow ratio) is 100 or less 1 or more, the flow rate ratio of H ₂ to SiH ₄ (flow ratio of H ₂ when the SiH ₄ to 1) is preferable 50 to 300.
Within this range, a dense first protective layer 51 can be formed.
The first protective layer 51 is preferably formed so as to overlap the entire lift-off layer 50 when the semiconductor substrate 5 is viewed in a plan view.
The first protective layer 51 is preferably formed in a range of 90% or more of the area of the semiconductor substrate 5 when the semiconductor substrate 5 is viewed in a plan view.

Subsequently, as shown in FIG. 5C, the third reaction gas is sprayed onto the first intrinsic semiconductor layer 6 in the film forming chamber of the same plasma CVD apparatus continuously from the lift-off layer forming step, and the second protective layer 52 (2nd protective layer forming step).
That is, in the second protective layer forming step, the second protective layer 52 is formed on the outermost surface on the front side, and the first work-in-process solar cell substrate 99 is formed.

The film thickness of the second protective layer 52 formed in the second protective layer forming step is thicker than the film thickness of the lift-off layer 50, and is preferably 10 nm or more and 200 nm or less.
Further, as the film forming conditions at this time, it is preferable to satisfy the following conditions.
The substrate temperature (film formation temperature) is 150 ° C. or lower, preferably 100 ° C. or higher and 140 ° C. or lower.
It is preferable that the film-forming temperature of the second protective layer 52 at the time of film-forming is substantially equal to or higher than the film-forming temperature of the lift-off layer 50.
The temperature difference between the film forming temperature of the second protective layer 52 and the film forming temperature of the first protective layer 51 at the time of film forming is preferably 50 ° C. or less, and more preferably 20 ° C. or less. It is preferably 5 ° C. or lower, and particularly preferably 5 ° C. or lower.
Within this range, the temperature can be adjusted quickly, so that the film can be continuously formed in the film forming chamber of the same plasma CVD apparatus.
The pressure is preferably 180 Pa or more and 220 Pa or less.
Power density is preferably 0.01 W / cm ² or more 1.00 W / cm ² or less.
The third reaction gas, a silane gas (SiH _4), and carbon dioxide (CO _2), and includes a hydrogen gas (H _2), flow ratio of CO ₂ with respect to SiH ₄ (SiH ₄ to 1 and the of CO ₂ when flow ratio) is 1 or more 400 or less, preferably the flow rate ratio of H ₂ to SiH ₄ (flow ratio of H ₂ when the SiH ₄ 1) is more than 0 and 300 or less.
The second protective layer 52 is preferably formed in a range of 90% or more of the area of the semiconductor substrate 5 when the semiconductor substrate 5 is viewed in a plan view.

Then, if necessary, the first in-process solar cell substrate 99 is moved to another base (for example, another building or another room), and as shown in FIG. 6A, the first in-process solar cell is printed by screen printing or the like. A comb-patterned liquid resist material was applied onto the first protective layer 51 of the substrate 99, a liquid resist material was further applied onto the second protective layer 52, and the resist material was applied to both sides. The substrate is heat-treated and dried to form resist layers 55 and 56 (resist layer forming step).

At this time, on the first protective layer 51, a portion where the resist material is applied and the resist layer 55 is formed (resist forming region 60) and a portion where the resist material is not applied and the resist layer 55 is not formed (resist). There is a non-forming region 61). That is, on the substrate after the resist layer forming step, in the thickness direction, the superposed portion (resist forming region 60) in which the resist layer 55 is superposed on the reverse conductive semiconductor layer 16 and the non-superimposed portion in which the resist layer 55 is not superposed are not superposed. There is a portion (resist non-forming region 61).

As shown in FIG. 6B, the substrate on which the resist layers 55 and 56 are formed is immersed in a resist etching solution (etching solution), and the non-overlapping portion (resist non-forming region 61) in which the resist layer 55 is not formed is immersed. The third intrinsic semiconductor layer 15, the reverse conductive semiconductor layer 16, the lift-off layer 50, and the first protective layer 51 are removed in part or all (etching step).

As the etching solution for resist used at this time, for example, a mixed solution of hydrofluoric acid and nitric acid (fluoric acid) or a solution containing ozone and hydrofluoric acid can be used.
At this time, in the semiconductor substrate 5, a peeled region 62 in which the layer on the back side main surface 26 side is peeled off is formed in the resist non-formed region 61.

As shown in FIG. 6C, the resist layers 55 and 56 are removed with a resist removing solution, and the substrate is washed with hydrofluoric acid if necessary (resist layer removing step).

At this time, since the lift-off layer 50 is protected by the first protective layer 51, it is substantially not dissolved, and only the resist layers 55 and 56 are peeled off. Further, even if the base material is washed with hydrofluoric acid, the lift-off layer 50 is not substantially dissolved.

Subsequently, as shown in FIG. 7A, the second intrinsic semiconductor layer 10 is formed on the entire back surface of the main surface by the plasma CVD apparatus (second intrinsic semiconductor layer forming step).
That is, in the second intrinsic semiconductor layer forming step, the second intrinsic semiconductor layer is formed so as to be outside the lift-off layer 50 with reference to the semiconductor substrate 5 and to have a portion overlapping the lift-off layer 50 when the semiconductor substrate 5 is viewed in a plan view. The intrinsic semiconductor layer 10 is formed.

At this time, as shown in FIG. 7A, a part of the second intrinsic semiconductor layer 10 is formed over the first protective layer 51a (51) over the peeling region 62a (62) of the adjacent semiconductor substrate 5. It is formed so as to extend from the peeled region 62a over the adjacent first protective layer 51b.

As shown in FIG. 7B, the monoconductive semiconductor layer 11 is formed on the second intrinsic semiconductor layer 10 by the same or different plasma CVD apparatus to form the second in-process solar cell substrate 100 (second semiconductor layer). Formation process).
That is, in the second semiconductor layer forming step, it is outside the second intrinsic semiconductor layer 10 with reference to the semiconductor substrate 5, and when the semiconductor substrate 5 is viewed in a plan view, it has a portion overlapping with the lift-off layer 50. A conductive semiconductor layer 11 is formed.

If necessary, the second work-in-process solar cell substrate 100 is moved to another base (for example, another building or another room), the second work-in-process solar cell substrate 100 is immersed in a lift-off etching solution (lift-off solution), and FIG. As in (c), the lift-off layer 50 is melted and lifted off, and the layer on the lift-off layer 50 is removed (lift-off step).

As the lift-off etching solution used in the lift-off step, for example, hydrofluoric acid or the like can be used.
At this time, in the second in-process solar cell substrate 100, all the layers in contact with the lift-off layer 50 are melted or peeled off on the back side main surface 26 side of the semiconductor substrate 5, and the second protective layer is on the front side main surface 25 side of the semiconductor substrate 5. 52 is also melted or peeled from the first intrinsic semiconductor layer 6.
Further, at this time, only the inner portion of the second intrinsic semiconductor layer 10 remains from the covering portion of the lift-off layer 50, and does not cover the outer side of the reverse conductive semiconductor layer 16 with reference to the semiconductor substrate 5.
The second intrinsic semiconductor layer 10 is located flush with the outer surface of the reverse conductive semiconductor layer 16 or inside the outer surface with reference to the semiconductor substrate 5.
At this time, the etching rate of the lift-off layer 50 by the lift-off etching solution is faster than the etching rate of the monoconductive semiconductor layer 11.
Further, the etching rate of the second protective layer 52 is faster than the etching rate of the first intrinsic semiconductor layer 6.

As shown in FIG. 8A, the antireflection layer 7 is formed on the first intrinsic semiconductor layer 6 by the plasma CVD apparatus (antireflection layer forming step).

The reaction gas used in the antireflection layer forming step preferably contains silane gas (SiH ₄ ) and ammonia (NH ₃ ).

Subsequently, the electrode layers 2 and 3 are formed on the monoconductive semiconductor layer 11 and the reverse conductive semiconductor layer 16.

Specifically, first, as shown in FIG. 8B, the transparent electrode layers 20 and 21 are formed on the monoconductive semiconductor layer 11 and the reverse conductive semiconductor layer 16 (transparent electrode layer forming step).
In the transparent electrode layer forming step, the transparent electrode layers 20 and 21 are patterned by a photoresist method, a mask method, or the like, and the transparent electrode layer 20 is formed only on the one-conductive semiconductor layer 11 and is a transparent electrode layer. 21 is formed only on the reverse conductive semiconductor layer 16. That is, the transparent electrode layer 20 does not straddle the reverse conductive semiconductor layer 16, and the transparent electrode layer 21 does not straddle the monoconductive semiconductor layer 11.

Next, as shown in FIG. 8C, the metal electrode layers 22 and 23 are formed on the transparent electrode layers 20 and 21 by screen printing or the like (metal electrode layer forming step).
In the metal electrode layer forming step, the metal electrode layer 22 is formed only on the transparent electrode layer 20 by a photoresist method, a mask method, or the like, and the metal electrode layer 23 is formed only on the transparent electrode layer 21. The transparent electrode layer 21 and the metal electrode layer 22 may be patterned at the same time.

Then, if necessary, wiring members such as interconnectors are attached to the electrode layers 2 and 3, and the solar cell 1 is completed.

Next, the detailed configuration of each part constituting the solar cell 1 will be described.

The semiconductor substrate 5 is a semiconductor substrate having either an n-type or a p-type conductive type.
The semiconductor substrate 5 of the present embodiment is a monoconductive semiconductor substrate having a conductive type similar to that of the monoconductive semiconductor layer 11, and is specifically an n-type single crystal silicon substrate.
The average thickness of the semiconductor substrate 5 is preferably 120 μm or more and 250 μm or less, and more preferably 160 μm or more and 200 μm or less.
The semiconductor substrate 5 may have a texture structure on the front side main surface 25 and / or the back side main surface 26, if necessary.

The intrinsic semiconductor layers 6, 10 and 15 are layers that suppress the diffusion of impurities to the semiconductor substrate 5 and passivate the surface. Intrinsic semiconductor layers 6, 10 and 15 are i-type semiconductor layers and are substantially free of conductive impurities.
The term "substantially free of conductive impurities" as used herein means not only those that do not completely contain conductive impurities such as n-type impurities and p-type impurities, but also those that can maintain their functions as an intrinsic layer. It also includes those containing a trace amount of conductive impurities.

The intrinsic semiconductor layers 6, 10 and 15 are not particularly limited as long as they have a function of suppressing the diffusion of impurities to the semiconductor substrate 5 and performing a surface passivation treatment. The intrinsic semiconductor layers 6, 10 and 15 may be, for example, an amorphous silicon-based semiconductor layer or a hydrogenated amorphous silicon-based semiconductor layer.

The average thickness of the intrinsic semiconductor layers 6, 10 and 15 is preferably 2 nm or more and 20 nm or less, and more preferably 5 nm or more and 10 nm or less. Within this range, the resistance can be suppressed low while functioning well as a passivation layer for the semiconductor substrate 5.

The conductive semiconductor layer 11 is a semiconductor layer having an n-type or p-type conductive type, and is a semiconductor layer having the same conductive type as the semiconductor substrate 5.
The one conductive semiconductor layer 11 of the present embodiment is an n-type semiconductor layer in which an n-type dopant (phosphorus or the like) is added to the same semiconductor as the intrinsic semiconductor layers 6, 10 and 15, and specifically, n. It is a type amorphous silicon layer.
The average thickness of the one-conductive semiconductor layer 11 is preferably 2 nm or more and 20 nm or less, and more preferably 5 nm or more and 15 nm or less.

The reverse conductive semiconductor layer 16 is a semiconductor layer having an n-type or p-type conductive type, and is a conductive type semiconductor layer different from the semiconductor substrate 5 and the monoconductive semiconductor layer 11.
The reverse conductive semiconductor layer 16 of the present embodiment is a p-type semiconductor layer in which a p-type dopant (boron or the like) is added to the same semiconductor as the intrinsic semiconductor layers 6, 10 and 15, and specifically, the p-type semiconductor layer. It is an amorphous silicon layer.
The average thickness of the reverse conductive semiconductor layer 16 is preferably 2 nm or more and 20 nm or less, and more preferably 5 nm or more and 15 nm or less.

The antireflection layer 7 is a low reflection layer having translucency and suppressing light reflection.
The antireflection layer 7 can be formed of, for example, a metal oxide such as silicon oxide, zinc oxide, or titanium oxide, or a metal nitride such as silicon nitride.
The antireflection layer 7 is preferably made of silicon nitride from the viewpoint of the light confinement effect of incident light.

The transparent electrode layers 20 and 21 can be formed of, for example, a transparent conductive oxide such as zinc oxide, indium tin oxide (ITO), titanium oxide, tin oxide, tungsten oxide, and molybdenum oxide.
The average thickness of the transparent electrode layers 20 and 21 is preferably 20 nm or more and 200 nm or less, and more preferably 50 nm or more and 150 nm or less.

The metal electrode layers 22 and 23 are layers whose resistivity is smaller than that of the transparent electrode layers 20 and 21 and functions as an auxiliary electrode layer of the transparent electrode layers 20 and 21.
The metal electrode layers 22 and 23 can be formed of, for example, a metal such as gold, silver, copper, platinum, aluminum, nickel, or palladium, or an alloy containing these metals.
The average thickness of the metal electrode layers 22 and 23 is preferably 1 μm or more and 80 μm or less.

Next, the detailed configuration of each part constituting the in-process solar cell substrates 99, 100 will be described. The description of the configuration overlapping with the solar cell 1 will be omitted.

The lift-off layer 50 is a layer that dissolves in the lift-off etching solution.
The lift-off layer 50 preferably contains silicon nitride or silicon oxide as a main component, and silicon nitride or silicon oxide preferably accounts for 90% or more of all the components. The lift-off layer 50 of the present embodiment is a silicon oxide layer containing silicon oxide as a main component.
When the silicon oxide layer is used as the lift-off layer 50, the refractive index is preferably 1.42 or more and 1.50 or less.
The "refractive index" here means the refractive index when irradiated with light of 550 nm.
Within this range, the etching rate with the lift-off etching solution is high, and lift-off is easy.
When a silicon oxide layer is used as the lift-off layer 50, the etching rate when immersed in 2% by weight of hydrofluoric acid is preferably 3 nm / s or more, more preferably 5 nm / s or more. It is more preferably 7 nm / s or more.

The first protective layer 51 is a layer that protects the lift-off layer 50 from hydrofluoric acid used for cleaning before the process of forming the resist etching solution and the second intrinsic semiconductor layer. The first protective layer 51 preferably contains silicon nitride or silicon oxide as a main component, and silicon nitride or silicon oxide preferably accounts for 90% or more of all the components.
Like the lift-off layer 50, the first protective layer 51 of the present embodiment is a silicon oxide layer containing silicon oxide as a main component.
When the silicon oxide layer is used as the first protective layer 51, the refractive index is higher than that of the lift-off layer 50, and is preferably more than 1.50.
Within this range, the etching rate with the resist etching solution and hydrofluoric acid is low, and it is difficult to dissolve.

The second protective layer 52 is more resistant to the resist etching solution and the lift-off etching solution than the lift-off layer 50, and protects the first intrinsic semiconductor layer 6 from the resist etching solution and the lift-off etching solution. ..
The second protective layer 52 preferably contains silicon nitride or silicon oxide as a main component, and silicon nitride or silicon oxide preferably accounts for 90% or more of all the components.
The second protective layer 52 of the present embodiment is a silicon oxide layer containing silicon oxide as a main component, like the lift-off layer 50 and the first protective layer 51.
When the silicon oxide layer is used as the second protective layer 52, the refractive index is higher than that of the lift-off layer 50, and is preferably more than 1.50.

According to the method for manufacturing the solar cell 1 of the present embodiment, the monoconductive semiconductor layer 11 is formed so that a part of the solar cell 1 overlaps with the lift-off layer 50, and the lift-off layer 50 is dissolved by the lift-off liquid to be formed on the lift-off layer 50. The monoconductive semiconductor layer 11 can be removed, and the monoconductive semiconductor layer 11 can be patterned. Therefore, it can be manufactured at a lower cost than the conventional method of patterning with a photoresist.
According to the method for manufacturing the solar cell 1 of the present embodiment, the lift-off layer 50 is formed at a film forming temperature of 150 ° C. or lower, so that the in-plane film thickness distribution is uniform even in a large area film forming apparatus. Lift-off layer 50 can be formed. Therefore, mass production is possible.

According to the method for manufacturing the solar cell 1 of the present embodiment, the first protective layer 51 has a higher density than the lift-off layer 50, and has high resistance to the etching solution for resist. Therefore, when the lift-off layer 50 is immersed in the resist etching solution in the etching step, the lift-off layer 50 is less likely to dissolve than when the lift-off layer 50 is directly immersed in the resist etching solution, and the lift-off layer 50 is formed by the resist etching solution. It dissolves, and it is possible to prevent the layer outside the lift-off layer 50 from peeling off due to the dissolution.

According to the method for manufacturing the solar cell 1 of the present embodiment, when the resist layer 55 patterned in a comb shape is formed on the first protective layer 51 and the semiconductor substrate 5 is viewed in a plan view, the reverse conductive semiconductor layer 16 is formed. The portion where the resist layer 55 does not overlap is dissolved with a resist etching solution, removed, and patterned. Therefore, the reverse conductive semiconductor layer 16 can be patterned without providing a mask or the like when the reverse conductive semiconductor layer 16 is formed.

According to the method for producing the solar cell 1 of the present embodiment, in the protective layer forming step, a second reaction gas containing silane gas, carbon dioxide and hydrogen gas is sprayed at a temperature of 150 ° C. or lower to contain silicon oxide as a main component. The first protective layer 51 is formed. That is, since a low-concentration second reaction gas diluted with hydrogen is sprayed to form a film at a low temperature, a dense first protective layer 51 can be formed.

According to the method for manufacturing the solar cell 1 of the present embodiment, the film forming temperature of the lift-off layer 50 in the lift-off layer forming step and the film forming temperature of the first protective layer 51 in the first protective layer forming step are different in temperature. Is 50 ° C. or lower. Therefore, the temperature can be adjusted quickly, and the lift-off layer 50 and the first protective layer 51 can be continuously formed.
Further, since the temperature difference between the film forming temperature of the first protective layer 51 in the first protective layer forming step and the film forming temperature of the second protective layer 52 in the second protective layer forming step is 50 ° C. or less, The temperature can be adjusted quickly, and the first protective layer 51 and the second protective layer 52 can be continuously formed.

According to the in-process solar cell substrates 99 and 100 of the present embodiment, the lift-off layer 50 contains silicon oxide as a main component and has an etching rate of 5 nm / s or more when immersed in 2% by weight of hydrofluoric acid. , The lift-off layer 50 can be quickly peeled off.

According to the second in-process solar cell substrate 100 of the present embodiment, the lift-off layer 50 is dissolved by being immersed in the lift-off removing solution, and when the semiconductor substrate 5 is viewed in a plan view, the lift-off layer 50 and the lift-off layer 50 of the one-conductive semiconductor layer 11 The overlapping portion can be removed, the lift-off layer 50 contains silicon oxide as a main component, and the refractive index is 1.42 or more and 1.50 or less. Therefore, when the lift is off, the etching rate can be increased, and the monoconductive semiconductor layer 11 can be easily patterned.

According to the second work-in-process solar cell substrate 100 of the present embodiment, the outermost surface of the semiconductor substrate 5 on the front side main surface 25 side is coated with a second protective layer 52 having more resistance to the lift-off liquid than the lift-off layer 50. Therefore, damage to each layer on the second main surface side of the semiconductor substrate 5 due to the lift-off liquid can be suppressed in the etching step.

According to the solar cell 1 of the present embodiment, the monoconductive semiconductor layer 11 and the reverse conductive semiconductor layer 16 do not overlap in the thickness direction, and the contact between the electrode layers 2 and 3 and the semiconductor layers 11 and 16 having different conductive types This can be prevented by the intrinsic semiconductor layers 10 and 15, so that the solar cell has excellent safety.

In the above-described embodiment, the reverse conductive semiconductor layer 16 is a p-type semiconductor layer and the monoconductive semiconductor layer 11 is an n-type semiconductor layer, but the present invention is not limited thereto. The reverse conductive semiconductor layer 16 may be an n-type semiconductor layer, and the one conductive semiconductor layer 11 may be a p-type semiconductor layer.

In the above-described embodiment, the semiconductor substrate 5 is an n-type semiconductor substrate, but the present invention is not limited thereto. The semiconductor substrate 5 may be a p-type semiconductor substrate.

In the above-described embodiment, the lift-off layer 50, the first protective layer 51, and the second protective layer 52 are formed in a film forming chamber of the same plasma CVD apparatus, but the present invention is not limited thereto. .. The film may be formed in a different film forming chamber.

In the above-described embodiment, the first protective layer 51 and the second protective layer 52 are formed by a separate process, but the present invention is not limited to this. The first protective layer 51 and the second protective layer 52 may be formed at the same time.

In the above embodiment, the lift-off layer 50 and the first protective layer 51 are made of the same material, but the present invention is not limited to this. The lift-off layer 50 and the first protective layer 51 may be made of different materials.

In the above-described embodiment, the lift-off layer 50, the first protective layer 51, and the second protective layer 52 are all formed of a silicon oxide layer, but the present invention is not limited thereto. The lift-off layer 50, the first protective layer 51, and the second protective layer 52 may be formed of a silicon nitride layer containing silicon nitride as a main component.

In the above-described embodiment, the lift-off layer 50 is formed by one layer, but the present invention is not limited to this. The lift-off layer 50 may be formed of a laminated body composed of a plurality of layers.

In the above-described embodiment, the first protective layer 51 and the second protective layer 52 are formed by one layer, but the present invention is not limited to this. The first protective layer 51 and the second protective layer 52 may be formed of a laminated body composed of a plurality of layers.

As long as the above-described embodiment is included in the technical scope of the present invention, each component can be freely replaced or added between the respective embodiments.

Hereinafter, the present invention will be specifically described with reference to Examples. The present invention is not limited to the following examples, and the present invention can be appropriately modified without changing the gist thereof.

(Example 1)
First, as shown in FIG. 9, a total of 30 wafers (Nos. 1 to 30 shown in FIG. 9), 5 in length and 6 in width, are mirror-polished silicon wafers (156 in length and width) on a square tray having a length of 998 mm and a width of 1200 mm. .75 mm) was arranged in a vertical and horizontal checkerboard shape, and a silicon oxide layer was formed on these silicon wafers by a plasma CVD apparatus. This was designated as Example 1.
The film forming conditions of the silicon oxide layer of Example 1 were a substrate temperature of 100 ° C., a distance of 10 mm from the electrode to the substrate, a pressure of 200 Pa, a gas flow rate ratio of SiH ₄ : CO ₂ of 25: 4900, and a power density of 0.22 W /. It was set to cm ² .

(Example 2)
The same applies except that the substrate temperature was set to 140 ° C. in Example 1, and this was designated as Example 2.

(Comparative Example 1)
In Example 1, the same was true except that the substrate temperature was set to 180 ° C., and this was designated as Comparative Example 1.

(Example 3)
A silicon oxide layer was formed on a mirror-polished silicon wafer installed on the same tray as in Example 1 by a plasma CVD apparatus, and this was designated as Example 3.
The film forming conditions of the silicon oxide layer of Example 3 are a substrate temperature of 140 ° C., a distance of 10 mm from the electrode to the substrate, a pressure of 200 Pa, a gas flow rate ratio of SiH ₄ : CO ₂ : H ₂ of 150: 4900: 9800, and a power density. Was 0.37 W / cm ² . That is, the film was formed by diluting with hydrogen gas.

(Comparative Example 2)
The same was applied in Example 3 except that it was not diluted with hydrogen, and this was designated as Comparative Example 2. That is, in Comparative Example 2, the film was formed with a gas flow rate ratio of SiH ₄ : CO ₂ of 150: 4900.

The refractive index of silicon oxide on a silicon wafer when irradiated with 550 nm light was measured with an ellipson meter manufactured by JA Woollam for Examples 1 to 3 and Comparative Examples 1 and 2. .. Then, the silicon oxide layer was dissolved with 2% by weight of hydrofluoric acid, the refractive index when irradiated with light of 550 nm was measured again with an ellipson meter, and the etching rate was calculated. Further, in each of the 1st to 30th silicon wafers installed on the tray, the difference between the thickest film thickness (maximum film thickness Max) and the thinnest film thickness (minimum film thickness Min) of the silicon oxide layer on the silicon wafer. Therefore, the in-plane distribution was calculated using the following formula (1).
{(Max-Min) / Min} x 100 ... (1)

In addition, as an evaluation of lift-off property, the degree of peeling of the silicon oxide layer when immersed in an etching solution for 15 minutes and rinsed with a rinsing solution was evaluated. Specifically, the degree of peeling was B for peeling of 50% or more and less than 90% by visual observation, and A for peeling of 90% or more.

The measurement results of Examples 1, 2 and 3 and Comparative Examples 1 and 2 are shown in Tables 1 and 2.

As shown in Table 1, when the silicon oxide layers of Examples 1 and 2 formed at a low temperature and Comparative Example 1 formed at a high temperature were compared, it was found that the etching rate increased as the temperature decreased.
At this time, the silicon oxide layers of Examples 1 and 2 could form a layer having a uniform film thickness even when the film was formed with a tray having a large in-plane distribution of 10% or less in the tray.
Further, it was found that the lift-off characteristics of Examples 1 and 2 were good at 50% or more, and the lift-off characteristics of Example 1 were particularly good as compared with Example 2.

As shown in Table 2, it was found that the silicon oxide layer of Example 3 diluted with hydrogen had a lower etching rate than that of Comparative Example 2 not diluted with hydrogen, and was difficult to dissolve in hydrofluoric acid.

As shown in Tables 1 and 2, the etching rate of the silicon oxide layer of Example 1 is about 9 times the etching rate of the silicon oxide layer of Example 3, and the etching rate of the silicon oxide layer of Example 2 is It was about 6 times the etching rate of the silicon oxide layer of Example 3.
From this, it was found that the etching rate of the silicon oxide layers of Examples 1 and 2 was extremely easy to dissolve by hydrofluoric acid as compared with the silicon oxide layer of Example 3.

From the above results, it was suggested that by forming a film at a substrate temperature of 140 ° C. or lower, a silicon oxide layer having a uniform in-plane distribution controlled to a desired etching rate can be formed even in a large-area film forming apparatus.
It was suggested that a silicon oxide layer having a low refractive index and a high etching rate could be formed by forming a film at a substrate temperature of 140 ° C. or lower under the same film forming conditions other than the substrate temperature.
It was also suggested that by diluting the raw material gas with hydrogen, a dense silicon oxide layer can be formed even when the substrate temperature is 140 ° C. or lower.
From the above, by using the silicon oxide layer of Example 1 or 2 as the lift-off layer and using the silicon oxide layer of Example 3 as the protective layer, the same plasma CVD apparatus is used continuously. It was suggested that the film could be formed.

1 Solar cell 2 1st electrode layer 3 2nd electrode layer 5 Semiconductor substrate 6 1st intrinsic semiconductor layer 10 2nd intrinsic semiconductor layer (intrinsic semiconductor layer, 2nd intrinsic layer)
11 1 Conductive semiconductor layer 15 3rd intrinsic semiconductor layer (intrinsic semiconductor layer, 1st intrinsic layer)
16 Reverse conductive semiconductor layer 25 Front side main surface (second main surface)
26 Back side main surface (first main surface)
50 Lift-off layer 51 1st protective layer 52 2nd protective layer 55,56 Resist layer 60 Resist forming area 61 Non-resist forming area 62 Peeling area 99 1st in-process solar cell substrate 100 2nd in-process solar cell substrate

Claims (15)

1. A monoconductive semiconductor layer, a reverse conductive semiconductor layer, a first electrode layer, and a second electrode layer are provided on the first main surface side of the semiconductor substrate, and the monoconductive is provided between the semiconductor substrate and the first electrode layer. A method for manufacturing a solar cell in which a type semiconductor layer is interposed and the reverse conductive semiconductor layer is further interposed between the semiconductor substrate and the second electrode layer.
   A first semiconductor layer forming step of forming the reverse conductive semiconductor layer on the first main surface side of the semiconductor substrate, and
   A lift-off layer forming step of forming a lift-off layer containing silicon oxide or silicon nitride as a main component on the reverse conductive semiconductor layer,
   A second semiconductor layer forming step of forming the monoconductive semiconductor layer so that a part of the semiconductor substrate overlaps with the lift-off layer when viewed in a plan view.
   A lift-off step of removing the overlapping portion of the monoconductive semiconductor layer by dissolving the lift-off layer with a lift-off liquid is included.
   In the lift-off layer forming step, a method for manufacturing a solar cell, in which the first reaction gas is sprayed at a film forming temperature of 150 ° C. or lower to form the lift-off layer.
2. A protective layer forming step of forming a protective layer on the lift-off layer is included.
   The method for manufacturing a solar cell according to claim 1, wherein the protective layer contains silicon oxide or silicon nitride as a main component and has a higher density than the lift-off layer.
3. A resist layer forming step of forming a resist layer having a predetermined shape on the outside of the reverse conductive semiconductor layer with reference to the semiconductor substrate.
   An etching step of removing a part of the reverse conductive semiconductor layer with an etching solution, and
   Including a resist layer removing step of removing the resist layer.
   In the resist layer forming step, when the semiconductor substrate is viewed in a plan view, the reverse conductive semiconductor layer has a non-overlapping portion that does not overlap with the resist layer.
   The method for manufacturing a solar cell according to claim 1 or 2, wherein in the etching step, a part or all of the non-superimposed portion of the reverse conductive semiconductor layer is removed.
4. A protective layer forming step of forming a protective layer containing silicon oxide as a main component on the lift-off layer is included.
   In the protective layer forming step, the protective layer is formed by spraying a second reaction gas at a temperature of 150 ° C. or lower.
   The method for producing a solar cell according to any one of claims 1 to 3, wherein the second reaction gas contains silane gas, carbon dioxide, and hydrogen gas.
5. The method for manufacturing a solar cell according to claim 4, wherein the second reaction gas has a flow rate ratio of hydrogen gas to silane gas of 50 or more.
6. The film forming temperature of the protective layer in the protective layer forming step is substantially equal to or higher than the film forming temperature of the lift-off layer in the lift-off layer forming step, and the lift-off layer is formed in the lift-off layer forming step. The method for manufacturing a solar cell according to claim 4 or 5, wherein the temperature difference from the film temperature is 50 ° C. or less.
7. A monoconductive semiconductor layer, a reverse conductive semiconductor layer, a first electrode layer, and a second electrode layer are provided on the first main surface side of the semiconductor substrate, and the monoconductive is provided between the semiconductor substrate and the first electrode layer. A method for manufacturing a solar cell in which a type semiconductor layer is interposed and the reverse conductive semiconductor layer is further interposed between the semiconductor substrate and the second electrode layer.
   A first semiconductor layer forming step of forming the reverse conductive semiconductor layer on the first main surface side of the semiconductor substrate, and
   A lift-off layer forming step of forming a lift-off layer containing silicon oxide or silicon nitride as a main component on the reverse conductive semiconductor layer,
   A protective layer forming step of forming a protective layer containing silicon oxide or silicon nitride as a main component on the lift-off layer and having a higher density than the lift-off layer.
   A second semiconductor layer forming step of forming the monoconductive semiconductor layer so as to have a portion overlapping the lift-off layer when the semiconductor substrate is viewed in a plan view.
   A lift-off step of removing the overlapping portion of the monoconductive semiconductor layer by dissolving the lift-off layer with a lift-off liquid is included.
   The lift-off step is performed after the protective layer forming step, and is performed.
   In the protective layer forming step, the protective layer is formed by spraying a second reaction gas at a temperature of 150 ° C. or lower.
   A method for producing a solar cell, wherein the second reaction gas contains silane gas, carbon dioxide, and hydrogen gas, and the flow rate ratio of hydrogen gas to silane gas is 50 or more.
8. A work-in-process solar cell substrate provided with a monoconductive semiconductor layer and a reverse conductive semiconductor layer on the first main surface side of the semiconductor substrate.
   A lift-off layer is provided on the outside of the reverse conductive semiconductor layer with reference to the semiconductor substrate.
   The lift-off layer has the one-conductive semiconductor layer laminated on the outside with the semiconductor substrate as a reference.
   The one-conductive semiconductor layer has a portion that overlaps with the lift-off layer when the semiconductor substrate is viewed in a plan view.
   By immersing the lift-off layer in the lift-off liquid, the lift-off layer can be dissolved and the overlapping portion of the monoconductive semiconductor layer can be removed.
   The lift-off layer is a work-in-process solar cell substrate containing silicon oxide as a main component and having an etching rate of 5 nm / s or more when immersed in 2% by weight of hydrofluoric acid.
9. A protective layer is provided on the lift-off layer.
   The work-in-process solar cell substrate according to claim 8, wherein the protective layer contains silicon oxide or silicon nitride as a main component and has a higher density than the lift-off layer.
10. A protective layer is provided on the lift-off layer.
    The work-in-process solar cell substrate according to claim 8 or 9, wherein the protective layer contains silicon oxide as a main component and has a refractive index higher than that of the lift-off layer.
11. A work-in-process solar cell substrate provided with a conductive semiconductor layer on the first main surface side of the semiconductor substrate.
    A lift-off layer and a protective layer are laminated in this order on the outside of the conductive semiconductor layer with the semiconductor substrate as a reference.
    The lift-off layer contains silicon oxide as a main component and has an etching rate of 5 nm / s or more when immersed in 2% by weight of hydrofluoric acid.
    The protective layer is a work-in-process solar cell substrate containing silicon oxide or silicon nitride as a main component and having a higher density than the lift-off layer.
12. Claims 8 to 11 include a second protective layer on the outermost surface of the semiconductor substrate on the second main surface side, which has a slower etching rate when immersed in 2% by weight of hydrofluoric acid than the lift-off layer. The in-process solar cell substrate according to any one of the above items.
13. A monoconductive semiconductor layer, a reverse conductive semiconductor layer, a first electrode layer, and a second electrode layer are provided on the first main surface side of the semiconductor substrate, and the monoconductive is provided between the semiconductor substrate and the first electrode layer. A solar cell in which a type semiconductor layer is interposed and the reverse conductive type semiconductor layer is further interposed between the semiconductor substrate and the second electrode layer.
    It has an intrinsic semiconductor layer and
    The intrinsic semiconductor layer is interposed between the semiconductor substrate, the monoconductive semiconductor layer and the reverse conductive semiconductor layer, and further, in the spreading direction of the first main surface of the semiconductor substrate, the one. It is also interposed between the conductive semiconductor layer and the reverse conductive semiconductor layer.
    A solar cell in which the intrinsic semiconductor layer is exposed from between the monoconductive semiconductor layer and the reverse conductive semiconductor layer in a direction orthogonal to the first main surface.
14. The intrinsic semiconductor layer is composed of a first intrinsic layer and a second intrinsic layer.
    The first intrinsic layer is interposed between the semiconductor substrate and the reverse conductive semiconductor layer.
    The second intrinsic layer is interposed between the semiconductor substrate and the monoconductive semiconductor layer.
    The solar cell according to claim 13, wherein the second intrinsic layer does not cover the outside of the reverse conductive semiconductor layer with reference to the semiconductor substrate.
15. The solar cell according to claim 14, wherein the second intrinsic layer is located flush with the outer surface of the reverse conductive semiconductor layer or inside the outer surface with respect to the semiconductor substrate.

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