CN113678244A - 氮化硅电路基板及电子部件模块 - Google Patents

氮化硅电路基板及电子部件模块 Download PDF

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Publication number
CN113678244A
CN113678244A CN202080025366.8A CN202080025366A CN113678244A CN 113678244 A CN113678244 A CN 113678244A CN 202080025366 A CN202080025366 A CN 202080025366A CN 113678244 A CN113678244 A CN 113678244A
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silicon nitride
copper layer
substrate
copper
circuit board
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CN202080025366.8A
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矢野清治
寺野克典
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Denka Co Ltd
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Denka Co Ltd
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Publication of CN113678244A publication Critical patent/CN113678244A/zh
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Abstract

本发明提供氮化硅电路基板，其具备氮化硅基板、设置于上述氮化硅基板的一面的第一铜层、和设置于上述氮化硅基板的另一面的第二铜层，上述氮化硅基板的断裂韧性值Kc为5.0MPa·m0.5以上、10.0MPa·m0.5以下，将上述氮化硅基板的线膨胀率设为αB(/℃)、将上述氮化硅基板的杨氏模量设为EB(GPa)、将上述第一铜层的线膨胀率设为αA(/℃)、将上述第二铜层的线膨胀率设为αC(/℃)时，热冲击参数HS1及热冲击参数HS2各自为1.30GPa以上、2.30GPa以下。

Description

氮化硅电路基板及电子部件模块
技术领域
本发明涉及氮化硅电路基板及电子部件模块。
背景技术
作为功率模块等中使用的电路用基板，从导热率、成本、安全性等方面考虑，使用了氧化铝、氧化铍、氮化硅、氮化铝等的陶瓷基板。这些陶瓷基板将铜或铝等的金属电路层、散热层接合，用作电路基板。与以树脂基板、树脂层为绝缘材料的金属基板相比，上述陶瓷基板具有优异的绝缘性及散热性等，因此用作用于搭载高散热性电子部件的基板。
在电梯、车辆、混合动力汽车等这样的功率模块用途中，使用了下述陶瓷电路基板：用钎料在陶瓷基板的表面接合金属电路板，进而在金属电路板的规定位置搭载半导体元件。近年来，随着半导体元件的高集成化、高频率化、高输出化等，来自半导体元件的发热量增加，针对于此，使用了具有高导热率的氮化铝烧结体、氮化硅烧结体等陶瓷基板。其中，特别是作为用于搭载电子部件的陶瓷基板，要求机械可靠性高，机械强度、韧性优异的氮化硅基板受到关注。
另外，在电子部件模块等中，对陶瓷电路基板反复施加热应力，因此，若不能承受该热应力，则陶瓷基板会产生微小裂纹，或者在产生了该微小裂纹的状态下持续施加热负荷循环时，金属电路层会从陶瓷基板剥离，从而导致接合强度不良或热阻不良，存在作为电子设备的动作可靠性降低等问题。
因此，例如，专利文献1记载了使氮化硅基板的断裂韧性值为6.5MPa·m1/2以上的技术。专利文献1中记载的发明公开了通过使用三点抗弯强度为500MPa以上、并且断裂韧性值也高达6.5MPa·m1/2以上的氮化硅基板，能够抑制因热应力产生裂纹。
现有技术文献
专利文献
专利文献1：日本特开2002-201075公报
然而，在电子部件模块等中，高输出化、高集成化不断发展，对陶瓷电路基板反复施加的热应力有进一步增大的倾向，就以往的技术而言，陶瓷基板无法承受热应力，例如，产生微小裂纹，或者金属电路层从陶瓷基板剥离，由此存在发生接合强度不良或热阻不良的情况，在这样的陶瓷电路基板上搭载半导体元件等电子部件而成的电子部件模块的可靠性不充分。
发明内容
发明要解决的课题
鉴于上述课题，本发明的目的在于得到能够提高作为电子部件模块的可靠性·成品率的氮化硅电路基板。
用于解决课题的手段
根据本发明，提供以下所述的氮化硅电路基板及电子部件模块。
即，根据本发明，提供氮化硅电路基板，其具备：
氮化硅基板；
设置于上述氮化硅基板的一面的第一铜层；和
设置于上述氮化硅基板的另一面的第二铜层，
上述氮化硅基板的断裂韧性值Kc为5.0MPa·m0.5以上、10.0MPa·m0.5以下，
将上述氮化硅基板的线膨胀率设为αB(/℃)、将上述氮化硅基板的杨氏模量设为EB(GPa)、将上述第一铜层的线膨胀率设为αA(/℃)、将上述第二铜层的线膨胀率设为αC(/℃)时，
下述式(1)表示的热冲击参数HS1及下述式(2)表示的热冲击参数HS2各自为1.30GPa以上、2.30GPa以下。
式(1) HS1＝(αA-αB)×EB×(350-(-78))
式(2) HS2＝(αC-αB)×EB×(350-(-78))
另外，根据本发明，提供电子部件模块，其具备氮化硅电路基板、搭载于上述氮化硅电路基板上的电子部件、和将上述氮化硅电路基板及上述电子部件密封的密封树脂部，
氮化硅电路基板为上述的氮化硅电路基板。
发明的效果
本发明的氮化硅电路基板以上述方式构成，因此，能够得到施加了热应力时的接合强度不良或热阻不良的发生率低、作为电子设备的可靠性·成品率高的电子部件模块。
附图说明
[图1]为本实施方式涉及的氮化硅电路基板的俯视图。
[图2]为本实施方式涉及的氮化硅电路基板的截面图。
[图3]为本实施方式涉及的电子部件模块的截面图。
[图4]为本实施方式涉及的电子部件模块的一部分的放大截面图。
具体实施方式
以下，对于本发明的实施方式，使用附图进行说明。需要说明的是，所有附图中，对同样的构成要素标注同样的标记，适当省略说明。另外，图为概略图，并不与实际的尺寸比率一致。
首先，对本实施方式的氮化硅基板的构成进行说明。
<本实施方式的氮化硅电路基板的构成>
关于本实施方式的氮化硅电路基板，使用图1及图2进行说明。图1为本实施方式涉及的氮化硅电路基板的俯视图，图2为本实施方式涉及的氮化硅电路基板的截面图。
如图2所示，本实施方式涉及的氮化硅电路基板100具备氮化硅基板10、第一铜层30、和第二铜层20。另外，氮化硅基板10与第二铜层20夹着钎料层12而构成层叠状态，氮化硅基板10与第一铜层30夹着钎料层13而构成层叠状态。
需要说明的是，本实施方式中，所谓“氮化硅-铜复合体”，是指形成电路图案之前的状态，是第一铜层30、钎料层13、氮化硅基板10、钎料层12、和第二铜层20层叠而成的状态。另外，所谓“氮化硅电路基板”，是指在“氮化硅-铜复合体”上形成有电路图案的状态，也可以是在形成有电路图案的铜层的一部分上安装有电子部件40等电子部件的状态。
如前文所述，本实施方式涉及的氮化硅电路基板为具备氮化硅基板10、设置于氮化硅基板10的一面的第一铜层30、和设置于上述氮化硅基板的另一面的第二铜层20的氮化硅电路基板，氮化硅基板10的断裂韧性值Kc为5.0MPa·m0.5以上、10.0MPa·m0.5以下，将氮化硅基板10的线膨胀率设为αB(/℃)、将氮化硅基板10的杨氏模量设为EB(GPa)、将第一铜层30的线膨胀率设为αA(/℃)、将第二铜层20的线膨胀率设为αC(/℃)时，下述式(1)表示的热冲击参数HS1及下述式(2)表示的热冲击参数HS2各自设定为1.30GPa以上、2.30GPa以下。
式(1) HS1＝(αA-αB)×EB×(350-(-78))
式(2) HS2＝(αC-αB)×EB×(350-(-78))
上述式中，HS1及HS2为层叠的氮化硅基板10及第二铜层20、氮化硅基板10及第一铜层30的线膨胀率之差、与氮化硅基板10的杨氏模量、与温度之积，是同氮化硅基板10与第二铜层20之间以及氮化硅基板10与第一铜层30之间可累积的热应力相关联的参数。
例如，作为氮化硅基板10，使用线膨胀率αB＝4.0×10-6(/℃)、杨氏模量EB＝250(GPa)的氮化硅基板，第一铜层30的线膨胀率αA＝17.3×10-6(/℃)、第二铜层20的线膨胀率αC＝17.3×10-6(/℃)时，HS1＝(αA-αB)×EB×(350-(-78))＝1.42(GPa)，HS2＝(αC-αB)×EB×(350-(-78))＝1.42(GPa)。
氮化硅基板10的断裂韧性值Kc更优选为5.5MPa·m0.5以上、9.0MPa·m0.5以下。另外，式(1)表示的热冲击参数HS1及式(2)表示的热冲击参数HS2更优选为1.30GPa以上、1.80GPa以下。
式(1)表示的热冲击参数HS1及式(2)表示的热冲击参数HS2、以及氮化硅基板10的断裂韧性值Kc可以通过对氮化硅电路基板的制造中使用的各构成材料的种类、制造条件等进行控制来调节。
根据本实施方式，通过将上述的热冲击参数HS1及HS2、以及氮化硅基板10的断裂韧性值Kc设定在上述数值范围内，并使氮化硅电路基板中累积的残留应力、和氮化硅基板的裂纹进展的程度为特定的范围，从而成为能够防止因裂纹的进展等产生的破坏、剥落的发生，能够减少制成电子部件模块时的接合强度不良或热阻不良的氮化硅电路基板。
根据后述的实施例的结果可理解，使式(1)表示的热冲击参数HS1及式(2)表示的热冲击参数HS2为1.80GPa以下时，尤其能够得到可提高可靠性·成品率的氮化硅电路基板。
需要说明的是，氮化硅基板10的断裂韧性值Kc可以基于JIS R1607、利用IF法来测定。即，以2kgf向氮化硅基板的表面压入维氏压头，根据维氏压痕的对角线的长度、从各端部延伸的裂纹的长度来评价氮化硅基板的断裂韧性值。
氮化硅基板10、第二铜层20及第一铜层30的线膨胀率(αB、αC、αA、)可基于JIS R1618、利用热机械分析装置(TMA：thermomechanical analyzer)而求出。需要说明的是，本发明中，线膨胀率(αB、αC、αA、)表示各铜板及各氮化硅基板在25℃～400℃时的线膨胀率(线性膨胀系数)。
氮化硅基板10的杨氏模量(EB)可以基于JIS R1602、利用静态挠曲法进行测定。
以下，对本实施方式涉及的氮化硅电路基板的各构成，更详细地进行说明。
<氮化硅基板>
本实施方式涉及的氮化硅基板10具有支撑第一铜层30及第二铜层20的功能。此处，氮化硅基板10从其厚度方向观察时为矩形。另外，氮化硅基板10的厚度被设定为0.2mm以上、1.5mm以下的范围，本实施方式中，设为0.32mm。需要说明的是，氮化硅基板10的形状等为本实施方式中的一例，只要能够发挥本发明涉及的功能，则也可以与本实施方式的情况不同。
如上文所述，本实施方式涉及的氮化硅基板10的断裂韧性值Kc为5.0MPa·m0.5以上、10.0MPa·m0.5以下，更优选为5.5MPa·m0.5以上、9.0MPa·m0.5以下。
另外，本实施方式涉及的氮化硅基板10的杨氏模量EB优选为250GPa以上、320GPa以下，更优选为250GPa以上且小于300GPa。
另外，本实施方式涉及的氮化硅基板10的线膨胀率αB优选为1.5×10-6/℃以上、4.0×10-6/℃以下，更优选为1.5×10-6/℃以上且小于2.5×10-6/℃。
通过将氮化硅基板10的物性调节为上述方式,容易将热冲击参数HS1及HS2调节至上述数值范围内，另外，能够进一步减少接合强度不良或热阻不良。
需要说明的是，氮化硅基板10可利用已知的方法制造，氮化硅基板10的断裂韧性值Kc、杨氏模量EB、线膨胀率αB可通过控制氮化硅基板10的制造方法、具体而言原料的配合、烧成条件(升温速度、保持温度、保持时间、冷却速度等)等来调节。氮化硅基板10的制造方法如后文所述。
<第一铜层及第二铜层>
第一铜层30及第二铜层20从其厚度方向观察时为多边形。第一铜层30及第二铜层20的厚度被设定为0.5mm以上、2.0mm以下的范围，进一步优选为0.8mm以上、1.2mm以下。本实施方式中，作为一例，设为0.8mm。需要说明的是，第一铜层30及第二铜层20的形状等为本实施方式中的一例,只要能够发挥本发明涉及的功能,则也可以与本实施方式的情况不同。
本实施方式涉及的第一铜层30及第二铜层20的线膨胀率根据铜的种类而变化,但不会大幅变化,因此，本实施方式中铜层的线膨胀率为17.3×10-6(/℃)。
通过将第一铜层30及第二铜层20的物性调节为上述方式,从而容易将热冲击参数HS1及HS2调节至上述数值范围内,能够进一步减少接合强度不良或热阻不良。
第一铜层30中的铜晶体的平均晶体粒径优选为50μm以上、500μm以下，更优选为100μm以上、300μm以下。
在如后文所述那样将本实施方式涉及的氮化硅电路基板制成电子部件模块的情况下，介由焊锡层31等接合层在第一铜层30上搭载电子部件40，第一铜层30被焊锡层及电子部件、和氮化硅基板10夹持，承受因与这些材料的热膨胀率差等而产生的热应力，但通过使第一铜层30中的铜晶体的平均晶体粒径在上述数值范围内，能够进一步减少接合强度不良或热阻不良。上述的机理虽不明确，但推测其原因在于，通过使第一铜层30中的铜晶体的平均晶体粒径在上述数值范围内，从而在第一铜层30中铜晶体适度地发生晶界滑动等，应力被适度地缓和。
第二铜层20中的铜晶体的平均晶体粒径优选为50μm以上、500μm以下，更优选为100μm以上、300μm以下。
在如后文所述那样将本实施方式涉及的氮化硅电路基板制成电子部件模块的情况下，介由焊锡层等接合层在第二铜层20上接合散热器，第二铜层20被焊锡层及散热器、和氮化硅基板10夹持，承受因与这些材料的热膨胀率差等而产生的热应力，但通过使第二铜层20中的铜晶体的平均晶体粒径在上述数值范围内，能够进一步减少接合强度不良或热阻不良。上述的机理虽不明确，但推测其原因在于，通过使第二铜层20中的铜晶体的平均晶体粒径在上述数值范围内，从而在第二铜层20中铜晶体适度地发生晶界滑动等，应力被适度地缓和。
需要说明的是，第一铜层30及第二铜层20中的平均晶体粒径可以通过对构成铜层的铜板的种类、及氮化硅电路基板的制造条件等进行控制来调节。
另外，第一铜层30及第二铜层20中的铜晶体的平均晶体粒径可以利用实施例中记载的方法求出。
<钎料层>
本实施方式涉及的钎料层12及钎料层13分别配置在氮化硅基板10与第一铜层30之间、氮化硅基板10与第二铜层20之间，使第一铜层30或第二铜层20接合于氮化硅基板10。钎料层12及钎料层13的厚度典型而言设定在3μm以上、40μm以下的范围内，进一步优选为4μm以上、25μm以下。
需要说明的是，本实施方式涉及的氮化硅电路基板可以在第一铜层30及第二铜层20上具有镀敷层。镀敷层可以由已知的材料形成，例如，可以为Ag、Ni-P。
就钎料层12及钎料层13的组成而言，可以由在钎料中含有选自钛、锆、铪、铌、钽、钒、铝、锡中的至少一种活性金属的银-铜系钎料构成。就Ag、Cu、与Sn或In的配合比而言，可优选举出包含：85.0质量份以上、95.0质量份以下的Ag；5.0质量份以上、13.0质量份以下的Cu；0.4质量份以上、3.5质量份以下的Sn或In。通过设定在上述数值范围内，从而防止钎料的熔解温度过度上升，能够于适度的温度进行接合，能够降低由接合时的热膨胀率差引起的热应力，能够提高耐热循环性。
相对于Ag、Cu、与Sn或In的合计100质量份而言，钛等活性金属的添加量例如可以为1.5质量份以上、5.0质量份以下。通过适当地调节活性金属的添加量，能够进一步提高与陶瓷板的润湿性，能够进一步抑制接合不良的发生。
接下来，使用图3及图4进一步对本实施方式涉及的氮化硅电路基板的实施方式进行说明。图3为本实施方式涉及的电子部件模块的截面图。另外，图4为本实施方式涉及的电子部件模块的一部分的放大截面图。
如上文所述，本实施方式涉及的氮化硅电路基板100为具备氮化硅基板10、设置于氮化硅基板10的一面的第一铜层30、和设置于氮化硅基板10的另一面的第二铜层20的氮化硅电路基板，如图3所示，以被密封树脂部50密封的形态使用。
另外，本实施方式中，第二铜层20的与设置有氮化硅基板10的面呈相反侧的面具有未被密封树脂部50覆盖的未被覆区域。
本实施方式中，氮化硅电路基板可以形成第二铜层20的与设置有氮化硅基板10的面呈相反侧的面直接或介由接合材料层与散热器接合的形态，图3所示的本实施方式的一例中，第二铜层20介由接合材料层21与散热器60接合。
即，本实施方式中，第二铜层20介由接合材料层21与散热器60接合，第二铜层20的与散热器60相对的面具有未被密封树脂部50覆盖的未被覆区域。
根据本实施方式，即使在氮化硅电路基板以还具有被线膨胀率不同的密封树脂部50覆盖的部分及未被覆盖的未被覆区域的形态使用的情况下，以及，即使在氮化硅电路基板中的第二铜层20以还与线膨胀率不同的散热器60接合的形态使用的情况下，通过调节热冲击参数HS1及HS2、以及氮化硅基板10的断裂韧性值，也能够减少接合强度不良或热阻不良。
本实施方式中，第一铜层30是形成为电路图案的铜层。需要说明的是，在第一铜层30上介由焊锡层31而接合有电子部件40，通过外部连接用的引线框架、接合引线(wirebonding)71，使第一铜层30、电子部件40与外部连接端子70连接。本实施方式中，作为一例，示出通过接合引线71与外部连接端子70连接的例子。另外，外部连接端子70也可以不介由接合引线71而直接与基板连接。在该情况下，外部连接端子70例如可以通过焊锡或超声波接合而进行接合。
需要说明的是，电子部件40为半导体元件等电子部件,可以根据所期望的功能选择例如IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极晶体管)、MOSFET(MetalOxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应管)、FWD(Free Wheeling Diode，续流二极管)等各种半导体元件。
另外，将电子部件40接合的焊锡层31例如可以为Sn-Sb系、Sn-Ag系、Sn-Cu系、Sn-In系、或Sn-Ag-Cu系的焊锡材料(所谓的无铅焊锡材料)。
另外，外部连接端子70例如由铜或铜合金形成，接合引线71例如由铜、铜合金、铝、金等形成。
密封树脂部50可以通过使密封树脂部形成用树脂组合物固化而形成。
密封树脂部形成用树脂组合物的种类没有特别限定，可以使用传递模塑用树脂组合物、压缩成型用树脂组合物、液态密封材料等该技术领域中通常使用的树脂组合物。
密封树脂部形成用树脂组合物优选包含热固性树脂，优选包含选自环氧树脂、酚醛树脂、氰酸酯树脂、双马来酰亚胺三嗪树脂、丙烯酸树脂、有机硅树脂中的一种或两种以上，更优选至少包含环氧树脂。
密封树脂部形成用树脂组合物可以还包含固化剂、填充材料等。
作为填充材料，可举出熔融二氧化硅(球状二氧化硅)、晶体二氧化硅、氧化铝、碳化硅、氮化硅、氮化铝、氮化硼、氧化铍、氧化锆等粉体或将它们制成球形而得的珠、玻璃纤维、芳族聚酰胺纤维、碳纤维等。填充材料可以单独使用一种，也可以组合两种以上而使用。作为密封树脂部形成用树脂组合物，例如可以使用加入有SiO2填料的环氧系树脂等。
另外，本实施方式中，第二铜层20为散热器接合用铜层。
本实施方式中，第二铜层20介由接合材料层21与散热器60接合。
需要说明的是，散热器60例如由铝、铜、它们的合金等具有高导热率的材料形成，优选由铝或铝合金形成。
本实施方式涉及的电子部件模块包含上述的氮化硅电路基板。即，本实施方式涉及的电子部件模块具备：氮化硅电路基板；搭载于氮化硅电路基板上的电子部件40；和将氮化硅电路基板100及电子部件40密封的密封树脂部50。
另外，就本实施方式涉及的电子部件模块而言，第二铜层20的与设置有氮化硅基板10的面呈相反侧的面较密封树脂部50更向远离氮化硅基板10的方向凸出。即，如图4所示，将密封树脂部50的、与散热器60相对的面作为密封树脂部下表面51、将第二铜层20的与散热器60对置的面作为第二铜层下表面22时，在密封树脂部下表面51与接合材料层21之间存在高低差，第二铜层下表面22被设计成相对于密封树脂部下表面51而凸出。通过如此设计，在将氮化硅电路基板100与散热器60接合的工序中、也即将第二铜层下表面22(未被密封树脂部50覆盖的未被覆区域)与散热器60接合的工序中，将氮化硅电路基板100与散热器60压接而接触时，最初与散热器60接触的是第二铜层下表面22，因此，密封树脂部50不会妨碍接合，能够顺利地将第二铜层下表面22与散热器60接合，并且能够提高第二铜层20与散热器60的接合的可靠性。
<氮化硅电路基板的制造方法>
本实施方式涉及的氮化硅电路基板可以利用以下的方法制造。
首先，准备具有所期望物性的氮化硅基板10。氮化硅基板10可利用以下的制造方法得到。即，利用球磨机，将包含氮化硅粉末、Y2O3、MgO等烧结助剂的原料粉末、有机溶剂、与根据需要加入的有机粘结剂、增塑剂等均匀地混合，制成原料浆料。将得到的原料浆料脱泡·增稠后，利用刮刀法进行片材成型，得到成型体。将得到的片材成型体切割后，于400～800℃进行脱脂，进而在烧成炉内于1700～1900℃在氮气氛中烧成1～10小时，由此能够得到氮化硅基板10。
此处，氮化硅基板10的断裂韧性值Kc、杨氏模量EB、线膨胀率αB可以通过对氮化硅基板10的制造方法、具体而言原料的配合、烧成条件等制造条件进行控制来调节。虽然也取决于原料的配合、与其他制造条件的平衡，断裂韧性值Kc例如可以通过调节烧成条件(升温速度、保持温度、保持时间、冷却速度等)来控制，作为一例，若提高烧成温度，则断裂韧性值Kc提高，若降低烧成温度，则断裂韧性值Kc降低。另外，杨氏模量EB例如可以通过调节烧成条件(升温速度、保持温度、保持时间、冷却速度等)来控制，作为一例，若提高烧成温度，则杨氏模量EB降低，若降低烧成温度，则杨氏模量EB提高。另外，虽然也取决于与其他制造条件的平衡，线膨胀率αB例如在烧结助剂的添加量增多时变小，在烧结助剂的添加量减少时变大。
接着，在氮化硅基板10的两面印刷形成例如添加有作为活性金属的Ti的Ag-Cu系合金膏作为含有活性金属的钎料，将与氮化硅基板10大致相同的长方形的铜板于600℃～900℃的温度加热接合于两面。此处，作为铜板，优选使用无氧铜板，更优选使用轧制铜板。通过介由钎料在氮化硅基板10的两面接合铜板，从而能够得到氮化硅-铜复合体。
接着，对第一铜层30进行蚀刻处理而形成电路图案。在30的上表面层压光致抗蚀剂(省略图示)。在该情况下，可以涂布液态的光致抗蚀剂。
接着，为了在光致抗蚀剂上形成电路图案，进行以电路图案为基准的图案曝光。在该情况下，可以使形成有电路图案的负型图像的膜紧贴在光致抗蚀剂上，通过所谓的一并曝光而使光致抗蚀剂感光，也可以使用所谓的直描型曝光装置(不使用上述膜)使光致抗蚀剂感光。
接着，依照电路图案对经感光的光致抗蚀剂进行蚀刻。
接着，将残余的光致抗蚀剂除去。
此时，对于第二铜层20，可以不进行蚀刻处理，也可以同样地形成图案。也可以进一步对形成电路图案后的第二铜层20及第一铜层30实施镀敷。
通过以上方式，制造了形成有电路图案的状态的氮化硅电路基板100。
接着，在第一铜层30上，介由焊锡层31搭载电子部件40。本实施方式中，使用例如Sn-Sb系、Sn-Ag系、Sn-In系、或Sn-Ag-Cu系的焊锡材料，将第一铜层30与电子部件40焊锡接合。
接着，利用密封树脂，对电子部件模块进行树脂密封，形成密封树脂部50。树脂密封可以使用已知的方法，例如，可以通过传递模塑进行树脂密封。另外，在树脂密封工序中，例如，在预先将电子部件模块的第二铜层下表面22按压于具有塑性的材料的状态下进行树脂密封，由此能够在第二铜层20的与设置有氮化硅基板10的面呈相反侧的面(即第二铜层下表面22)残留未被密封树脂部50覆盖的未被覆区域，并且能够使第二铜层下表面22相对于密封树脂部下表面51而凸出。
通过上述方式，制作了电子部件模块。
需要说明的是，本发明不限于前述的实施方式，能够实现本发明目的的范围内的变形、改良等包括在本发明中。
实施例
以下，参照实施例对本发明详细地进行说明，但本发明并不受这些实施例的记载任何限定。
利用以下的方法，准备HS1、HS2及断裂韧性值KC不同的多个氮化硅电路基板，进行后述的热循环试验。
<氮化硅基板>
通过调节原料的配合、烧成条件，从而准备了具有各种线膨胀率αB、杨氏模量EB、断裂韧性值KC的氮化硅基板B-1～B-10(148mm×200mm×0.32mm)。
<第一铜层及第二铜层用铜板>
准备线膨胀率为17.3×10-6/℃、厚度为0.8mm的轧制铜板。
<氮化硅电路基板的制造方法>
使用表1所示的组合的氮化硅基板和铜板来制造氮化硅电路基板1～10。
首先，作为钎料(包含活性金属)，准备相对于Ag粉末(福田金属箔粉工业株式会社制：Ag-HWQ 2.5μm)89.5质量份、Cu粉末(福田金属箔粉工业株式会社制：Cu-HWQ 3μm)9.5质量份、Sn粉末(福田金属箔粉工业株式会社制：Sn-HPN 3μm)1.0质量份的合计100质量份包含3.5质量份氢化钛粉末(TOHO TECHNICAL株式会社制：TCH-100)的钎料。
将上述钎料、粘结剂树脂和溶剂混合，得到钎料膏。利用丝网印刷法，将该钎料膏涂布于氮化硅基板的两面，以使得各面处的干燥厚度成为约10μm。
然后，在氮化硅基板的两面上叠合铜板，在1.0×10-3Pa以下的真空中以780℃、30分钟的条件进行加热，利用钎料将氮化硅基板与铜板接合。由此，得到氮化硅基板与铜板经钎料接合而成的氮化硅-铜复合体。进而，在得到的氮化硅-铜复合体的铜层上印刷抗蚀剂，利用氯化铁溶液进行蚀刻而形成电路图案，得到氮化硅电路基板。
针对氮化硅电路基板1，利用下述的方法来评价铜的平均晶体粒径，结果，第一铜层中的铜晶体的平均晶体粒径为250μm，第二铜层中的铜晶体的平均晶体粒径为255μm。
<铜板及氮化硅基板的评价方法>
(1)铜板及氮化硅基板的线膨胀率(αB)
基于JIS R 618，利用热机械分析装置(TMA：thermomechanical analyzer)，对各铜板及各氮化硅基板在25℃～400℃时的线膨胀率(线性膨胀系数)进行测定。
(2)氮化硅基板的杨氏模量(EB)
基于JIS R1602，利用静态挠曲法进行测定。试验片形状为3mm×4mm×40mm。
(3)氮化硅基板的断裂韧性值(KC)
基于JIS R 1607，利用IF法进行测定。即，以2kgf向氮化硅基板的表面压入维氏压头，根据维氏压痕的对角线的长度、从各端部延伸的裂纹的长度，对氮化硅基板的断裂韧性值进行评价。
<铜的平均晶体粒径的评价方法>
利用以下的方法求出氮化硅电路基板中的第一铜层及第二铜层的铜的平均晶体粒径。
首先，通过以下步骤，得到测定用的“截面”。
(1)针对各实施例及比较例中得到的陶瓷电路基板，沿着与主面垂直且从基板的重心通过的截面进行切割。切割中使用带锯。
(2)对经切割的氮化硅电路基板进行树脂包埋，制作树脂包埋体。
(3)使用金刚石磨粒，对制作的树脂包埋体中的复合体截面进行抛光研磨。
针对上述经研磨的氮化硅电路基板截面，利用电子背散射衍射法进行测定。
具体而言，首先，在上述经研磨的第一铜层或第二铜层的大致中心附近处，以15kV的加速电压的条件，在50倍的观察视场中，进行基于电子背散射衍射(EBSD)法的分析，取得数据。EBSD法中，使用株式会社日立高科技制的SU6600型场致发射型扫描显微镜及株式会社TSL Solutions制的分析装置。
利用株式会社TSL Solutions制的软件：OIM Data Analysis 7.3.0将测定数据可视化，制作晶体取向图。利用图像处理软件对该晶体取向图进行分析，由此求出铜层中的铜晶体的平均晶体粒径。
上文中，作为图像处理软件，使用Media Cybernetics公司制的Image-Pro PlusShape Stack版本6.3。需要说明的是，平均晶体粒径的计算中，使用截距法，在一个观察图像上平行地划出10根以上规定长度的直线，得到上述直线横切铜晶粒的部分的直线长度的平均值作为铜晶体的平均晶体粒径(这些是软件自动地处理而算出值)。
<热循环试验及可靠性评价>
首先，将常温(作为一例，为20℃)的试验对象的接合基板移动至150℃的环境内，并在150℃的环境内保持15分钟(第1工序)。
接着，将接合基板从150℃的环境内移动至-55℃的环境内，并在-55℃的环境内保持15分钟(第2工序)。
然后，将第1工序和第2工序交替重复2000次。
接着，通过超声波探伤测定，观察铜层有无剥离。
将评价基准示于以下。
○：未发生剥离。
△：剥离少量发生。
具体而言，以发生了剥离的氮化硅电路基板2为基准，将虽观察到剥离的发生但与氮化硅电路基板2为同等程度、或者虽然观察到剥离的发生但程度比氮化硅电路基板2轻的情况评价为△。
×：剥离大量发生。
具体而言，以观察到剥离的发生的氮化硅电路基板2为基准，将观察到剥离的发生、且发生了比氮化硅电路基板2更多的剥离的情况评价为×。
将评价结果等归纳示于表1。
[表1]
Figure BDA0003281536230000171
如表1所示，在断裂韧性值、以及HS1及HS2被控制在本发明所规定范围内的实施例涉及的氮化硅电路基板中，剥离的发生少，特别是在HS1及HS2为1.80GPa以下的实施例涉及的氮化硅电路基板中，未发生剥离。
由上述内容可理解，为了稳定地得到可靠性高的氮化硅电路基板，构成铜层的材料、氮化硅基板的材料的选择是重要的。
本申请主张以于2019年3月29日提出申请的日本申请特愿2019-066151号为基础的优先权，其全部公开内容并入本文中。
附图标记说明
10 氮化硅基板
12 钎料层
13 钎料层
20 第二铜层
21 接合材料层
22 第二铜层下表面
30 第一铜层
31 焊锡层
40 电子部件
50 密封树脂部
51 密封树脂部下表面
60 散热器
70 外部连接端子
71 接合引线
100 氮化硅电路基板

Claims (12)

1.氮化硅电路基板，其具备：
氮化硅基板；
设置于所述氮化硅基板的一面的第一铜层；和
设置于所述氮化硅基板的另一面的第二铜层，
所述氮化硅基板的断裂韧性值Kc为5.0MPa·m0.5以上、10.0MPa·m0.5以下，
将所述氮化硅基板的线膨胀率设为αB(/℃)、将所述氮化硅基板的杨氏模量设为EB(GPa)、将所述第一铜层的线膨胀率设为αA(/℃)、将所述第二铜层的线膨胀率设为αC(/℃)时，
下述式(1)表示的热冲击参数HS1及下述式(2)表示的热冲击参数HS2各自为1.30GPa以上、2.30GPa以下，
式(1) HS1＝(αA-αB)×EB×(350-(-78))
式(2) HS2＝(αC-αB)×EB×(350-(-78))。
2.如权利要求1所述的氮化硅电路基板，其中，所述第一铜层中的铜晶体的平均晶体粒径为50μm以上、500μm以下。
3.如权利要求1或2所述的氮化硅电路基板，其中，所述第二铜层中的铜晶体的平均晶体粒径为50μm以上、500μm以下。
4.如权利要求1至3中任一项所述的氮化硅电路基板，其中，所述氮化硅基板的杨氏模量EB为250GPa以上、320GPa以下。
5.如权利要求1至4中任一项所述的氮化硅电路基板，其中，所述氮化硅基板的线膨胀率αB为1.5×10-6/℃以上、4.0×10-6/℃以下。
6.如权利要求1至5中任一项所述的氮化硅电路基板，其以经密封树脂部密封的形态被使用。
7.如权利要求6所述的氮化硅电路基板，其中，所述形态为所述第二铜层的与设置有所述氮化硅基板的面呈相反侧的面具有未被所述密封树脂部覆盖的未被覆区域的形态。
8.如权利要求6或7所述的氮化硅电路基板，其中，所述形态为所述第二铜层的与设置有所述氮化硅基板的面呈相反侧的面直接或介由接合材料层与散热器接合的形态。
9.如权利要求1至8中任一项所述的氮化硅电路基板，其中，所述第一铜层是形成为电路图案的铜层。
10.如权利要求1至9中任一项所述的氮化硅电路基板，其中，所述第二铜层为散热器接合用铜层。
11.电子部件模块，其具备：氮化硅电路基板、搭载于所述氮化硅电路基板上的电子部件、和将所述氮化硅电路基板及所述电子部件密封的密封树脂部，
其中，氮化硅电路基板为权利要求1至10中任一项所述的氮化硅电路基板。
12.如权利要求11所述的电子部件模块，其中，所述第二铜层的与设置有所述氮化硅基板的面呈相反侧的面较所述密封树脂部更向远离所述氮化硅基板的方向凸出。
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