CN113594238A - 共集成的高压(hv)和中压(mv)场效应晶体管 - Google Patents

共集成的高压(hv)和中压(mv)场效应晶体管 Download PDF

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CN113594238A
CN113594238A CN202110318832.8A CN202110318832A CN113594238A CN 113594238 A CN113594238 A CN 113594238A CN 202110318832 A CN202110318832 A CN 202110318832A CN 113594238 A CN113594238 A CN 113594238A
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gate dielectric
dielectric layer
soi
region
insulator
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吴楠
T·E·坎姆勒
P·巴尔斯
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Dresden First Mock Exam Co ltd And Two Cos
GlobalFoundries Dresden Module One LLC and Co KG
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Dresden First Mock Exam Co ltd And Two Cos
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Abstract

本公开涉及半导体结构，更具体地，涉及共集成的高压器件和中压器件及其制造方法。该结构包括：衬底，其具有绝缘体上半导体(SOI)区域和体区域；以及第一器件，其形成在体区域上，该第一器件具有第一栅极电介质层和围绕第一电介质层的第二栅极电介质层，第一栅极电介质层和第二栅极电介质层的厚度大于SOI区域的绝缘体层的厚度。

Description

共集成的高压(HV)和中压(MV)场效应晶体管
技术领域
本公开涉及半导体结构，更具体地，涉及共集成的高压和中压器件及其制造方法。
背景技术
包括全耗尽SOI(FDSOI)或射频SOI(RFSOI)的绝缘体上硅(SOI)衬底可用于各种集成电路(IC)应用。SOI衬底包括通过掩埋氧化物(BOX)与体衬底隔开的薄表面晶体或硅层。
通常，IC应用包括高压(HV)晶体管，例如扩展漏极金属氧化物半导体(EDMOS)晶体管。然而，SOI衬底的薄表面衬底不适合容纳诸如EDMOS的HV晶体管。这导致难以在具有其他器件的SOI衬底上集成HV晶体管。例如，用于在SOI衬底上集成HV晶体管的常规技术需要复杂的处理以使这些晶体管与其他器件兼容。但是，这些复杂的处理导致成本增加。
发明内容
在本公开的一方面，一种结构包括：衬底，其具有绝缘体上半导体(SOI)区域和体区域；以及第一器件，其形成在所述体区域上，所述第一器件具有第一栅极电介质层和围绕所述第一电介质层的第二栅极电介质层，所述第一栅极电介质层和所述第二栅极电介质层的厚度等于或大于所述SOI区域的绝缘体层的厚度。
在本公开的一方面，一种结构包括：衬底，其具有绝缘体上半导体(SOI)区域和体区域；第一器件，其形成在所述体区域上，所述第一器件具有第一栅极电介质层和围绕所述第一电介质层的第二栅极电介质层；以及第二器件，其形成在所述体区域上，所述第二器件具有第二栅极电介质层，所述第二栅极电介质层具有与用于所述第一器件的所述第二栅极电介质层相同的厚度。所述第一器件和所述第二器件具有不同的绝对高度。
在本公开的一方面，一种结构包括：衬底，其具有绝缘体上半导体(SOI)区域和体区域；第一器件，其形成在所述体区域上，所述第一器件具有第一栅极电介质层和围绕所述第一电介质层的第二栅极电介质层；第二器件，其形成在所述体区域上，所述第二器件具有第二栅极电介质材料；以及至少第三器件，其形成在所述SOI区域上，所述至少第三器件没有所述第一栅极电介质材料和所述第二栅极电介质材料。所述第一器件、所述第二器件和所述至少第三器件每一者具有侧表面部分地硅化的源区和漏区。
附图说明
在下面的详细描述中，借助本公开的示例性实施例的非限制性示例，参考所提到的多个附图来描述本公开。
图1示出了根据本公开的方面的除其他特征之外的衬底以及相应的制造工艺。
图2示出了根据本公开的方面的除其他特征之外的来自同一衬底的SOI技术和体技术以及相应的制造工艺。
图3示出了根据本公开的方面的除其他特征之外的位于衬底上的第一栅极电介质材料以及相应的制造工艺。
图4示出了根据本公开的方面的除其他特征之外的位于图案化的第一栅极电介质材料和体技术上的第二栅极电介质材料以及相应的制造工艺。
图5示出了根据本公开的方面的除其他特征之外的图案化的第二电介质材料以及相应的制造工艺。
图6示出了根据本公开的方面的除其他特征之外的位于SOI技术和体技术上的用于形成栅极的栅极材料以及相应的制造工艺。
图7示出了根据本公开的方面的除其他特征之外的位于SOI技术和体技术上的图案化的栅极材料以及相应的制造工艺。
图8示出了根据本公开的方面的除其他特征之外的位于SOI技术和体技术上的具有被部分地硅化的升高的源区和漏区的不同器件以及相应的制造工艺。
具体实施方式
本公开涉及半导体结构，更具体地，涉及共集成的高压(HV)和中压(MV)器件及其制造方法。更具体地，本公开涉及HV和MV场效应晶体管(FET)与全耗尽绝缘体上半导体(FDSOI)技术及相关器件的共集成。有利地，本公开提供了显示驱动器集成电路(DDIC)所需的器件的完整集成方案，同时还保持了低功率FDSOI平台器件性能。此外，将HV和MV FET集成到FDSOI技术节点中以允许将来自较旧技术的应用和/或电路迁移到更多的当前技术节点中。
在实施例中，HV FET和MV FET可以与全耗尽MOSFET器件集成在同一管芯(die)(体技术)上。更具体地，例如，HV和MV FET可以被集成在体技术和SOI技术两者上。在该集成方案的示例中，HV FET包括第一栅极电介质层和第二栅极电介质层。第二栅极电介质层也将被用于MV FET。第二栅极电介质层围绕第一栅极电介质层的顶表面和侧表面，其中第一栅极电介质层和第二栅极电介质层的总厚度等于或大于SOI技术的绝缘体层(例如，掩埋氧化物)的厚度。例如，电介质层的厚度例如可以是绝缘体层的三倍。
在另外的实施例中，HV FET的栅极电介质层的厚度大于MV FET的栅极电介质层的厚度。在另一示例中，MV和HV FET(例如，MOSFET)的沟道表面与SOI技术的绝缘体层(例如，BOX)的底部对齐。另外，MV FET的栅极电介质层的厚度可以与SOI技术的绝缘体层(例如，掩埋氧化物)的厚度大致相同。
本公开的器件可以使用多种不同的工具以多种方式来制造。一般而言，方法和工具被用于形成具有微米和纳米尺寸的结构。已从集成电路(IC)技术中采用了用于制造本公开的器件的方法，即，技术。例如，该结构可以建立在晶片上，并且以通过光刻工艺被图案化的材料膜来实现。特别地，该器件的制造使用三个基本构建块：(i)将薄膜材料沉积在衬底上，(ii)通过光刻成像在膜的顶部施加图案化的掩模，以及(iii)选择性地将膜蚀刻到掩模。
图1示出了根据本公开的方面的除其他特征之外的衬底以及相应的制造工艺。更具体地，图1的结构10包括衬底12，该衬底12包括SOI技术。作为示例，衬底12可以是全耗尽p掺杂衬底。在实施例中，出于说明的目的，衬底12包括四个分开的区域：(i)用于混合器件的区域100；(ii)用于SOI/cSiGe器件的区域200；(iii)用于MV FET器件的区域300；(iv)用于HV FET器件的区域400。如以下进一步描述的，衬底12的区域100、300和400将被修改为体晶圆实现。在实施例中，作为说明性和非限制性示例，MV FET器件可以是8V FET；而HV FET器件可以是20V FET。
在SOI技术中，衬底12包括被接合或附接到绝缘层12b的半导体材料12c，并且绝缘体层12b接合到体晶圆12a，例如体半导体材料。可以使用晶圆接合技术和/或其他合适的方法来将半导体材料12c接合到绝缘层12b。绝缘层12b还通过任何合适的工艺(例如注氧隔离(SIMOX)、氧化、沉积和/或其他合适的工艺)形成。半导体材料12a、12c可以包括任何合适的半导体材料，例如Si、SiGeC、SiC、GaAs、InAs、InP以及其它III/V或II/VI族化合物半导体。绝缘体层12b还包括任何合适的材料，其中包括氧化硅、蓝宝石、其他合适的绝缘材料和/或其组合。示例性绝缘体层12b是厚度约为10-30nm的掩埋氧化物层(BOX)。
仍参考图1，在区域200中，半导体材料12c的一部分经受缩合工艺以形成具有不同半导体材料的沟道区14。例如，沟道区14可以是通过SiGe缩合工艺创建的SiGe。缩合工艺可以是本领域公知的任何缩合工艺。例如，可以使用被注入到半导体材料12c中的锗的一步或两步湿式氧化来展现锗缩合。另外，如本领域技术人员应当理解的，Ge的扩散和积累将随气流和温度而变化。在实施例中，SiGe沟道区14用于pFET器件(例如，cSiGe)。
图1进一步示出了多个浅沟槽隔离结构16。在实施例中，浅沟槽隔离结构16通过本领域技术人员公知的常规光刻、蚀刻和沉积方法形成。例如，将形成在半导体材料12c上的抗蚀剂暴露于能量(光)以形成图案(开口)。使用具有选择性化学的蚀刻工艺(例如反应离子蚀刻(RIE))，穿过抗蚀剂的开口在衬底12中形成延伸到体半导体材料12a中的一个或多个沟槽。在通过常规的氧灰化工艺或其他已知的剥离剂去除抗蚀剂之后，可以通过任何常规的沉积工艺(例如化学气相沉积(CVD)工艺)来沉积绝缘体材料(例如氧化物)。可以通过常规的化学机械抛光(CMP)工艺去除半导体材料12c、14的表面上的任何残留材料。
应当进一步理解，衬底12可以经受离子注入工艺以，特别是在区域300和400中，形成阱。例如，用于MV FET器件的区域300可以经受离子注入工艺以创建N阱；而用于HV FET器件的区域400经受离子注入工艺以形成N阱和P阱两者。例如，使用p型掺杂物(例如硼(B))掺杂或注入到P阱，使用n型掺杂物(例如砷(As)、磷(P)和Sb以及其他合适的例子)掺杂或注入到N阱。
在实施例中，可通过在衬底12中引入一定浓度的具有相反导电类型的不同掺杂物来形成阱。在实施例中，可以使用各种图案化的注入掩模来限定被暴露于注入的选定区域。在注入之后并且在注入掩模用于形成不同类型的其他阱之前，剥离用于选择暴露区域以形成阱的注入掩模。注入掩模可包括光敏材料层，例如有机光致抗蚀剂，其通过旋涂工艺施加，然后被预烘烤，接着暴露于通过光掩模投射的光下，曝光之后继续被烘烤，随后通过化学显影剂进行显影。每个注入掩模具有足以阻挡被遮蔽的区域以防止接收一定剂量的注入离子的厚度和停止能力。如本领域技术人员所理解的，在注入工艺之后，可以执行退火以驱动掺杂物。
在图2中，衬底12经受蚀刻工艺以在区域100、300和400中形成体半导体实现。例如，在去除注入掩模(和/或其他掩模)之后，对衬底12执行光刻和蚀刻工艺以去除区域100、300和400中的半导体材料12c和绝缘体层12b。这些工艺将使体半导体材料12a暴露，从而创建混合器件、MV FET和HV FET的体实现。更具体地，将形成在半导体材料12c上方的抗蚀剂暴露于能量(光)以在区域100、300和400上方形成图案(开口)。将使用具有选择性化学的蚀刻工艺(例如RIE)来去除区域100、300和400中的半导体材料12c和绝缘体层12b，同时保护区域200(包括沟道区14)，从而暴露区域100、300和400中的体半导体材料12a。以此方式，可以以体实现的方式来制造区域100、300和400中的器件，而使用SOI技术来制造区域200中的器件。可通过常规的氧灰化工艺或其他已知的剥离剂来去除抗蚀剂。
在蚀刻工艺之后，可以在区域300和400中制备沟道和延伸区域注入。在沟道和延伸区域注入期间，可通过硬掩模和/或抗蚀剂材料堆叠来保护区域100和200。以此方式，区域100和200将不会经受注入工艺。在注入工艺之后，如本领域中公知的，可以去除抗蚀剂材料堆叠。也可以清洁区域300和400的任何掩模材料以暴露体半导体材料12a的表面。然而，如图3所示，在清洁过程期间，硬掩模18将保留在区域100和200中的半导体材料12c、14上。
在图3中，在区域300和400中的体半导体材料12a上方以及在区域100和200中的硬掩模18上方形成绝缘体材料20。在沉积绝缘体材料20之前，可通过例如湿法工艺(诸如本领域技术人员公知的HF化学)来清洁半导体材料12c的暴露表面。硬掩模18将在清洁过程期间保护区域100和200的表面。在实施例中，绝缘体材料20可以是用于HV FET器件(例如区域400)的栅极氧化物材料。
绝缘体材料20可以通过用于栅极氧化物的任何常规的沉积方法(例如CVD、等离子气相沉积(PVD)等)来沉积。在沉积工艺之后，绝缘体材料20可以经受本领域公知的快速热退火工艺。在实施例中，绝缘体材料20的底表面与绝缘体层12b的底表面对齐。可以沉积大约
Figure BDA0002991944590000061
厚度的绝缘体材料20；尽管本文构想了其他尺寸。在优选实施例中，所沉积的绝缘体材料20的厚度大于绝缘体层12b的厚度。
在图4中，绝缘体材料20经历图案化工艺，随后在例如区域300中沉积用于MV FET器件的绝缘体材料22。更具体地，如图4所示，通过常规的光刻和蚀刻工艺(例如干法和湿法蚀刻工艺)从区域100、200和300中去除绝缘体材料20。绝缘体材料20还被部分地从区域400中去除，留下用于HV FET器件的图案化的绝缘体材料20。在去除抗蚀剂之后，作为示例，可通过HF溶剂来清洁暴露表面，其中硬掩模18用作HF蚀刻停止层。
在清洁工艺之后，在区域400中的绝缘体材料20的暴露表面上、在区域300和400中的体半导体材料12a的暴露表面上、以及在区域100和200中的硬掩模材料18上方沉积绝缘体材料22。在实施例中，绝缘体材料22将围绕用于HV FET器件的在区域400中的绝缘体材料20的顶表面和侧表面。此外，绝缘体材料22和绝缘体材料20两者的底表面与绝缘体层12b(例如SOI技术的掩埋氧化物层)对齐。在实施例中，绝缘体材料22是区域300中的用于MVFET器件的栅极氧化物材料。
区域400中的绝缘体材料22和绝缘体材料20的组合将比绝缘体层12b(例如SOI技术的掩埋氧化物层)厚。例如，绝缘体材料22可以具有大约
Figure BDA0002991944590000071
的厚度；尽管本文构想了其他尺寸。可通过用于栅极氧化物的任何常规的沉积方法(例如CVD、PVD等)来沉积绝缘体材料22，然后执行本领域公知的快速热退火工艺。
在图5中，用于例如区域300中的MV FET器件的绝缘体材料22经历图案化工艺，然后从区域100和200中去除硬掩模。更具体地，如图5所示，绝缘体材料22被完全地从区域100和200中去除，同时通过使用常规的光刻和蚀刻工艺(例如干法和湿法蚀刻工艺)在区域300和400中被图案化。如本领域技术人员应当理解的，区域300和400中的绝缘体材料20、22的图案化是抗蚀剂材料的图案化的结果，即，防止绝缘体材料20、22从区域300和400中去除。
在区域300中，绝缘体材料22被部分地去除，留下用于MV FET器件的绝缘体材料22。另外，在区域400中，绝缘体材料22将保留在用于HV FET器件的绝缘体材料20的侧表面和顶表面上。应当理解，由于抗蚀剂图案化，区域400中的用于HV FET器件的绝缘体材料22将形成阶梯状特征或图案23，并且还将保留在体半导体材料12a的暴露表面的一部分上。
图5进一步示出了从区域100和200中去除硬掩模18。可以去除硬掩模18。另外，在实施例中，例如，暴露表面(例如，半导体材料12c、14)可以经历使用抗蚀剂剥离的预清洁工艺，以去除半导体材料12c、14的表面上的任何自然的氧化物。
在图6中，针对每个区域中的混合器件、SOI器件、MV FET器件和HV FET器件来开始栅极图案化工艺。有利地，可通过相同的处理步骤针对每个器件制备每种栅极材料。举例来说，栅极电介质材料28被沉积在用于MV FET器件和HV FET器件的绝缘体材料22上方，同时也被沉积在用于混合器件和SOI器件的半导体材料12c、14上方。在实施例中，栅极电介质材料28可以是高k电介质材料，例如HfO2、Al2O3、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3，以及包括上述元素的多层的组合。
仍参考图6，栅极导体材料30被沉积在栅极电介质材料28上。在实施例中，首先对于栅极，栅极导体材料30可以包括本领域技术人员公知的功函数金属，其顶部具有可选的Si层，该层稍后可被硅化。用于p沟道FET的功函数材料的示例包括Ti、TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co。用于n沟道FET的功函数材料的示例包括TiN、TaN、TaAlC、TiC、TiAl、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC。功函数材料可通过CVD、包括溅射的PVD、原子层沉积(ALD)或其他合适的方法形成。使用任何常规的沉积方法在栅极导体材料30上沉积覆盖材料(例如SiN)32。如本领域技术人员应当理解的，覆盖材料32将用作侧壁间隔物。
在图7中，栅极结构将经历图案化工艺以形成例如混合器件36、SOI器件38、MV FET器件40和HV FET42。例如，从器件的水平表面去除覆盖材料32、栅极导体材料30和栅极电介质材料28，从而暴露半导体材料12a、12c、14。在该栅极图案化工艺中，在栅极图案化工艺之后，另一覆盖材料33将保留在器件36、38、40、42中的每一者的侧壁上。该图案化工艺将限定器件36、38、40、42。
在限定器件36、38、40、42中的每一者之后，在暴露的半导体材料12a、12c、14上形成源区和漏区34。在实施例中，源区和漏区34是通过掺杂外延生长工艺而直接形成在相应被暴露的半导体材料12a(用于混合器件36、MV FET器件40和HV FET器件42)和半导体材料12c、14(用于SOI器件38)上的升高的源区和漏区。然后去除覆盖材料32以暴露栅极导体材料20。
如图8进一步所示，在覆盖材料32、暴露的导体材料20以及源区和漏区34上方沉积衬里43。在实施例中，衬里是硅化物阻挡材料，其防止硅化物形成在源区和漏区34的顶表面上。在部分地去除衬里43以暴露导体材料20以及源区和漏区34的侧表面之后，在暴露的导体材料20以及源区和漏区34上形成硅化物44。本领域技术人员应当理解，硅化工艺开始于在完全形成和图案化的半导体器件(例如被掺杂或被离子注入的源区和漏区以及相应的器件)上方沉积薄的过渡金属层(例如镍、钴或钛)。在沉积材料之后，对结构进行加热，以使过渡金属与半导体器件的有源区(例如，源区、漏区、栅极接触区)中暴露的硅(或本文所述的其他半导体材料)发生反应，从而形成低电阻过渡金属硅化物。在反应之后，通过化学蚀刻来去除任何剩余的过渡金属，从而在器件的有源区中留下硅化物接触44。本领域技术人员应当理解，当栅极结构由金属材料构成时，器件上将不需要硅化物接触。
除了源区和漏区34之外，衬里46还被沉积在器件36、38、40、42中的每一者上方。在实施例中，衬里46可以是由拉伸材料(例如氮化物)构成的拉伸应力衬里。通过CVD沉积在器件上方沉积层间电介质材料48，然后进行CMP工艺。尽管该图中未示出，但是使用本领域技术人员公知的常规光刻、蚀刻和沉积工艺来形成到器件36、38、40、42以及源区和漏区34的接触，使得不需要为了完全理解本公开而做进一步解释。
图8进一步示出了器件36、38、40和42中的每一者具有不同的绝对高度。这是由于建立这些不同的器件的材料和制备工艺不同所导致的。例如，器件42包括两个栅极氧化物材料层20、24；而器件40包括包括一个栅极氧化物材料层20，而器件36不包括任何栅极氧化物。另外，器件38被建立在SOI晶圆12(例如，半导体材料12a、14)上，而不使用栅极氧化物材料；而器件36、40、42被建立在体晶圆上。
可以在片上系统(SoC)技术中利用本文描述的器件。本领域技术人员应当理解，SoC是将电子系统的所有组件集成在单个芯片或衬底上的集成电路(也称为“芯片”)。由于组件被集成在单个衬底上，因此与具有等效功能的多芯片设计相比，SoC消耗的功率少得多并且占用的面积也少得多。因此，SoC正成为移动计算(例如智能手机)和边缘计算市场中的主导力量。SoC也被常用于嵌入式系统和物联网。
如上所述的方法用在集成电路芯片的制造中。所得到的集成电路芯片可以由制造商以作为裸芯片的原始晶片形式(即，作为具有多个未封装芯片的单个晶片)或者以封装形式分发。在后一种情况下，芯片被安装在单芯片封装(诸如塑料载体中，其引线固定到母板或其他更高级别的载体)或多芯片封装(诸如陶瓷载体中，其具有表面互连和/或掩埋互连中的一者或两者)中。在任何情况下，芯片然后与其他芯片、分立电路元件和/或其他信号处理设备集成，作为(a)中间产品(诸如母板)或者(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其他低端应用，到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已为了示例的目的而给出，但并非旨在是穷举性的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的被选择以旨在最好地解释实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能理解本文公开的实施例。

Claims (20)

1.一种结构，包括：
衬底，其具有绝缘体上半导体(SOI)区域和体区域；以及
第一器件，其形成在所述体区域上，所述第一器件具有第一栅极电介质层和围绕所述第一电介质层的第二栅极电介质层，所述第一栅极电介质层和所述第二栅极电介质层的厚度等于或大于所述SOI区域的绝缘体层的厚度。
2.根据权利要求1所述的结构，进一步包括形成在所述体区域上的第二器件，所述第二器件具有与所述第一器件不同的绝对高度。
3.根据权利要求2所述的结构，其中，所述第一器件是高压场效应晶体管(FET)。
4.根据权利要求3所述的结构，其中，所述SOI区域和所述体区域中的半导体材料包括相同的半导体材料。
5.根据权利要求2所述的结构，其中，位于所述第一器件侧面的所述第一栅极电介质层和所述第二栅极电介质层形成阶梯状图案。
6.根据权利要求1所述的结构，进一步包括位于所述第一器件侧面的升高的源区和漏区，所述升高的源区和漏区包括位于其侧表面上的硅化物。
7.根据权利要求1所述的结构，进一步包括位于所述第一器件侧面且位于所述第一栅极电介质层和所述第二栅极电介质层上方的两个间隔物。
8.根据权利要求1所述的结构，进一步包括位于所述体区域上的第二器件，所述第二器件包括所述第二栅极电介质层，所述第二栅极电介质层具有与在所述第一器件上的第二栅极电介质层相同的厚度。
9.根据权利要求1所述的结构，进一步包括位于所述SOI区域上的第一SOI器件和第二SOI器件，每一个SOI器件位于所述SOI区域中的不同半导体材料上，并且每一个SOI器件包括侧面被硅化的升高的源区和漏区。
10.根据权利要求9所述的结构，进一步包括形成在所述体区域上的另一器件，所述另一器件没有所述第一栅极电介质层和所述第二栅极电介质层，并且共享用于所述第一器件、所述第二器件、所述第一SOI器件和所述第二SOI器件的相同的高k电介质材料和应力衬里。
11.一种结构，包括：
衬底，其具有绝缘体上半导体(SOI)区域和体区域；
第一器件，其形成在所述体区域上，所述第一器件具有第一栅极电介质层和围绕所述第一电介质层的第二栅极电介质层；以及
第二器件，其形成在所述体区域上，所述第二器件具有所述第二栅极电介质层，所述第二栅极电介质层具有与用于所述第一器件的所述第二栅极电介质层相同的厚度，
其中，所述第一器件和所述第二器件具有不同的绝对高度。
12.根据权利要求11所述的结构，其中，所述第一栅极电介质层和所述第二栅极电介质层的厚度等于或大于所述SOI区域的绝缘体层的厚度。
13.根据权利要求12所述的结构，进一步包括形成在所述体区域上的第三器件，所述第三器件具有与所述第一器件和所述第二器件不同的绝对高度，并且所述第三器件没有所述第一栅极电介质层和所述第二栅极电介质层。
14.根据权利要求13所述的结构，其中，所述第一器件是高压场效应晶体管(FET)，所述第二器件是中压FET。
15.根据权利要求11所述的结构，进一步包括用于所述第一器件和所述第二器件的升高的源区和漏区以及位于所述升高的源区和漏区的侧表面上的硅化物。
16.根据权利要求15所述的结构，进一步包括位于所述SOI区域中的第一SOI器件和第二SOI器件，所述第一SOI器件和所述第二SOI器件没有所述第一栅极电介质层和所述第二栅极电介质层，并且所述第一SOI器件和所述第二SOI器件中的每一者被设置在所述SOI区域中的不同半导体材料上方，以及所述第一SOI器件和所述第二SOI器件具有与所述第一器件和所述第二器件不同的高度。
17.根据权利要求15所述的结构，其中，位于所述SOI区域中的所述第一SOI器件和所述第二SOI器件具有其侧表面上包括硅化物的升高的源区和漏区。
18.一种结构，包括：
衬底，其具有绝缘体上半导体(SOI)区域和体区域；
第一器件，其形成在所述体区域上，所述第一器件具有第一栅极电介质层和围绕所述第一电介质层的第二栅极电介质层；
第二器件，其形成在所述体区域上，所述第二器件具有所述第二栅极电介质材料；以及
至少第三器件，其形成在所述SOI区域上，所述至少第三器件没有所述第一栅极电介质材料和所述第二栅极电介质材料，其中，
所述第一器件、所述第二器件和所述至少第三器件每一者具有侧表面被硅化的源区和漏区。
19.根据权利要求18所述的结构，其中，所述第一栅极电介质材料和所述第二栅极电介质材料的组合厚度大于所述SOI区域的掩埋绝缘体的厚度。
20.根据权利要求19所述的结构，其中，所述第一器件是高压器件，所述第二器件是中压器件，所述至少第三器件是形成在所述SOI区域中的不同半导体材料上方的两个器件。
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