CN113540266A - 雪崩光电二极管 - Google Patents

雪崩光电二极管 Download PDF

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CN113540266A
CN113540266A CN202110261431.3A CN202110261431A CN113540266A CN 113540266 A CN113540266 A CN 113540266A CN 202110261431 A CN202110261431 A CN 202110261431A CN 113540266 A CN113540266 A CN 113540266A
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semiconductor material
trench
semiconductor
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M·D·莱维
S·P·埃杜苏米利
J·J·埃利斯-莫纳甘
V·贾因
R·哈兹布恩
P·东莫
C·E·路斯
S·M·尚克
R·克里希纳萨米
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GlobalFoundries US Inc
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Abstract

本公开涉及半导体结构,更具体地涉及雪崩光电二极管及制造方法。该结构包括:衬底材料,其具有沟槽,该沟槽具有由该衬底材料构成的侧壁和底部;第一半导体材料,其对沟槽的侧壁和底部加衬里;光敏半导体材料,其设置在第一半导体材料上;以及第三半导体材料,其设置在光敏半导体材料上。

Description

雪崩光电二极管
技术领域
本公开涉及半导体结构,更具体地涉及雪崩光电二极管及制造方法。
背景技术
雪崩光电二极管(APD)是一种高度灵敏的半导体光电二极管,其利 用光电效应将光转换为电。从功能的角度来看,雪崩光电二极管可以被视 为光电倍增管的半导体模拟。雪崩光电二极管的典型应用是长距光纤通信, 以及用于控制算法的量子感测。较新的应用包括正电子发射断层扫描和粒 子物理。
雪崩光电二极管的适用性和实用性取决于许多参数。例如,两个因素 是量子效率和总泄漏。量子效率指示入射光子如何被吸收,然后被用于产 生初级电荷载流子;而总泄漏电流是暗电流、光电流和噪声的总和。
光电二极管的灵敏度取决于通过光敏材料的光路的长度以及所产生的 载流子对到达电极/接触(contact)/阴极的能力。在常规结构中,载流子 沿二维路径(例如,垂直地或横向地)行进,这导致路径较长。由于常规 雪崩光电二极管的路径较长,因此光敏材料内的光子复合频率很高,导致 信号丢失或信号本身减弱。此外,光敏材料本身需要非常厚,生长成本较 高且耗时较长,并且可能使得与其他电路元件的集成更具挑战性。
发明内容
在本公开的一方面,一种结构包括:衬底材料,其具有沟槽,所述沟 槽具有包括所述衬底材料的侧壁和底部;第一半导体材料,其对所述沟槽 的所述侧壁和所述底部加衬里(line);光敏半导体材料,其设置在所述 第一半导体材料上;以及第三半导体材料,其设置在所述光敏半导体材料 上。
在本公开的一方面,一种结构包括:半导体材料;沟槽,其形成在所 述半导体材料中,所述沟槽具有侧壁和底部;具有第一掺杂剂类型的半导 体材料,其对所述沟槽的所述侧壁和所述底部加衬里;本征光敏半导体材 料,其与所述半导体材料接触;第二半导体材料,其具有所述第一掺杂剂 类型,位于所述沟槽中,并且与所述本征光敏半导体材料接触;以及隔离 结构,其包括包围所述沟槽的反射材料,并远离所述本征光敏半导体材料 定位。
在本公开的一方面,一种方法包括:在衬底中形成沟槽;在所述沟槽的 侧壁和底部上设置半导体材料的衬里;在所述沟槽内的所述半导体材料上 形成未掺杂的光敏材料;在所述沟槽的外侧内的所述未掺杂的光敏材料上 形成另一半导体材料;以及在与所述半导体材料的所述衬里相邻的所述衬 底中形成具有反射材料的沟槽结构。
附图说明
在下面的详细描述中,通过本公开的示例性实施例的非限制性示例, 参考所提到的多个附图来描述本公开。
图1示出了根据本公开的方面的除其他特征之外的具有沟槽的衬底以 及相应的制造工艺。
图2示出了根据本公开的方面的除其他特征之外的对沟槽的底表面和 侧壁二者加衬里的半导体材料以及相应的制造工艺。
图3示出了根据本公开的方面的沟槽中用于形成光电二极管的另外的 半导体材料以及相应的制造工艺。
图4示出了根据本公开的方面的围绕光电二极管的浅沟槽隔离结构以 及相应的制造工艺。
图5示出了根据本公开的方面的光电二极管中的载流子路径。
图6A和图6B示出了根据本公开的方面的光电二极管的不同形状。
图7示出了根据本公开的方面的除其他特征之外的到光电二极管的接 触的形成以及相应的制造工艺。
图8示出了根据本公开的另外方面的光电二极管。
图9示出了根据本公开的进一步另外方面的光电二极管。
图10A和图10B示出了根据本公开的方面的光电二极管的不同阵列。
图11是示出本公开的光电二极管和常规系统的光电二极管的响应度 的比较图,在常规系统中,光子路径仅是二维的,例如从顶部到底部(垂 直)或从一侧到另一侧(横向)。
具体实施方式
本公开涉及半导体结构,更具体地涉及雪崩光电二极管及制造方法。 更具体地说,本公开涉及形成同心形状(或其他形状)的雪崩光电二极管 的结构和方法。有利地,除了晶胞的密堆积和改善的反射之外,由于特殊 的形状因子(例如圆形),本文所述的雪崩光电二极管显示出增加的灵敏 度。此外,雪崩光电二极管可以使用已建立的/现有的工艺与其他器件集成。
在更具体的实施例中,雪崩光电二极管形成在具有由暴露的半导体材 料构成的侧壁和底部的沟槽中。与在侧壁上具有抑制侧壁上的Ge材料的 生长的氧化物相比,沿着沟槽的侧壁和底部设置诸如硅之类的半导体材料 以增强光敏材料(例如锗(Ge)层)的生长。即,在本文提供的结构中, 从沟槽的底部和侧壁二者都生长Ge层,而不是仅从沟槽的底部生长Ge 层。
在实施例中,通过实现本文的结构,可以使用分层的外延生长(相对 于固体Ge质量)来为生成的载流子创建较短的三维(3D)路径(相对于 严格线性的路径),从而降低了检测前可能发生载流子复合的风险。在进 一步的实施例中,在沟槽内,从底部和外侧分层生长多膜堆叠(polyfilm stack),其中P+插塞位于结构中央以针对雪崩二极管的操作提供偏置。
本公开的雪崩光电二极管可以使用多种不同的工具,以多种方式来制 造。然而,一般地,方法和工具被用来形成具有微米和纳米级尺寸的结构。 已经根据集成电路(IC)技术采用了用于制造本公开的雪崩光电二极管的 方法(即,技术)。例如,这些结构建立在晶片上,并在借助晶片顶部上 的光刻工艺而图案化的材料膜中实现。具体地,雪崩光电二极管的制造使 用三个基本构造块:(i)在衬底上沉积材料薄膜;(ii)通过光刻成像在膜顶 部上施加图案化掩模;以及(iii)对掩模有选择性地蚀刻膜。
图1示出了根据本公开的方面的除其他特征之外的具有沟槽的衬底以 及相应的制造工艺。更具体地,结构10包括衬底12。衬底12例如可以表 示CMOS芯片。在实施例中,衬底12优选地是Si材料;但本文可以构想 其他半导体材料。例如,衬底12可以由包括SiC、GaAs、InAs、InP和 其他III/V或II/VI族化合物半导体的任何合适的材料组成。在优选的实施 例中,衬底12是由单一半导体材料(例如体硅)构成的N型衬底;但是, 如关于图9所描述的,例如,衬底12可以是P型衬底。
硬掩模14沉积在衬底12上。在实施例中,硬掩模14可以是氮化物或 本领域中已知的其他硬掩模材料,这样,不需要进一步解释就可以完全理 解本公开。可以通过已知的沉积方法,例如化学气相沉积(CVD)工艺, 来沉积硬掩模14。硬掩模14将在后续工艺中防止半导体材料在衬底12的 表面上外延生长。
仍然参考图1,使用本领域技术人员已知的常规光刻和蚀刻工艺在衬 底12中形成沟槽16。在一个非限制性示例中,沟槽16可具有约2.5μm的 深度(但本文可以构想其他尺寸)。在形成沟槽16时,在硬掩模14上方 形成的抗蚀剂被暴露于能量(光)下以形成图案(开口)。将使用具有选 择性化学的蚀刻工艺(例如反应离子蚀刻(RIE)),通过硬掩模14和抗蚀剂的开口在衬底12中形成一个或多个沟槽16。如关于图6A和图6B所 述的,沟槽16可以具有许多不同的配置,例如圆形、正方形等。在蚀刻工 艺之后,可以执行HF清洁以从沟槽16的表面去除污染物,从而确保沟槽 16的底表面和侧壁的暴露的半导体材料具有清洁的表面。可以通过常规的 氧灰化工艺或其他已知的剥离剂去除抗蚀剂。
由于蚀刻工艺期间化学物质的选择性,可以相对于硬掩模14的开口在 硬掩模14下方横向蚀刻衬底12。通过具有横向凹进(recess),将在沟槽 16上方形成硬掩模14的悬伸部(overhang)16a。悬伸部16a将钉扎位错, 保持材料之间的分离,并避免夹断(pinch-off)以及在后续工艺中改善外 延生长。
在图2中,半导体材料18在悬伸部16a下方的沟槽16的底表面和侧 壁二者上都生长。在实施例中,半导体材料18是通过选择性外延生长工艺 形成的衬里,该生长工艺从沟槽16的侧壁和底表面二者上的暴露半导体材 料开始。半导体材料18例如可以沿着环形圈生长。本领域普通技术人员应 该理解,硬掩模14将防止半导体材料在沟槽16外侧的衬底12的表面上生 长。半导体材料18将是P型半导体材料,优选地由与衬底12相同的材料 (例如Si)构成。在替代实施例中,半导体材料18可以是不同的材料, 例如SiGe。
如图3所示,在半导体材料18上选择性地生长另外的半导体材料20。 在实施例中,另外的半导体材料20是通过外延生长工艺形成的本征光敏半 导体材料(未掺杂)。半导体材料20优选地是Ge材料,以提供优异的响 应性,并且比由半导体材料18构成的衬里厚。在替代实施例中,半导体材 料20可以是Si、SiGe等。然后在半导体材料20上方的沟槽17的剩余部 分中生长半导体材料22。半导体材料22也将在半导体材料20的暴露的上 表面上生长。半导体材料22优选地是与半导体材料18相同的材料。例如, 半导体材料22是P+型半导体材料或多晶硅。
在实施例中,半导体材料22是位于结构中心的P+插塞,以为雪崩光 电二极管的操作提供偏置。以此方式,可以形成N-P-I-P光电二极管25。 更具体地,位于光电二极管25的中心的P+材料(例如半导体材料22)和 位于SiGe材料(例如半导体材料20)的侧面和底部上的P+材料(例如半 导体材料18)形成雪崩光电二极管(APD),该雪崩光电二极管在三个维度上偏置,从而增加了在载流子复合之前拾取信号的可能性。
在图4中,现在通过选择性蚀刻工艺去除硬掩模。在实施例中,去除 硬掩模将在半导体材料22和沟槽16(例如,光电二极管25)的边缘之间 留下空间“x”。在现在填充的沟槽16(例如,光电二极管25)周围形成浅 沟槽隔离结构或深氧化物填充/加衬里的沟槽24。在实施例中,浅沟槽隔 离结构或深氧化物填充/加衬里的沟槽24应当与本征材料(例如,Ge材料 20)间隔开,以避免对这种材料的损伤,并因此减少捕获光子的任何可能 性。而且,取决于性能参数,浅沟槽隔离结构或深氧化物填充/加衬里的沟 槽24可以具有各种深度,其中包括在沟槽16(例如,光电二极管25)的 深度以下。
浅沟槽隔离结构或深氧化物填充/加衬里的沟槽24可以通过常规的光 刻、蚀刻和沉积方法来制造。例如,形成在衬底12和光电二极管25上方 的抗蚀剂被暴露于能量(光)下以形成图案(开口)。将使用具有选择性 化学的蚀刻工艺(例如RIE)在光电二极管25一侧的衬底12中形成一个 或多个沟槽。去除抗蚀剂后,可以通过任何常规的沉积工艺(例如CVD工艺)来沉积绝缘体材料(例如氧化物)。可以通过常规化学机械抛光 (CMP)工艺去除衬底12的表面上的任何残留材料。
如在图5中代表性地示出的,光子进入光电二极管25并在本征材料中 产生载流子,这些载流子穿过本征半导体材料20(例如,Ge材料)到达 所有侧面上的半导体材料18(例如,如箭头所示)。以此方式,光电二极 管25具有三维电流。通过使三维电流流动,到衬底12的载流子路径,或 者更准确地说,穿过半导体材料(p材料)18到达衬底(N型材料)12的载流子路径要短得多(与具有从顶部到底部的路径的已知光电二极管相 比),这是因为本征半导体材料20在其侧面和底部被半导体材料18包围 着。而且,通过具有较短路径,载流子复合的可能性较小,从而导致信号 强度的损失。
另外,浅沟槽隔离结构或深氧化物填充/加衬里的沟槽24将充当反射 器或反射镜,以抑制光从沟槽的侧面进入衬底12;取而代之的是,有效地 将任何光(光子)推向衬里18并进入衬底12。换言之,形成在光电二极 管25外侧周围的浅沟槽隔离结构或深氧化物填充/加衬里的沟槽24提供反 射界面,以最大化入射光子与用于产生载流子的本征半导体材料20的相互 作用,例如,提供反射表面以增加光子在Ge材料中的驻留时间。
图6A和图6B示出了光电二极管25的不同横截面形状。例如,在图 6A中,光电二极管25的横截面轮廓是圆形的(柱状);而在图6B中, 光电二极管25的横截面轮廓为四边形(例如,正方形)。然而,应当理解, 本文还预期其他轮廓,例如但不限于条形、矩形、椭圆形、八边形等。
图7示出了除其他特征之外的到光电二极管的接触的形成以及相应的 制造工艺。在图7中,在光电二极管25的顶侧上形成半导体材料26(例 如多晶硅)。半导体材料26将用作到半导体材料26的顶部(例如,光电 二极管25的P+插塞)的接触。更具体地,半导体材料26将驱动电流引入 光电二极管25以使插塞22偏置,并将载流子从光电二极管25的中心(例如,半导体材料20)驱动到光电二极管25的外侧(例如,半导体材料的 衬里18)。这样,驱动电流将有效地放大信号。
膜28(例如氮化物或其他硬掩模材料)将覆盖或隔离半导体材料26, 以防止在光电二极管25的顶部上形成硅化物。未硅化的顶表面将在光电二 极管25的正面照明下提供最佳性能。
在光电二极管25的一侧的衬底12的外露表面上形成硅化物接触30。 本领域技术人员应当理解,硅化处理始于薄过渡金属层(例如,镍、钴或 钛)在衬底12的半导体材料上方的沉积。在沉积材料之后,加热该结构, 使过渡金属与暴露的硅(或本文所述的其他半导体材料)发生反应,从而 形成低电阻过渡金属硅化物。反应之后,通过化学蚀刻去除任何剩余的过 渡金属,从而留下硅化物接触30。
仍然参考图7,在结构上方沉积层间电介质材料(例如,氧化物)32。 在层间电介质材料(例如,氧化物)32中形成沟槽,该沟槽与硅化物接触 30的上表面对准并暴露出该上表面。沟槽通过本文已经描述的常规光刻和 蚀刻工艺形成。用金属材料(例如钨)填充沟槽以形成接触34。本领域技 术人员应当理解,接触34用于检测由光子撞击光电二极管25(例如,光 电二极管25的半导体材料20)产生的电流。
图8示出了根据本公开的另外方面的光电二极管。更具体地说,在图8的结构10a中,直接在光电二极管25的顶表面(例如,半导体材料22) 上形成硅化物接触30。该布置适合于背面照明。此后,如参考图7所述, 将接触34形成到硅化物接触30。
图9示出了根据本公开的另外方面的光电二极管。在图9的结构10b 中,光电二极管25包括与参考图1至图8描述的膜堆叠布置不同的膜堆叠 布置(例如,P-I-P-N)。具体地,衬底12a、半导体材料18a和半导体材 料22a是P型半导体材料;而半导体材料20仍为通过外延生长工艺在半 导体材料18a上形成的本征半导体材料(未掺杂)。
然而,在该实施例中,半导体材料22a不会完全填充沟槽的剩余部分。 而是,将在半导体材料22a上外延生长N型半导体材料36。或者,可以生 长半导体材料22a以完全填充沟槽的剩余部分,然后进行光刻和蚀刻工艺 以在其中央部分形成沟槽。然后,可以通过在半导体材料22a上外延生长 而用N型半导体材料36填充沟槽。直接在光电二极管25的顶表面(例如, 半导体材料36)上形成硅化物接触30,如参考图7所述,将接触34形成 到硅化物接触30。该布置也适合于背面照明。还应当理解,也可以使用该 配置(例如,通过使用多晶硅接触并且在探测器上方未发生硅化)来实践 正面照明。
图10A和图10B示出了根据本公开的方面的光电二极管的不同阵列。 更具体地,图10A示出了四边形(例如,正方形或矩形)光电二极管25 的阵列,图10B示出了圆形光电二极管25的阵列。尽管四边形(例如, 正方形或矩形)光电二极管25的阵列以彼此对齐的方式设置,但是它们可 以采取其他形式。另外,应当注意,圆形光电二极管25的阵列比四边形(例如,正方形或矩形)光电二极管25(例如18个光电二极管对16个光电二 极管)更紧密地堆积在一起。
图11是示出本公开的光电二极管和常规系统的光电二极管的响应度 的比较图,在常规系统中,光子路径仅是二维的,例如从顶部到底部(垂 直)或从一侧到另一侧(横向)。在该图中,x轴是波长(μm),y轴是 响应度(mA/W)。线“A”表示具有Ge材料的光电二极管,线“B”表示具 有Si材料的光电二极管,根据本公开的方面,它们二者都具有三维(3D)路径;而线“C”表示路径仅在横向方向上的具有Ge材料的光电二极管,线 “D”表示仅包括路径仅在垂直方向上的具有Ge材料的光电二极管。从图中 可以清楚地看出,在大约0.7μm的波长下,线“A”和“B”的光电二极管的 响应度最大。此外,在大约1.5μm的波长范围内,线“A”所示的Ge实施 方式远优于任何其他实施方式。
可以在片上系统(SoC)技术中利用雪崩光电二极管。本领域技术人 员应当理解,SoC是将电子系统的所有组件集成在单个芯片或衬底上的集 成电路(也称为“芯片”)。由于组件集成在单个衬底上,因此与具有等 效功能的多芯片设计相比,SoC消耗的功率少得多,占用的面积也小得多。 因此,SoC正成为移动计算(例如智能手机)和边缘计算市场中的主导力 量。SoC也常用于嵌入式系统和物联网。
上述方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制 造商以原始晶片形式(即,作为具有多个未封装芯片的单个晶片),作为 裸芯或以封装形式分发。在后一种情况下,芯片以单芯片封装(例如塑料 载体,其引线固定到主板或其它更高级别的载体)或多芯片封装(例如陶 瓷载体,其具有表面互连和/或掩埋互连)的形式被安装。在任何情况下, 芯片然后与其它芯片、分立电路元件和/或其它信号处理器件集成,作为(a) 中间产品(例如主板)或(b)最终产品的一部分。最终产品可以是包括 集成电路芯片的任何产品,从玩具和其它低端应用到具有显示器、键盘或 其它输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已经出于说明的目的给出,但并非旨在是 穷举的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的 情况下,许多修改和变化对于本领域普通技术人员将是显而易见的。本文 中所用术语的选择旨在最好地解释各实施例的原理、实际应用或对市场中 发现的技术的技术改进,或者使本技术领域的其他普通技术人员能够理解 本文公开的实施例。

Claims (20)

1.一种结构,包括:
衬底材料,其具有沟槽,所述沟槽具有包括所述衬底材料的侧壁和底部;
第一半导体材料,其对所述沟槽的所述侧壁和所述底部加衬里;
光敏半导体材料,其设置在所述第一半导体材料上;以及
第三半导体材料,其设置在所述光敏半导体材料上。
2.根据权利要求1所述的结构,进一步包括隔离结构,所述隔离结构延伸到所述衬底材料中并围绕所述沟槽,远离所述光敏半导体材料。
3.根据权利要求1所述的结构,其中,所述隔离结构包括反射材料,所述反射材料将光子反射到对所述沟槽的所述侧壁和所述底部加衬里的所述第一半导体材料中。
4.根据权利要求1所述的结构,其中,所述光敏半导体材料包括本征材料。
5.根据权利要求4所述的结构,其中,所述本征材料包括未掺杂的Ge材料。
6.根据权利要求4所述的结构,其中,所述衬底材料包括N型半导体材料,并且所述第一半导体材料和所述第三半导体材料包括P型半导体材料。
7.根据权利要求6所述的结构,其中,所述第三半导体材料包括P+插塞,以偏置雪崩光电二极管的操作。
8.根据权利要求7所述的结构,进一步包括位于所述P+插塞上的半导体材料和位于该半导体材料上方的掩蔽材料,以防止在所述P+插塞上形成硅化物。
9.根据权利要求8所述的结构,其中,所述P+插塞包括未硅化的材料,并且在所述沟槽的一侧上形成有接触,所述接触与所述衬底电接触以检测信号。
10.根据权利要求7所述的结构,进一步包括位于所述P+插塞上的硅化物和接触。
11.根据权利要求3所述的结构,进一步包括位于所述第三半导体材料上的第四半导体材料,所述第三半导体材料和所述第四半导体材料全部位于所述沟槽内,其中,所述衬底材料、所述第一半导体材料和所述第三半导体材料包括P型材料,所述第四半导体材料包括N型材料。
12.根据权利要求11所述的结构,进一步包括与所述N型半导体材料电连接的硅化物接触和接触。
13.一种结构,包括:
半导体材料;
沟槽,其形成在所述半导体材料中,所述沟槽具有侧壁和底部;
具有第一掺杂剂类型的半导体材料,其对所述沟槽的所述侧壁和所述底部加衬里;
本征光敏半导体材料,其与所述半导体材料接触;
第二半导体材料,其具有所述第一掺杂剂类型,位于所述沟槽中,并且与所述本征光敏半导体材料接触;以及
隔离结构,其包括包围所述沟槽的反射材料,并远离所述本征光敏半导体材料定位。
14.根据权利要求13所述的结构,其中,所述半导体材料包括N型材料,所述第一掺杂剂类型包括P型材料,并且所述结构进一步包括位于所述第二半导体材料上方的掩蔽材料,以防止在所述第二半导体材料上形成硅化物。
15.根据权利要求13所述的结构,其中,所述半导体材料包括N型材料,所述第一掺杂剂类型包括P型材料,并且进一步包括直接在所述第二半导体材料上的硅化物接触。
16.根据权利要求13所述的结构,进一步包括直接在所述沟槽内的所述第二半导体材料上的N型半导体材料,其中,所述半导体材料和所述第二半导体材料是P型材料,所述本征光敏半导体材料包括未掺杂的Ge材料。
17.根据权利要求13所述的结构,其中,所述本征光敏半导体材料包括未掺杂的Ge材料。
18.根据权利要求13所述的结构,进一步包括与所述半导体材料电连接的硅化物接触和接触。
19.根据权利要求13所述的结构,其中,所述沟槽的横截面为圆形或四边形。
20.一种方法,包括:
在衬底中形成沟槽;
在所述沟槽的侧壁和底部上设置半导体材料的衬里;
在所述沟槽内的所述半导体材料上形成未掺杂的光敏材料;
在所述沟槽的外侧内的所述未掺杂的光敏材料上形成另一半导体材料;以及
在与所述半导体材料的所述衬里相邻的所述衬底中形成具有反射材料的沟槽结构。
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