CN113488434A - 使用相同功函数材料的复合功函数层的形成 - Google Patents

使用相同功函数材料的复合功函数层的形成 Download PDF

Info

Publication number
CN113488434A
CN113488434A CN202110063658.7A CN202110063658A CN113488434A CN 113488434 A CN113488434 A CN 113488434A CN 202110063658 A CN202110063658 A CN 202110063658A CN 113488434 A CN113488434 A CN 113488434A
Authority
CN
China
Prior art keywords
aluminum
work function
function layer
layer
over
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110063658.7A
Other languages
English (en)
Inventor
李欣怡
洪正隆
徐志安
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN113488434A publication Critical patent/CN113488434A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

本公开涉及使用相同功函数材料的复合功函数层的形成。方法包括在半导体区上形成栅极电介质层，和使用第一含铝前驱物沉积第一含铝功函数层。所述第一含铝功函数层在所述栅极电介质层上方。使用第二含铝前驱物沉积第二含铝功函数层，所述第二含铝前驱物不同于所述第一含铝前驱物。所述第二含铝功函数层沉积在所述第一含铝功函数层上方。在所述第二含铝功函数层上方形成传导区。

Description

使用相同功函数材料的复合功函数层的形成
相关申请的交叉引用
本申请要求2020年7月16日提交的并且名称为“n-WFM TiAlC的新颖共前驱物方法(A Novel Co-Precursor method of n-WFM TiAlC)”的美国临时申请号63/052,612的权益，所述申请据此以引用的方式并入本文。
背景技术
金属氧化物半导体(MOS)器件通常包括金属栅极，其形成是为了解决常规多晶硅栅极中的多晶耗尽效应。当施加的电场自靠近栅极电介质的栅极区扫除载流子时发生多晶耗尽效应，从而形成耗尽层。在n掺杂多晶硅层中，耗尽层包括离子化非移动性供体位(donor site)；其中在P掺杂多晶硅层中，耗尽层包括离子化非移动性受体位(acceptorsite)。耗尽效应导致有效栅极电介质厚度的增加，使得在半导体表面上产生反型层更难。
金属栅极可包括多个层，使得可满足NMOS器件和PMOS器件的不同要求。金属栅极的形成通常涉及去除伪栅极堆叠件以形成沟槽、沉积延伸到沟槽中的多个金属层、形成金属区以填充沟槽的剩余部分，并且然后进行化学机械抛光(CMP)工艺以去除金属层的多余部分。金属层和金属区的剩余部分形成金属栅极。
金属栅极包括功函数层。常规地，n型MOS器件的功函数层由TiAlC形成，TiAlC可使用TiCl4和三乙基铝(TEA)形成。由于沉积速率限制，难以产生具有受控厚度(例如，厚度为10埃或更小)的超薄功函数层。
发明内容
本公开的一些实施方式提供了一种方法，所述方法包括：在半导体区上形成栅极电介质层；使用第一含铝前驱物沉积第一含铝功函数层，其中所述第一含铝功函数层在所述栅极电介质层上方；使用不同于所述第一含铝前驱物的第二含铝前驱物沉积第二含铝功函数层，其中所述第二含铝功函数层沉积在所述第一含铝功函数层上方；以及在所述第二含铝功函数层上方形成传导区。
本公开的另一些实施方式提供了一种器件，其包括：半导体区；在所述半导体区上方的栅极电介质；在所述栅极电介质上方的功函数层，其中所述功函数层包含TiAlC，并且其中所述功函数层包括：顶部部分，其中所述顶部部分具有第一铝原子百分比；和底部部分，其中所述底部部分具有第二铝原子百分比，并且其中所述第一铝原子百分比小于所述第二铝原子百分比；以及在所述功函数层上方的胶层。
本公开的还要另一些实施方式提供了一种器件，其包括：半导体鳍；在所述半导体鳍上的高k栅极电介质；以及栅电极，所述栅电极包括：在所述高k栅极电介质上方的包含铝的功函数层，所述功函数层包括：下半部，其中所述功函数层的峰值铝原子百分比在所述功函数层的所述下半部中；和在所述下半部上方的上半部，其中所述上半部中的原子百分比低于所述下半部中的铝原子百分比；以及在所述功函数层上方并接触所述功函数层的胶层。
附图说明
当结合附图来阅读以下详细说明时可最好地理解本公开的各方面。应注意的是，根据行业中的标准惯例，各种特征并不一定按比例绘制。事实上，为了论述清楚起见，各种特征的尺寸可任意放大或缩小。
图1-6、图7A、图7B、图8-16、图17A和图17B展示了根据一些实施方式的形成鳍式场效应晶体管(FinFET)的中间阶段的透视图和截面图。
图18展示了根据一些实施方式的具有使用不同方法形成的TiAlC层的样品。
图19展示了根据一些实施方式的TiAlC样品中的铝的信号强度。
图20展示了根据一些实施方式的n型功函数层和不同位置处的部分。
图21展示了根据一些实施方式的用于形成FinFET的工艺流程。
具体实施方式
以下公开提供许多不同实施方式或实施例以用于实现本发明的不同特征。部件和布置的具体实施例在下面描述以便简化本公开。当然，这些实施例仅仅是示例并且不意图进行限制。例如，在下面的描述中，在第二特征上方或第二特征之上的第一特征的形成可包括第一特征和第二特征直接接触形成的实施方式，并且还可包括在第一特征与第二特征之间形成附加特征，使得第一特征和第二特征可不直接接触的实施方式。另外，本公开可在各种实施例中重复参考标号和/或字母。这种重复是为了简单和清楚起见，但这种重复本身不指示所论述的各种实施方式和/或配置之间的关系。
此外，可在本文使用空间相对术语，诸如“在……下面”、“在……下方”、“下部”、“在……上面”、“上部”及等以用于方便描述，从而描述如附图中所展示出的一个元件或特征与另一元件或特征的关系。所述空间相对术语旨在涵盖除附图中所描绘的定向之外的在使用中或操作中的器件的不同定向。可以其他方式来定向装置(旋转90度或以其他定向)，并且可同样地相应解释本文所使用的空间相对描述符。
根据各种实施方式，提供了用于形成晶体管的功函数层的方法。根据本公开的一些实施方式，功函数层的形成包括两个或更多个沉积工艺，其中使用不同的前驱物来形成相同功函数材料(具有不同的组成)。原子层沉积(ALD)可用于形成功函数层。可使用可导致较大的每循环厚度和/或较高的铝百分比的前驱物形成功函数层的一个或多个下层，并且可使用可导致较小的每循环厚度和/或较低的铝百分比的前驱物形成一个或多个上层。因此，可能期望在一个或多个下层中存在更多的铝，并且对功函数层的厚度进行良好的控制。根据一些实施方式，展示了形成晶体管的中间阶段。论述了一些实施方式的一些变型。贯穿各种视图和说明性实施方式，类似的参考标号用于指示类似的元件。根据一些实施方式，将鳍式场效应晶体管(FinFET)的形成用作示例以解释本公开的概念。其他类型的晶体管和器件(诸如平面晶体管和全环绕栅极(GAA)晶体管)也可采用本公开的概念。此外，将TiAlC用作功函数层的示例，但是也可采用本公开的概念来形成包含其他材料的功函数层。
图1-6、图7A、图7B、图8-16、图17A和图17B展示了根据本公开的一些实施方式的鳍式场效应晶体管(FinFET)的形成中的中间阶段的截面图和透视图。这些图中所示的工艺也示意性地反映在如图21中所示的工艺流程400中。
在图1中，提供了衬底20。衬底20可以是半导体衬底，诸如块状半导体衬底、绝缘体上半导体(SOI)衬底等，所述半导体衬底可以是掺杂的(例如，用p型或n型掺杂物)或无掺杂的。半导体衬底20可以是晶片10(诸如硅晶片)的一部分。通常，SOI衬底是在绝缘体层上形成的半导体材料层。绝缘体层可以是例如埋氧化物(BOX)层、氧化硅层等。绝缘体层设置在通常为硅衬底或玻璃衬底的衬底上。也可使用其他衬底，诸如多层或梯度衬底。在一些实施方式中，半导体衬底20的半导体材料可包括硅；锗；化合物半导体，包括碳掺杂硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或其组合。
进一步参考图1，在衬底20中形成阱区22。相应的工艺展示为如图21中所示的工艺流程400中的工艺402。根据本公开的一些实施方式，阱区22是通过将n型杂质(其可以是磷、砷、锑等)注入到衬底20中而形成的n型阱区。根据本公开的其他实施方式，阱区22是通过将p型杂质(其可以是硼、铟等)注入到衬底20中而形成的p型阱区。所得的阱区22可延伸至衬底20的顶面。n型或p型杂质浓度可等于或小于1018cm-3，诸如在约1017cm-3与约1018cm-3之间的范围内。
参考图2，隔离区24形成为从衬底20的顶面延伸至衬底20中。在下文中，隔离区24可替代地称为浅沟槽隔离(STI)区。相应的工艺展示为如图21中所示的工艺流程400中的工艺404。衬底20的在相邻的STI区24之间的部分称为半导体带26。为了形成STI区24，在半导体衬底20上形成垫氧化物层28和硬掩模层30，且然后对其图案化。垫氧化物层28可以是由氧化硅形成的薄膜。根据本公开的一些实施方式，在热氧化工艺中形成垫氧化物层28，其中半导体衬底20的顶面层被氧化。垫氧化物层28充当半导体衬底20与硬掩模层30之间的粘合层。垫氧化物层28还可充当用于蚀刻硬掩模层30的蚀刻停止层。根据本公开的一些实施方式，硬掩模层30由氮化硅形成，例如使用低压化学气相沉积(LPCVD)。在硬掩模层30上形成光致抗蚀剂(未示出)，且然后使其图案化。然后，将图案化的光致抗蚀剂用作蚀刻掩模来图案化硬掩模层30，以形成如图2中所示的硬掩模30。
接下来，将图案化的硬掩模层30用作蚀刻掩模以蚀刻垫氧化物层28和衬底20，之后用一种或多种电介质材料填充衬底20中的所得沟槽。进行诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以去除电介质材料的多余部分，并且一种或多种电介质材料的剩余部分是STI区24。STI区24可包括内衬电介质(未示出)，所述内衬电介质可以是通过对衬底20的表面层进行热氧化而形成的热氧化物。内衬电介质还可以是使用例如原子层沉积(ALD)、高密度等离子体化学气相沉积(HDPCVD)或化学气相沉积(CVD)形成的沉积的氧化硅层、氮化硅层等。STI区24还可包括在内衬氧化物上方的电介质材料，其中可使用可流动化学气相沉积(FCVD)、旋涂等形成电介质材料。根据一些实施方式，在内衬电介质上方的电介质材料可包括氧化硅。
硬掩模30的顶面和STI区24的顶面可基本上彼此齐平。半导体带26在相邻的STI区24之间。根据本公开的一些实施方式，半导体带26是初始衬底20的一部分，因此半导体带26的材料与衬底20的材料相同。根据本公开的替代性实施方式，半导体带26是通过蚀刻衬底20的在STI区24之间的部分以形成凹槽，并且进行外延以在凹槽中再生长另一半导体材料而形成的替换带。因此，半导体带26由与衬底20的半导体材料不同的半导体材料形成。根据一些实施方式，半导体带26由硅锗、硅碳或III-V族化合物半导体材料形成。
参照图3，STI区24是凹陷的，使得半导体条26的顶部部分突出高于STI区24的剩余部分的顶面24A，以形成突出鳍36。相应的工艺展示为如图21中所示的工艺流程400中的工艺406。可使用干法蚀刻工艺来进行蚀刻，其中例如将NF3和NH3用作蚀刻气体。在蚀刻工艺中，可以产生等离子体。也可以包括氩气。根据本公开的替代性实施方式，利用湿法蚀刻工艺来进行STI区24的凹陷。蚀刻化学品可包括例如HF。
在上文例示的实施方式中，可通过任何合适的方法来图案化鳍。例如，可使用一种或多种光刻工艺(包括双重图案化或多重图案化工艺)来图案化鳍。通常，双重图案化或多重图案化工艺将光刻和自对准工艺相组合，从而允许创建例如节距小于使用单一直接光刻工艺可获得的节距的图案。例如，在一个实施方式中，在衬底上方形成牺牲层并使用光刻工艺图案化。使用自对准工艺沿着图案化的牺牲层的边形成间隔件。然后去除牺牲层，且然后可使用剩余的间隔件、或心轴来图案化鳍。
参考图4，伪栅极堆叠件38形成为在(突出)鳍36的顶面和侧壁上延伸。相应的工艺展示为如图21中所示的工艺流程400中的工艺408。伪栅极堆叠件38可包括伪栅极电介质40(图7B)和在伪栅极电介质40上方的伪栅极电极42。伪栅电极42可例如使用多晶硅或非晶硅形成，并且也可使用其他材料。伪栅极堆叠件38中的每一个还可包括在伪栅电极42上方的一个(或多个)硬掩模层44。硬掩模层44可由氮化硅、氧化硅、碳氮化硅或它们的多层形成。伪栅极堆叠件38可横跨在单个或多个突出鳍36和/或STI区24上方。伪栅极堆叠件38还具有垂直于突出鳍36的纵向方向的纵向方向。
接下来，在伪栅极堆叠件38的侧壁上形成栅极间隔件46。相应的工艺还示出为如图21中所示的工艺流程400中的工艺408。根据本公开的一些实施方式，栅极间隔件46由一种或多种电介质材料(诸如氮化硅、碳氮化硅等)形成，并且可具有单层结构或包括多个电介质层的多层结构。
然后，进行蚀刻工艺以蚀刻突出鳍36的未被伪栅极堆叠件38和栅极间隔件46覆盖的部分，从而产生图5中所示的结构。相应的工艺展示为如图21所示的工艺流程400中的工艺410。所述凹陷可以是各向异性的，且因此鳍36的直接在伪栅极堆叠件38和栅极间隔件46下面的部分受到保护，并且未被蚀刻。根据一些实施方式，凹陷的半导体条26的顶面可低于STI区24的顶面24A。因此形成凹槽50。凹槽50包括位于伪栅极堆叠件38的相对侧上的部分、和在突出鳍36的剩余部分之间的部分。
接下来，通过在凹槽50中选择性地生长(通过外延)半导体材料来形成外延区(源极/漏极区)52，从而产生图6中的结构。相应的工艺展示为如图21中所示的工艺流程400中的工艺412。根据所得的FinFET是p型FinFET还是n型FinFET，随着外延的进行，可原位掺杂p型或n型杂质。例如，当所得的FinFET是p型FinFET时，可生长硅锗硼(SiGeB)、硅硼(SiB)等。相反，当所得的FinFET是n型FinFET时，可生长硅磷(SiP)、硅碳磷(SiCP)等。在凹槽50填充有外延区52之后，外延区52的进一步外延生长导致外延区52水平扩展，并且可形成小平面(facet)。外延区52的进一步生长还可导致相邻的外延区52彼此合并。可能产生空隙(气隙)53。
在外延工艺之后，可进一步向外延区52注入p型或n型杂质以形成源极区和漏极区，这些源极区和漏极区也使用参考标号52表示。根据本公开的替代性实施方式，当在外延期间用p型或n型杂质原位掺杂外延区52时，跳过注入工艺。
图7A展示了在形成接触蚀刻停止层(CESL)58和层间电介质(ILD)60之后的结构的透视图。相应的工艺展示为如图21中所示的工艺流程400中的工艺414。CESL 58可由氧化硅、氮化硅、碳氮化硅等形成，并且可使用CVD、ALD等形成。ILD 60可包括使用例如FCVD、旋涂、CVD或另一种沉积方法形成的电介质材料。ILD 60可由含氧的电介质材料形成，所述含氧的电介质材料可以是使用作为前驱物的原硅酸四乙酯(TEOS)形成的基于硅氧化物的材料、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG)等。可进行诸如CMP工艺或机械研磨工艺的平坦化工艺，以使ILD 60、伪栅极堆叠件38和栅极间隔件46的顶面彼此平齐。
图7B展示了在n型FinFET和p型FinFET的形成中的中间结构的截面图。n型FinFET和p型FinFET的任一个截面图可对应于从图7A中的含有线7B-7B的垂直面获得的截面图。在器件区100N中形成n型FinFET，并且在器件区200P中形成p型FinFET。为了将N型FinFET中的特征与p型FinFET中的特征区分开，可使用图7A中对应特征的参考标号加数字100来表示N型FinFET中的特征，并且p型FinFET中的特征可使用图7A中的对应特征的参考标号加上数字200来表示。例如，图7B中的源极/漏极区152和252对应于图7A中的源极/漏极区52，并且图7B中的栅极间隔件146和246对应于图7A中的栅极间隔件46。n型FinFET和p型FinFET中的对应特征可以常见工艺形成。
在形成图7A和7B中所示的结构之后，将包括硬掩模层44、伪栅电极42和伪栅极电介质40的伪栅极堆叠件用金属栅极和替换栅极电介质替换，如图8至16中所示的工艺中所示。在图8至图16中，展示了STI区24的顶面124A和224A，并且半导体鳍136和236分别突出高于顶面124A和224A。
为了形成替换栅极，去除如图7A和7B中所示的硬掩模层44、伪栅电极42和伪栅极电介质40，从而形成如图8中所示的沟槽162和262。相应的工艺展示为如图21中所示的工艺流程400中的工艺416。突出鳍136和236的顶面和侧壁分别暴露于沟槽162和262。
接下来，参考图9，形成分别延伸至沟槽162和262中的栅极电介质168和268。相应的工艺展示为如图21中所示的工艺流程400中的工艺418。根据本公开的一些实施方式，栅极电介质包括分别形成在突出鳍136和236的暴露表面上的界面层(IL)164和264。IL 164和264可包括诸如氧化硅层的氧化物层，所述氧化物层通过突出鳍136和236的热氧化、化学氧化工艺或沉积工艺而形成。栅极电介质还可包括在对应的IL 164和264上方的高k电介质层166和266。高k电介质层166和266可由诸如氧化铪、氧化镧、氧化铝、氧化锆等的高k电介质材料形成。高k电介质材料的介电常数(k值)高于3.9，并且可高于约7.0或更高。高k电介质层166和266形成为共形层，并且分别在突出鳍136和236的侧壁以及栅极间隔件146和246的顶面和侧壁上延伸。根据本公开的一些实施方式，高k电介质层166和266使用ALD或CVD形成。
进一步参考图10，沉积p型功函数层169和269。相应的工艺展示为如图21中所示的工艺流程400中的工艺420。P型功函数层169和269通过沉积而形成，并且同时沉积。可使用诸如ALD或CVD的共形沉积方法来进行沉积，使得p型功函数层269的水平部分的水平厚度和垂直部分的垂直厚度彼此相等或基本上相等，例如，其中差异小于约10％。根据本公开的一些实施方式，p型功函数层169和269分别延伸至沟槽162和262中，并且包括在ILD 60上方的一些部分。
P型功函数层169和269可由诸如TiN、TaN、TiAlN、WCN、MOCN或其组合的p型功函数材料形成。根据本公开的一些实施方式，p型功函数层169和269中的每一个是由诸如TiN的均质材料或其他上述材料形成的单层。
参照图11，在p型功函数层169和269上形成蚀刻掩模70。蚀刻掩模70可包括底部减反射涂层(BARC)70A和在BARC 70A上方的光致抗蚀剂70B。相应的工艺展示为如图21中所示的工艺流程400中的工艺422。根据本公开的一些实施方式，BARC 70A由交联的光致抗蚀剂形成。接下来，施加光致抗蚀剂70B并图案化，使得去除器件区100N中的光致抗蚀剂70B的部分，并且保留器件区200P中的光致抗蚀剂70B的部分。
根据一些实施方式，使用光刻掩模(未示出)通过曝光图案化光致抗蚀剂70B，然后进行显影工艺以去除器件区100N中的光致抗蚀剂70B的部分。然后在蚀刻工艺中去除器件区100N中的BARC 70A的部分，使得暴露出p型功函数层169。
然后，进行蚀刻工艺71以蚀刻p型功函数层169。结果，使高k电介质层166显露出。相应的工艺展示为如图21中所示的工艺流程400中的工艺424。所得结构示出于图12中。光致抗蚀剂和/或BARC 70A用作蚀刻掩模，以在蚀刻工艺中保护p型功函数层269。根据本公开的一些实施方式，通过湿法蚀刻进行蚀刻工艺。例如，当p型功函数层169由TiN形成时，蚀刻化学品可包括包含氨(NH3)、过氧化氢(H2O2)和水的化学溶液。根据替代性实施方式，可使用干法蚀刻工艺。在蚀刻工艺之后，去除蚀刻掩模70，并且暴露p型功函数层269，如图13中所示。相应的工艺展示为如图21中所示的工艺流程400中的工艺426。
图14展示了在常见沉积工艺中的n型功函数层172A和272A的沉积。在整个说明书中，将n型功函数层172A和272A的沉积工艺称为功函数层的第一沉积工艺。相应的工艺展示为如图21中所示的工艺流程400中的工艺428。使用第一前驱物进行n型功函数层172A和272A的沉积。根据一些实施方式，使用ALD工艺或CVD工艺进行n型功函数层172A和272A的沉积。第一前驱物可包括含金属前驱物和含铝前驱物。含金属前驱物可包括TiCl4、TaCl5等。含铝前驱物可包括三乙基铝(TEA)和三叔丁基铝(TTBA)之一，但不是两者都包括。根据含金属前驱物，所得的n型功函数层172A和272A是TiAlC或TaAlC层。当采用ALD时，ALD循环包括脉冲含金属前驱物、清除含金属前驱物、脉冲含铝前驱物和清除含铝前驱物。n型功函数层172A和272A的沉积可包括仅单个ALD循环、或多个ALD循环。
根据一些实施方式，ALD工艺在约300℃和约500℃之间的范围内的温度下进行，前驱物的压力可在约0.5托和约40托之间的范围内。ALD工艺的沉积速率(其为每ALD循环的沉积厚度，在下文中称为每循环厚度)可在约
Figure BDA0002903344050000111
和约
Figure BDA0002903344050000112
之间的范围内。沉积速率受多种因素影响，所述因素包括但不限于晶片温度、前驱物的类型等。当晶片温度增加时，沉积速率也可能增加。例如，当将TiCl4和TEA用作前驱物时，沉积速率在水温为300℃时为每ALD循环约
Figure BDA0002903344050000113
在水温度为360℃时为每ALD循环
Figure BDA0002903344050000114
并且在水温450℃时为每ALD循环
Figure BDA0002903344050000115
当将TiCl4和TTBA用作前驱物时，沉积速率在水温为300℃时为每ALD循环约
Figure BDA0002903344050000116
在水温度为360℃时为每ALD循环大约
Figure BDA0002903344050000117
并且在水温450℃时为每ALD循环大约
Figure BDA0002903344050000118
图15展示了n型功函数层172B和272B的沉积。在整个说明书中，将n型功函数层172B和272B的沉积工艺称为功函数层的第二沉积工艺。相应的工艺展示为如图21中所示的工艺流程400中的工艺430。N型功函数层172B和272B可由与n型功函数层172A和272A相同的元素(例如Ti、Al和C)形成或包括所述相同的元素。然而，n型功函数层172B和272B中的元素的原子百分比不同于n型功函数层172A和272A中的对应元素的原子百分比。在整个说明书中，当两种材料具有不同的元素或具有相同的元素但具有不同的原子百分比时，这两种材料被称为具有不同的组成。例如，n型功函数层172B和272B中的铝的原子百分比可低于n型功函数层172A和272A中的铝的原子百分比。在整个说明书中，将n型功函数层172A和172B统称为n型功函数层172，并且将n型功函数层272A和272B统称为n型功函数层272。
使用与在第一沉积工艺中使用的第一前驱物不同的第二前驱物进行n型功函数层的第二沉积过程。根据一些实施方式，使用ALD工艺或CVD工艺进行第二沉积工艺。根据一些实施方式，第二前驱物可包括含金属前驱物和含铝前驱物。含金属前驱物可包括TiCl4、TaCl5等。此外，第二前驱物中的含金属前驱物可与第一前驱物中的含金属前驱物相同或不同，例如，当在第一前驱物中使用TiCl4时，可使用TiCl4或TaCl4作为第二前驱物。根据一些实施方式，含铝前驱物可包括TTBA和三甲基铝(TMA)之一，但不是两者都包括。根据前驱物，所得的n型功函数层172B和272B是TiAlC或TaAlC层。当采用ALD时，ALD循环还包括脉冲含金属前驱物、清除含金属前驱物、脉冲含铝前驱物和清除含铝前驱物。n型功函数层172B和272B的沉积可包括仅单个ALD循环、或多个循环。
根据一些实施方式，n型功函数层172B和272B的沉积是随着n型功函数层172A和272A的沉积原位进行的，在两者之间没有真空中断。ALD工艺可在约300℃和约500℃之间的范围内温度下进行。前驱物的压力可在约0.5托和约40托之间的范围内。ALD工艺的沉积速率可在约
Figure BDA0002903344050000121
和约
Figure BDA0002903344050000122
之间的范围内。根据一些实施方式，当将TiCl4和TMA用作前驱物时，沉积速率在水温为300℃时为每ALD循环约
Figure BDA0002903344050000123
在水温度为360℃时为每ALD循环
Figure BDA0002903344050000124
并且在水温450℃时为每ALD循环
Figure BDA0002903344050000125
根据一些实施方式，第二沉积工艺中的晶片温度与第一沉积工艺中的晶片温度相同，使得沉积可快速地从第一沉积工艺转变为第二沉积工艺。根据替代性实施方式，第二沉积工艺中的晶片温度高于或低于第一沉积工艺中的晶片温度，使得可通过调节晶片温度来更精确地调整第一沉积工艺和第二沉积工艺中的沉积速率。
根据一些实施方式，选择用于沉积n型功函数层172A和沉积n型功函数层172B的第一前驱物，使得n型功函数层172B的沉积速率(每循环厚度)小于n型功函数层172A的沉积速率(假设使用相同的晶片温度)。应理解，层272A和272B对对应的p型FinFET的功函数(以及因此阈值电压)的影响比层172A和172B的影响小，因此层272A和272B的特性可能没有在下面的论述中提及，但它们的效应与对应的层172A和172B相同。还可选择第一前驱物和第二前驱物，使得n型功函数层172A(沉积时)中的铝原子百分比高于n型功函数层172B(沉积时)中的铝原子百分比。例如，如上所述，使用TEA(和TiCl4或TaCl5)沉积的TiAlC的沉积速率大于使用TTBA(和TiCl4或TaCl5)沉积的TiAlC的沉积速率，并且进一步大于使用TMA(和TiCl4或TaCl5)沉积的TiAlC的沉积速率。此外，使用TEA(和TiCl4或TaC54)沉积的TiAlC中的铝原子百分比大于使用TTBA(和TiCl4或TaCl4)沉积的TiAlC的铝原子百分比，并且进一步大于使用TMA(和TiCl4或TaCl5)沉积的TiAlC的铝原子百分比。因此，当将TEA用于沉积n型功函数层172A时，用于沉积n型功函数层172B的前驱物可包括TTBA或TMA之一，但不是两者都包括。当将TTBA用于沉积n型功函数层172A时，用于沉积n型功函数层172B的前驱物可包括TMA。
根据一些实施方式，n型功函数层172A和272A的沉积包括m个ALD循环，其中整数m可等于1或更大，例如2、3、4或更大。n型功函数层172B和272B的沉积包括n个ALD循环，其中整数n可等于1或更大，诸如2、3、4或更大。假设n型功函数层172A和272A的沉积速率为DR72A(
Figure BDA0002903344050000131
/循环)，并且n型功函数层172B和272B的沉积速率为DR72B(
Figure BDA0002903344050000132
/循环)，则n类型功函数层172(或272)的总厚度是(m x DR72A+n x DR72B)。因为沉积速率DR72A不同于沉积速率DR72B，所以可选择值m和n以实现n型功函数层172和272的所需厚度。例如，假设将晶片温度选择为360℃，并且所需厚度为
Figure BDA0002903344050000133
则可使用TiCl4和TEA进行一个ALD循环以形成
Figure BDA0002903344050000134
的TiAlC，之后使用TiCl4和TMA进行一个ALD循环以形成形成
Figure BDA0002903344050000135
的TiAlC。如果所需厚度为
Figure BDA0002903344050000136
则可使用TiCl4和TEA进行一个ALD循环以形成
Figure BDA0002903344050000137
的TiAlC，之后使用TiCl4和TMA进行两个ALD循环以形成形成
Figure BDA0002903344050000138
的TiAlC。第一沉积工艺和第二沉积工艺的晶片温度也可彼此不同，以实现更好的厚度调整。根据本公开的一些实施方式，n型功函数层172的厚度在约
Figure BDA0002903344050000139
和约
Figure BDA00029033440500001310
之间的范围内，其中层172A的厚度可在层172的总厚度的约20％和约80％之间的范围内。
根据一些实施方式，使用TEA形成的TiAlC具有第一铝原子百分比(其可在约30％或约80％之间的范围内)，该第一铝原子百分比高于使用TTBA形成的TiAlC中的第二铝原子百分比(其可在约10％或约75％之间的范围内)。使用TTBA形成的第二铝原子百分比进一步高于使用TMA形成的TiAlC中的第三铝原子百分比(其可在约2％或约10％之间的范围内)。应理解，为了改善n型晶体管的性能，期望铝在n型功函数层172与下面的高k电介质层166之间的界面处具有高原子百分比。因此，使用TEA(或TTBA)形成n型功函数层172A是有利的，使得实现高的铝原子百分比，并且在界面处可有更多的铝。在另一方面，为了能够更精确地控制n型功函数层的总厚度，可使用具有较低沉积速率的前驱物(诸如TTBA或TMA)形成n型功函数层172B，使得可更好地控制n型功函数层的总厚度。N型功函数层172B还可有利地充当缓冲层以将含高铝层与上面层隔离。
图18和图19展示了具有不同功函数层的多个样本，其中一些形成工艺包括退火工艺。图18展示了样本302、304、306和308。样本302包括硅衬底、在硅衬底上方的栅极电介质、使用TiCl4和TEA形成的TiAlC层和在TiAlC层上方的TiN层。TiAlC层的厚度为约
Figure BDA0002903344050000141
并且TiN层的厚度为约
Figure BDA0002903344050000142
样本304类似于样本302，不同的是样本302不进行退火，而样本304在快速热退火工艺中进行退火。样本306包括硅衬底、在硅衬底上方的栅极电介质、使用TiCl4和TEA形成的第一TiAlC层、使用TiCl4和TMA形成的第二TiAlC层和在TiAlC层上方的TiN层。TiAlC层的总厚度为约
Figure BDA0002903344050000143
并且TiN层的厚度为约
Figure BDA0002903344050000144
样本308类似于样本306，不同的是样本306不进行退火，而样本308在快速热退火工艺中进行退火。
使用二次离子质谱法(SIMS)分析样本。结果示出于图19中。线312、314、316和318分别是样本302、304、306和308的结果。X轴指示用于溅射(且因此剥离)样本的溅射时间，所述时间对应于从样本顶部至底部的距离。标记了TiN层、TiAlC层、栅极电介质层和衬底的范围。观察到，线316和318的铝更集中于TiAlC层和下面的栅极电介质之间的界面处，这意味着较低的功函数和更好的器件性能。TiAlC的峰值铝原子百分比也可在TiAlC与栅极电介质之间的界面处。作为比较，线312和314的铝更集中于TiAlC层和上面的TiN层之间的界面处，这意味着铝对各个栅极的功函数有很小影响(如果有的话)。因此，样本306和308(图18)比样本302和304具有更好的结果。此外，线312接近于线314，并且线316接近于线318。这表明退火工艺不会显著改变铝的分布。
返回参考图15，根据一些实施方式，n型功函数层172包括两个层172A和172B。根据其他实施方式，n型功函数层172可包括更多层。例如，图15分别展示了在层172B和272B上方的n型功函数层172C和272C。N型功函数层172C和272C可形成为具有比下面的n型功函数层172B和272B更低的沉积速率和/或更低的铝原子百分比。例如，可使用TiCl4和TEA(没有TTBA和TMA)作为前驱物形成n型功函数层172A和272A，可使用TiCl4和TTBA(没有TEA和TMA)作为前驱物形成n型功函数层172B和272B，并且可使用TiCl4和TMA(没有TEA和TTBA)作为前驱物形成n型功函数层172C和272C。层172A、172B和172C中的每一个的形成可包括一个或多个ALD循环，以实现n型功函数层172的所需总厚度。
图16展示了替换栅极的剩余形成工艺。相应的工艺展示为如图21中所示的工艺流程400中的工艺432。在剩余形成工艺中，如果尚未完全填充沟槽162和262(图15)，则可沉积附加层以完全填充所述沟槽。附加层表示为层174和274。根据一些实施方式，附加层包括可以是形成的TiN的胶层174A/274A、和在胶层174A/274A上方的填充金属174B/274B，其中填充金属174B/274B可包括钨、钴等。然后进行诸如CMP工艺或机械研磨工艺的平坦化工艺，从而形成金属栅电极176和276。还形成分别包括对应的栅电极176和276和对应的栅极电介质168和268的替换栅极堆叠件178和278。
参照图17A，栅电极176和276凹陷，并填充有电介质材料(诸如SiN)以形成硬掩模182和282。在硬掩模182和282以及ILD 60上方形成蚀刻停止层84。蚀刻停止层84由电介质材料形成，所述电介质材料可包括氮化硅、氧氮化硅等。在蚀刻停止层84上方形成ILD 86，并且在ILD 86中形成栅极触点塞188和288。由此形成FinFET 180和280。
图17B展示了FinFET 80的透视图，其可代表图17A中的FinFET 180和280中的任一个。图17B中的栅极触点188/288代表图17A中的栅极触点塞188或288。图17B中的硬掩模82代表图17A中的硬掩模182和282。源极/漏极硅化物区90和源极/漏极触点塞92也展示于图17A中。
图20展示了图17A中区域173的放大视图。n型功函数层172的厚度表示为T1。线75A是与n型功函数层172的底部具有1/4T1的垂直距离的水平面，并且线75B是与n型功函数层172的顶部具有1/4T1的垂直距离的水平面。n型功函数层172A和172B的界面可在线75A和75B之间的某处，但界面也可高于线75B或低于线75A。层172在水平面75A处的部分的铝原子百分比表示为AAP75A，并且层172在水平面75B处的部分的铝原子百分比表示为AAP75B。根据一些实施方式，铝原子百分比AAP75B小于铝原子百分比AAP75A。此外，比率AAP75B/AAP75A可在约0.1和约0.9之间的范围内。根据一些实施方式，n型功函数层172的下半部的整体具有比n型功函数层172的上半部大的铝原子百分比，也如图19中所揭示。
应理解，尽管以TiAlC作为示例来公开使用多种前驱物形成功函数层的概念，但是功函数层不限于TiAlC。例如，可形成TaAlC。此外，功函数层不限于n型FinFET的功函数层，并且本申请的概念可应用于p型n型FinFET的功函数层。
本公开的实施方式具有一些有利特征。通过使用不同的前驱物形成功函数层的下部部分和上部部分，下部部分可具有比上部部分更高的铝原子百分比。这导致在功函数层和下面的高k介电层之间的界面处有更多的铝。因此，改善了FinFET的性能。此外，上部部分具有较低的沉积速率(每ALD循环厚度)，且因此可与下部部分组合使用以实现用于超薄功函数层的精确所需总厚度。
根据本公开的一些实施方式，方法包括：在半导体区上形成栅极电介质层；使用第一含铝前驱物沉积第一含铝功函数层，其中第一含铝功函数层在栅极电介质层上方；使用不同于第一含铝前驱物的第二含铝前驱物沉积第二含铝功函数层，其中第二含铝功函数层沉积在第一含铝功函数层上方；以及在第二含铝功函数层上方形成传导区。在一个实施方式中，第一含铝功函数层和第二含铝功函数层两者均包含TiAlC。在一个实施方式中，第一含铝功函数层被沉积为具有比第二含铝功函数层更高的铝原子百分比。在一个实施方式中，第一含铝前驱物包括TEA，并且第二含铝前驱物包括TTBA或TMA。在一个实施方式中，第二含铝前驱物包括TTBA，并且所述方法还包括在第二含铝功函数层上方沉积第三含铝功函数层，并且第三铝含功函数层使用包括TMA的第三含铝前驱物沉积。在一个实施方式中，第一含铝前驱物包括TTBA，并且第二含铝前驱物包括TMA。在一个实施方式中，第一含铝功函数层和第二含铝功函数层两者均使用原子层沉积来沉积。在一个实施方式中，第一含铝功函数层的第一每循环厚度大于第二含铝功函数层的第二每循环厚度。在一个实施方式中，第一含铝功函数层和第二含铝功函数层在相同的温度下沉积，并且在两者间没有真空中断的情况下原位沉积。
根据本公开的一些实施方式，器件包括：半导体区；在半导体区上方的栅极电介质；功函数层，所述功函数层包括接触栅极电介质的底面，其中功函数层包含TiAlC，并且其中功函数层包括顶部部分，其中顶部部分具有第一铝原子百分比；和底部部分，其中底部部分具有第二铝原子百分比，并且其中第一铝原子百分比小于第二铝原子百分比；以及在功函数层上方的胶层。在一个实施方式中，第一铝原子百分比与第二铝原子百分比的比率小于约90％。在一个实施方式中，第一铝原子百分比与第二铝原子百分比的比率在约10％和约90％之间的范围内。在一个实施方式中，功函数层包括上半部和下半部，并且上半部的整体具有比下半部低的铝原子百分比。在一个实施方式中，胶层包括氮化钛。在一个实施例中，半导体区包括半导体鳍，并且栅极电介质形成在半导体鳍的侧壁和另外的顶面上。
根据本公开的一些实施方式，器件包括：半导体鳍；在半导体鳍上的高k栅极电介质；以及栅电极，所述栅电极包括在高k栅极电介质上方的包含铝的功函数层，功函数层包括下半部，其中功函数层的峰值铝原子百分比在功函数层的下半部中；和在下半部上方的上半部，其中上半部中的原子百分比低于下半部中的铝原子百分比；以及在功函数层上方并接触功函数层的胶层。在一个实施方式中，从上半部的底部到上半部的顶部，铝原子百分比连续降低。在一个实施方式中，功函数层还包括钛。在一个实施方式中，栅电极被包括在n型鳍式场效应晶体管中。在一个实施方式中，峰值铝原子百分比在下半部与高k栅极电介质之间的界面处。
前述内容概述了多个实施方式的特征以使得本领域技术人员可更好理解本公开的各方面。本领域技术人员应了解，其可容易地使用本公开作为设计或修改其他过程和结构以便执行本文介绍的实施方式的相同目的和/或实现其相同优势的基础。本领域技术人员还应认识到，此类等效构造不偏离本公开的精神和范围，并且其可在本文中进行各种变化、取代和更改而不背离本公开的精神和范围。

Claims (10)

1.一种方法，其包括：
在半导体区上形成栅极电介质层；
使用第一含铝前驱物沉积第一含铝功函数层，其中所述第一含铝功函数层在所述栅极电介质层上方；
使用不同于所述第一含铝前驱物的第二含铝前驱物沉积第二含铝功函数层，其中所述第二含铝功函数层沉积在所述第一含铝功函数层上方；以及
在所述第二含铝功函数层上方形成传导区。
2.根据权利要求1所述的方法，其中所述第一含铝功函数层和所述第二含铝功函数层两者均包含TiAlC。
3.根据权利要求2所述的方法，其中所述第一含铝功函数层被沉积为具有比所述第二含铝功函数层更高的铝原子百分比。
4.根据权利要求1所述的方法，其中所述第一含铝前驱物包括三乙基铝(TEA)，并且所述第二含铝前驱物包括三叔丁基铝(TTBA)或三甲基铝(TMA)。
5.根据权利要求4所述的方法，其中所述第二含铝前驱物包括TTBA，并且所述方法还包括在所述第二含铝功函数层上方沉积第三含铝功函数层，并且所述第三含铝功函数层使用包括TMA的第三含铝前驱物沉积。
6.根据权利要求1所述的方法，其中所述第一含铝前驱物包括三叔丁基铝(TTBA)，并且所述第二含铝前驱物包括三甲基铝(TMA)。
7.根据权利要求1所述的方法，其中所述第一含铝功函数层和所述第二含铝功函数层两者均使用原子层沉积来沉积。
8.根据权利要求7所述的方法，其中所述第一含铝功函数层的第一每循环厚度大于所述第二含铝功函数层的第二每循环厚度。
9.根据权利要求1所述的方法，其中所述第一含铝功函数层和所述第二含铝功函数层在相同的温度下沉积，并且在两者间没有真空中断的情况下原位沉积。
10.一种器件，其包括：
半导体区；
在所述半导体区上方的栅极电介质；
在所述栅极电介质上方的功函数层，其中所述功函数层包含TiAlC，并且其中所述功函数层包括：
顶部部分，其中所述顶部部分具有第一铝原子百分比；和
底部部分，其中所述底部部分具有第二铝原子百分比，并且其中所述第一铝原子百分比小于所述第二铝原子百分比；以及
在所述功函数层上方的胶层。
CN202110063658.7A 2020-07-16 2021-01-18 使用相同功函数材料的复合功函数层的形成 Pending CN113488434A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063052612P 2020-07-16 2020-07-16
US63/052,612 2020-07-16
US16/952,503 2020-11-19
US16/952,503 US11508826B2 (en) 2020-07-16 2020-11-19 Composite work function layer formation using same work function material

Publications (1)

Publication Number Publication Date
CN113488434A true CN113488434A (zh) 2021-10-08

Family

ID=77300719

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110063658.7A Pending CN113488434A (zh) 2020-07-16 2021-01-18 使用相同功函数材料的复合功函数层的形成

Country Status (7)

Country Link
US (2) US11508826B2 (zh)
EP (1) EP3940748A1 (zh)
JP (1) JP2022019657A (zh)
KR (1) KR102490716B1 (zh)
CN (1) CN113488434A (zh)
DE (1) DE102020131319A1 (zh)
TW (1) TWI785537B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114836729A (zh) * 2022-05-17 2022-08-02 合肥安德科铭半导体科技有限公司 一种功函数可调的wcn薄膜沉积方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10458018B2 (en) * 2015-06-26 2019-10-29 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US10049940B1 (en) 2017-08-25 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for metal gates with roughened barrier layer
CN108074815B (zh) * 2016-11-17 2021-04-02 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
WO2019014448A1 (en) 2017-07-13 2019-01-17 Applied Materials, Inc. NMOS INTEGRATION WITH LOW OUTPUT OUTPUT DEPENDING THICKNESS FOR METALLIC GRID
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
US11264289B2 (en) * 2019-07-11 2022-03-01 Tokyo Electron Limited Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114836729A (zh) * 2022-05-17 2022-08-02 合肥安德科铭半导体科技有限公司 一种功函数可调的wcn薄膜沉积方法

Also Published As

Publication number Publication date
US20220359703A1 (en) 2022-11-10
TW202205395A (zh) 2022-02-01
KR102490716B1 (ko) 2023-01-19
JP2022019657A (ja) 2022-01-27
US11508826B2 (en) 2022-11-22
EP3940748A1 (en) 2022-01-19
KR20220009846A (ko) 2022-01-25
TWI785537B (zh) 2022-12-01
DE102020131319A1 (de) 2022-01-20
US20220020861A1 (en) 2022-01-20

Similar Documents

Publication Publication Date Title
US11532735B2 (en) Self-aligned epitaxy layer
CN110416081B (zh) Nfet/pfet的源极/漏极区域的选择性凹进
TWI696220B (zh) 半導體裝置的形成方法
US11145749B2 (en) Method of fabricating a semiconductor device
KR101946765B1 (ko) 반도체 디바이스 및 그 제조 방법
US20220130730A1 (en) Semiconductor Device and Method
US11101366B2 (en) Remote plasma oxide layer
CN111696859B (zh) 使用等离子体刻蚀进行超窄沟道图案化
CN112750768A (zh) 虚设栅极切割工艺及所得栅极结构
KR102571374B1 (ko) 반도체 디바이스 및 방법
CN111106000B (zh) 形成半导体器件的方法
TW202006830A (zh) 半導體裝置及其製造方法
CN112750818A (zh) 半导体器件及其形成方法
CN109585293B (zh) 切割金属工艺中的基脚去除
CN110875392A (zh) FinFET器件及其形成方法
US20220359703A1 (en) Composite Work Function Layer Formation Using Same Work Function Material
US11935937B2 (en) Nanosheet field-effect transistor device and method of forming
US20220336626A1 (en) Densified gate spacers and formation thereof
KR102447138B1 (ko) 금속 게이트 변조기의 인시추 형성
US11837649B2 (en) Method for selective removal of gate dielectric from dummy fin
US11527621B2 (en) Gate electrode deposition and structure formed thereby
US20210257263A1 (en) NMOS and PMOS Transistor Gates with Hafnium Oxide Layers and Lanthanum Oxide Layers
CN115881794A (zh) 形成半导体器件的方法
CN113257898A (zh) 偶极设计高k栅极电介质及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination