CN113471289A - 一种绝缘体上硅衬底及其制备方法、应用 - Google Patents
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Abstract
本发明涉及一种绝缘体上硅衬底及其制备方法。一种绝缘体上硅衬底的制备方法，包括：在背衬硅层上形成掩蔽层；进行光刻和蚀刻，使掩蔽层形成多条沟槽，并且沟槽贯穿掩蔽层且深入背衬硅层中，使背衬硅层的表面被分隔成多个硅线条；去除掩蔽层；沉积第一氧化硅层，第一氧化硅层填充沟槽并覆盖硅线条；减薄第一氧化硅层，使硅线条曝露；形成硅顶层；对硅顶层进行热氧化处理，使其表面形成第二氧化硅层；进行退火处理；在退火之后去除第二氧化硅层。本发明制作的衬底能减小寄生电容，提高运行速度；还能降低漏电，具有更低的功耗；还能消除闩锁效应；还能抑制衬底脉冲电流干扰；同时引入应变。
Description
技术领域
本发明涉及半导体生产工艺领域，特别涉及一种绝缘体上硅衬底及其制备方法、应用。
背景技术
非平面的Fin FE器件结构作为其核心器件拥有较强的栅控能力，对短沟道效应的抑制能力强，但Fin FET器件的工艺流程复杂；相比于三维Fin FET工艺，平面SOI器件工艺的光刻板数量要少得多，工艺相对更容易，工艺成本大大降低。但是如何制作出寄生电容小、漏电小的SOI衬底仍然是难点。
为此，提出本发明。
发明内容
本发明的主要目的在于提供一种绝缘体上硅衬底的制备方法，该方法制作的衬底能减小寄生电容，提高运行速度；还能降低漏电，具有更低的功耗；还能消除闩锁效应；还能抑制衬底脉冲电流干扰；同时引入应变。
为了实现以上目的，本发明提供了以下技术方案。
一种绝缘体上硅衬底的制备方法，包括：
在背衬硅层上形成掩蔽层；
进行光刻和蚀刻，使掩蔽层形成多条沟槽，并且所述沟槽贯穿所述掩蔽层且深入所述背衬硅层中，使所述背衬硅层的表面被分隔成多个硅线条；
去除所述掩蔽层；
沉积第一氧化硅层，所述第一氧化硅层填充所述沟槽并覆盖所述硅线条；
减薄所述第一氧化硅层，使所述硅线条曝露；
形成硅顶层；
对所述硅顶层进行热氧化处理，使其表面形成第二氧化硅层；
进行退火处理；
在所述退火之后去除所述第二氧化硅层。
与现有技术相比，本发明达到了以下技术效果：
(1)相比非平面的Fin FET器件结构，本发明的SOI(绝缘体上硅)衬底用于制作器件工艺更简单，成本也随之降低；
(2)通过先形成沟槽再填入氧化硅及退火的过程制作顶层硅和背衬硅之间的隔离层，可以达到减小寄生电容、提高运行速度、降低漏电、消除闩锁效应、抑制衬底脉冲电流干扰等效果；同时还引入了应变，还可以调整工艺条件获得不同应变以提升器件的迁移率；
(3)工艺简单、短沟道效应小及特别适用于低压低功耗电路等优势，可用于更精密要求的半导体器件。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。
图1至9为本发明提供的SOI衬底制作工艺中不同步骤形成的形貌图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
虽然现有的SOI衬底相比普通衬底已具有寄生电容小、集成密度高、速度快等优点，但是仍不足以满足日益发展的精密器件要求。
为此，本发明提供了一种新型SOI制作工艺，以进一步减小寄生电容小、提高运行速度、降低漏电、消除闩锁效应、抑制衬底脉冲电流干扰等，具体过程如下。
首先，选择硅板作为背衬层，在上面形成掩蔽层。掩蔽层可以是氧化物、氮化物等绝缘材料，例如常见的氮化硅、氧化硅、氧化铝等。生长方法包括但不限于APCVD、UHVCVD、LPCVD、RTCVD、PECVD或氧化生长等。掩蔽层可以是单层结构，也可以多层复合结构，例如单层氧化硅、单层氮化硅，或者氧化硅层和氮化硅层堆叠的复合层。氧化硅通常采用PECVD或氧化法。
接着进行图形化和蚀刻，通常借助光刻胶，蚀刻可以结合CMP、湿法腐蚀、干法刻蚀、原子层腐蚀(ALE)(干法或湿法)、气体氧化+湿法腐蚀等手段。蚀刻要在使掩蔽层形成多条沟槽，并且沟槽贯穿所述掩蔽层且深入背衬硅层中，使背衬硅层的表面被分隔成多个硅线条。由于这一步要蚀刻两种化学组成不同的材料(掩蔽层和背衬硅)，因此需要选用不同的腐蚀剂分步蚀刻。以氧化硅为例，其湿法腐蚀适用的腐蚀剂包括但不限于缓冲氢氟酸溶液(BHF)、缓冲氧化物刻蚀剂(BOE)等。硅可采用HF-HNO3腐蚀剂、碱性腐蚀液等。这一步形成的硅线条对衬底的性能有重要影响，优选采用宽度为10nm～100nm的硅线条，沟槽的深宽比控制在2:1以上，硅线条的高度限定了最终所得SOI中绝缘层的厚度。依据以上不同要求可以确定掩蔽层适宜的厚度等。
接下来去除所述掩蔽层。去除的手段不限，包括但不限于磨抛、湿法腐蚀、干法刻蚀和CMP之间的任意组合等。
然后沉积第一氧化硅层，是氧化硅填充所述沟槽并覆盖所述硅线条。优选采用TEOS(四乙氧基硅烷)作为硅源，生长方式包括但不限于PECVD，LPCVD，SACVD(次常压化学气相沉积)等，此处优选SACVD，生长温度480-600℃，更优选540℃。
之后减薄所述第一氧化硅层，使所述硅线条曝露。减薄的方法通常为CMP。
接下来形成硅顶层，该硅层为单晶硅，优选选择性外延生长。
之后对硅顶层的表面进行热氧化处理，使其表面形成第二氧化硅层，为后续的退火处理做准备。
然后退火，此时由于第一氧化硅层中还富含H2O气或自由氧等，这些形态的氧会消耗硅线条，使其转化为氧化硅，从而将背衬硅和顶层硅完全隔离，形成氧化硅隔离层。
最后去除所述第二氧化硅层，去除的手段不限，包括但不限于磨抛、湿法腐蚀、干法刻蚀和CMP之间的任意组合等。
本发明还提供的具体的实施例，以下结合图进行说明。
实施例
第一步，在背衬硅层1上形成氧化硅掩蔽层2，得到如图1所示的形貌。
第二步，进行光刻和蚀刻，使氧化硅掩蔽层2形成多条沟槽4，得到如图2所示的形貌。其中，沟槽4贯穿氧化硅掩蔽层2且深入背衬硅层1中，使背衬硅层1的表面被分隔成多个硅线条3，沟槽4的深宽比在2:1以上，并且每个所述硅线条3的宽度为10nm～100nm。
第三步，蚀刻去除氧化硅掩蔽层2，得到如图3所示的形貌。
第四步，以TEOS为硅源，采用SACVD沉积第一氧化硅层5，其填充沟槽并覆盖硅线条，得到如图4所示的形貌，沉积温度控制在480～600℃，尤其是540℃。
第五步，CMP减薄第一氧化硅层5，使硅线条3曝露，得到如图5所示的形貌。
第六步，选择性外延生长形成硅顶层6，得到如图6所示的形貌。
第七步，对硅顶层6进行热氧化处理，使其表面形成第二氧化硅层7，得到如图7所示的形貌。
第八步，进行退火处理，此时氧化硅中的氧会消耗硅线条3，从而形成隔离层8，得到如图8所示的形貌。
第九步，去除第二氧化硅层7，得到寄生电容小、运行速度快、漏电小、无闩锁效应的SOI衬底，如图9所示，包括背衬硅层1、隔离层8和硅顶层6。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。
Claims (10)
1.一种绝缘体上硅衬底的制备方法，其特征在于，包括：
在背衬硅层上形成掩蔽层；
进行光刻和蚀刻，使掩蔽层形成多条沟槽，并且所述沟槽贯穿所述掩蔽层且深入所述背衬硅层中，使所述背衬硅层的表面被分隔成多个硅线条；
去除所述掩蔽层；
沉积第一氧化硅层，所述第一氧化硅层填充所述沟槽并覆盖所述硅线条；
减薄所述第一氧化硅层，使所述硅线条曝露；
形成硅顶层；
对所述硅顶层进行热氧化处理，使其表面形成第二氧化硅层；
进行退火处理；
去除所述第二氧化硅层。
2.根据权利要求1所述的制备方法，其特征在于，所述掩蔽层为氧化硅层或氮化硅层，或者氧化硅层和氮化硅层堆叠的复合层。
3.根据权利要求1所述的制备方法，其特征在于，所述沟槽的深宽比在2:1以上。
4.根据权利要求1所述的制备方法，其特征在于，所述硅顶层的形成方法为选择性外延生长。
5.根据权利要求1所述的制备方法，其特征在于，所述减薄的方法为化学机械抛光。
6.根据权利要求1所述的制备方法，其特征在于，所述第一氧化硅层的沉积方法为SACVD。
7.根据权利要求6所述的制备方法，其特征在于，所述SACVD时的沉积温度为480～600℃。
8.根据权利要求1-7任一项所述的制备方法，其特征在于，每个所述硅线条的宽度为10nm～100nm。
9.利用权利要求1-8任一项所述的制备方法得到的绝缘体上硅衬底。
10.权利要求9所述的绝缘体上硅衬底在半导体器件中的应用。
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