CN113394285A - 一种具有ESD栅极防护的p-GaN HEMT器件 - Google Patents

一种具有ESD栅极防护的p-GaN HEMT器件 Download PDF

Info

Publication number
CN113394285A
CN113394285A CN202110716823.4A CN202110716823A CN113394285A CN 113394285 A CN113394285 A CN 113394285A CN 202110716823 A CN202110716823 A CN 202110716823A CN 113394285 A CN113394285 A CN 113394285A
Authority
CN
China
Prior art keywords
gan hemt
hemt device
gan
esd
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110716823.4A
Other languages
English (en)
Inventor
陈万军
信亚杰
段力冬
孙瑞泽
张波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN202110716823.4A priority Critical patent/CN113394285A/zh
Publication of CN113394285A publication Critical patent/CN113394285A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明属于半导体器件及集成电路技术领域，具体的说是涉及一种具有ESD栅极防护的p‑GaN HEMT器件。与常规的p‑GN HEMT器件不同的是，本发明基于增强型p‑GaN HEMT器件，限流电阻组成具有自触发功能的栅极ESD防护电路。本发明利用ESD发生时产生的瞬态随时间增大的电压，再通过第一限流电阻和第二限流电阻之间的分压，在第二增强型器件的栅极产生一个大于阈值电压的信号，实现第二增强型器件的开启来泄放ESD电荷，从而对p‑GaN HEMT器件栅极的防护。相比于传统p‑GaN HEMT器件，栅极ESD失效电压能够提升19倍以上，不牺牲其他电学特性。其次，由于该发明制备过程与增强型p‑GaN HEMTs工艺兼容，能够大幅降低与传统p‑GaN HEMT器件集成时的制备工艺难度。

Description

一种具有ESD栅极防护的p-GaN HEMT器件
技术领域
本发明属于半导体器件及集成电路技术领域，具体涉及一种具有ESD栅极防护的p-GaN HEMT器件。
背景技术
氮化镓(GaN)是第三代宽禁带半导体材料代表，受到各国研究人员的广泛关注。GaN 材料具有禁带宽度大、饱和电子漂移速度高、介电常数小及良好的化学稳定性等特点，因此， GaN基HEMT器件与Si基器件相比，具有较低的导通电阻、较小寄生电容、较高的击穿电压等优良性能，可以满足下一代系统对半导体器件更大功率、更小体积、更高频率的应用需求。
然而，传统的基于AlGaN/GaN异质结器件由于存在自发极化和压电极化效应形成天然的二维电子气导电沟道，为耗尽型器件。但是由于耗尽型器件会增大应用时驱动电路设计的复杂性和可靠性，因此需要增强型的GaN器件来满足应用需求。目前几种常用的增强型技术中， p-GaN增强型器件已经实现商业化。p-GaN HEMT器件的实现方法为在栅极区域外延一层p 型GaN层，p-GaN与AlGaN/GaN异质结形成类PiN结构，类二极管结构中内建电场能够抵消AlGaN/GaN异质结中自发极化和压电极化产生的电场作用，从而能够耗尽栅极下方的二维电子气，从而使得器件具有常关型特性。由于p-GaN HEMTs器件特有的Metal/p-GaN/AlGaN 栅极结构限制了栅极工作电压范围，当前常见的p-GaN HEMTs器件栅极的工作电压范围约为 -4～6V。同时，在实际应用中，为了降低器件工作时的导通电阻，栅极工作电压一般在5V左右，这就导致p-GaN HEMT器件在工作时的安全电压范围很低。另外，由于p-GaN HEMT 器件栅极Metal/p-GaN结部分为肖特基接触，当栅极施加正压时Metal/p-GaN结部分反偏，所以在p-GaN HEMTs栅极施加高压时，栅极极易击穿导致器件失效。
根据前期研究结果表明，p-GaN HEMTs栅极与源极之间在基于HBM模型的ESD可靠性测试中，失效电压仅200～400V，远低于2000V的工业标准。因此急需一种具备栅极ESD防护的器件，来提升p-GaN HEMT器件栅极源极间ESD可靠性，使p-GaN HEMT器件满足ESD 可靠性标准。
发明内容
本发明在于克服传统p-GaN HEMT器件栅极源极间ESD可靠性无法满足工业标准的问题，提供一种具备栅极ESD防护能力的p-GaN HEMT器件。实现不影响器件的正常工作，ESD耐压电压等级更高，更节约芯片面积，且产生的额外功耗更小的器件。
本发明的技术方案为：
一种具有ESD栅极防护的p-GaN HEMT器件，其特征在于，包括作为主功率器件的第一增强型p-GaN HEMT器件、作为触发器件的第二增强型p-GaN HEMT器件、第一限流电阻和第二限流电阻；所述第一限流电阻的一端与第一增强型p-GaN HEMT器件的源极连接，第一限流电阻的另一端与第二增强型p-GaN HEMT器件的栅极连接；所述第二限流电阻的一端与第一增强型p-GaN HEMT器件的栅极连接，第二限流电阻的另一端与第二增强型p-GaN HEMT器件的栅极连接；所述第二增强型p-GaN HEMT器件的漏极与第一增强型p-GaN HEMT器件的栅极连接，第二增强型p-GaN HEMT器件的源极与第一增强型p-GaN HEMT 器件的源极连接。
进一步的，所述第一增强型p-GaN HEMT器件和第二增强型p-GaN HEMT器件的栅极金属与p-GaN层接触为欧姆接触或者肖特基接触。
进一步的，所述第一和第二限流电阻为二维电子气沟道形成的电阻或通过外延形成的薄膜电阻。
本发明的有益效果为：本发明利用ESD发生时产生的瞬态随时间增大的电压，再通过第一限流电阻和第二限流电阻之间的分压，在第二增强型器件的栅极产生一个大于阈值电压的信号，使第二增强型器件的导电沟道开启来泄放ESD电荷，从而实现对p-GaN HEMT器件栅极的防护。相比于传统p-GaN HEMT器件，栅极ESD失效电压能够提升19倍以上，不牺牲其他电学特性。其次，由于该发明制备过程与增强型p-GaN HEMTs工艺兼容，能够大幅降低与传统p-GaN HEMT器件集成时的制备工艺难度。
附图说明
图1为提出的具有ESD栅极防护的p-GaN HEMT器件结构原理图；(a)为具有ESD栅极防护的p-GaN HEMT器件的三维结构图，(b)为三维结构图的俯视图。
图2(a)为传统p-GaN HEMT器件的等效模型，(b)为本发明提出的具有ESD防护的p-GaN HEMT器件的等效模型。
图3为本发明的具有ESD栅极防护功能的p-GaN HEMT器件在正偏ESD发生时的工作原理。
图4为本发明的栅源间产生的功耗与相应时间与第一限流电阻R1的关系。
图5为本发明的TLP I-V特性曲线与传统p-GaN HEMT器件的对比。
图6为本发明的静态I-V特性与传统p-GaN HEMT器件的对比；(a)击穿特性；(b)输出特性；(c)转移特性；(d)IGS-VGS特性。
具体实施方式
下面结合附图对本发明进行详细描述。
如图1所示，本发明由第一增强型p-GaN HEMT器件(Main p-GaN HEMT)，第二增强型p-GaN HEMT器件(Self-triggered p-GaN HEMT)，第一限流电阻(R1)和第一限流电阻(R2)组成。本发明的具有ESD栅极防护的p-GaN HEMT器件的等效模型如图2(b)所示。其中 p-GaN增强型器件栅极金属与p-GaN层接触为肖特基接触型(也可为欧姆接触)，限流电阻为利用二维电子气沟道形成的电阻。
该发明所述的具有ESD栅极防护功能的p-GaN HEMT器件的工作原理为：
当正偏的ESD事件发生时，栅极积累的静电电荷会产生一个瞬态的电压，形成一个正向的电流流过R2，从而在G1端口产生一个电压。当在G1端口的电压超过第二增强型器件的阈值电压Vth_ST_F时，第二增强型器件导电沟道就会开启。因此，正向的静电泄放电流就可以流经第二增强型器件的沟道，不再流过第一增强型器件的栅极与源极，从而起到保护p-GaN HEMT器件的栅极，如图3所示。我们定义，当G1端口达到第二增强型器件的阈值电压时，第一增强型器件的栅极对应的电压为Vtrigger。特别地，正向的触发电压为Vtrigger_F，反向的触发电压为Vtrigger_R。具体地，当本发明的第一增强型器件的栅极达到触发电压Vtrigger_F时，流过第一限流电阻R1的电流为Vth_ST_F/R1。由于第二增强型器件的栅极源极间的泄漏电流IG1-S1非常小，可以忽略不计，那么流过第二限流电阻的电流就等于流经第一限流电阻的电流IR1。因此，正向的触发电压Vtrigger_F就正比于第二增强型器件的阈值电压Vth_ST_F，比例就是 (R1+R2)/R1，如公式1所示。类似地，反向的触发电压Vtrigger_R也正比于阈值电压Vth_ST_R，如公式2所示。
Figure BDA0003135300060000031
Figure BDA0003135300060000041
当本发明的器件工作于导通状态时，会在栅极与源极之间产生额外的功耗。如图3所示，我们可以看出有两个泄露电流的路径(ID1-S1和IR2)会产生功耗。通常，第二增强型器件的漏源泄露电流ID1-S1非常小，可以忽略。那么产生的额外功耗就主要由IR2产生。而产生的功耗可以由公式3估算，其中d是占空比，Vop是栅极工作电压。当把占空比设定为0.5时，R2/R1的比例设定为3，估算得到的功耗如图4所示。从图4可以看出，当电阻R1从60欧增加至1k欧时，功耗急剧降低，然后趋于平缓。但是，当功耗增加到一定程度时，会产生很大的延时，延时时间估算方式如图4所示。当设定第二增强型器件的输入电容为1pF时，得到的延迟时间如图4所示。所以基于上述分析，R1选值的范围大概为1k欧～8k欧。
Figure BDA0003135300060000042
τ＝R2×Ciss_ST_p-GaN,with R2/R1＝3 (4)
根据选定的优化值(R2/R1＝3，R1＝4k欧)，对本发明的具有自触发的ESD耐压进行了评估。如图5所示，仿真结果表明，本发明的具有ESD栅极防护的p-GaN HEMT器件具有更高的TLP电流处理能力，更高的TLP电流承受能力表示更高的ESD耐压。典型地，对于本发明的正向的和反向的TLP电流处理能力分别为4.32安和4.4安。相比于传统的p-GaN HEMT器件，TLP电流电流能够提升19倍以上。
另外，将本发明的器件的I-V特性与传统的器件进行了对比，如图6所示。可以看出，对于击穿特性、输出特性和转移特性，本发明的器件与传统的p-GaN HEMT器件完全一致。而对于IGS-VGS特性，由于本发明具有自触发的泄放通路，在栅源电压达到触发电压后，会使第二增强型器件沟道开启，从而导通电流。

Claims (3)

1.一种具有ESD栅极防护的p-GaN HEMT器件，其特征在于，包括作为主功率器件的第一增强型p-GaN HEMT器件、作为触发器件的第二增强型p-GaN HEMT器件、第一限流电阻和第二限流电阻；所述第一限流电阻的一端与第一增强型p-GaN HEMT器件的源极连接，第一限流电阻的另一端与第二增强型p-GaN HEMT器件的栅极连接；所述第二限流电阻的一端与第一增强型p-GaN HEMT器件的栅极连接，第二限流电阻的另一端与第二增强型p-GaN HEMT器件的栅极连接；所述第二增强型p-GaN HEMT器件的漏极与第一增强型p-GaN HEMT器件的栅极连接，第二增强型p-GaN HEMT器件的源极与第一增强型p-GaN HEMT器件的源极连接。
2.根据权利要求1所述的具有ESD栅极防护的p-GaN HEMT器件，其特征在于，所述第一增强型p-GaN HEMT器件和第二增强型p-GaN HEMT器件的栅极金属与p-GaN层接触为欧姆接触或者肖特基接触。
3.根据权利要求1所述的具有ESD栅极防护的p-GaN HEMT器件，其特征在于，所述第一二限流电阻和第二限流电阻为二维电子气沟道形成的电阻或通过外延形成的薄膜电阻。
CN202110716823.4A 2021-06-28 2021-06-28 一种具有ESD栅极防护的p-GaN HEMT器件 Pending CN113394285A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110716823.4A CN113394285A (zh) 2021-06-28 2021-06-28 一种具有ESD栅极防护的p-GaN HEMT器件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110716823.4A CN113394285A (zh) 2021-06-28 2021-06-28 一种具有ESD栅极防护的p-GaN HEMT器件

Publications (1)

Publication Number Publication Date
CN113394285A true CN113394285A (zh) 2021-09-14

Family

ID=77624068

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110716823.4A Pending CN113394285A (zh) 2021-06-28 2021-06-28 一种具有ESD栅极防护的p-GaN HEMT器件

Country Status (1)

Country Link
CN (1) CN113394285A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113809067A (zh) * 2021-11-16 2021-12-17 芯众享(成都)微电子有限公司 一种带有片内栅极回跳保护的常关型hmet器件
CN114256822A (zh) * 2021-12-21 2022-03-29 电子科技大学 一种新型的GaN基ESD保护电路
CN116073768A (zh) * 2023-03-20 2023-05-05 成都明夷电子科技有限公司 射频低噪声放大器芯片的静电保护电路及射频放大电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101022128A (zh) * 2006-02-16 2007-08-22 松下电器产业株式会社 氮化物半导体装置及其制作方法
US20140015591A1 (en) * 2012-07-10 2014-01-16 The Hong Kong University Of Science And Technology Gate protected semiconductor devices
US20140284662A1 (en) * 2013-03-21 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor device
CN105304707A (zh) * 2015-10-28 2016-02-03 电子科技大学 一种增强型hemt器件
US20160307886A1 (en) * 2015-04-16 2016-10-20 Gan Systems Inc. GATE INPUT PROTECTON FOR DEVICES AND SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101022128A (zh) * 2006-02-16 2007-08-22 松下电器产业株式会社 氮化物半导体装置及其制作方法
US20140015591A1 (en) * 2012-07-10 2014-01-16 The Hong Kong University Of Science And Technology Gate protected semiconductor devices
US20140284662A1 (en) * 2013-03-21 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor device
US20160307886A1 (en) * 2015-04-16 2016-10-20 Gan Systems Inc. GATE INPUT PROTECTON FOR DEVICES AND SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS
CN105304707A (zh) * 2015-10-28 2016-02-03 电子科技大学 一种增强型hemt器件

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113809067A (zh) * 2021-11-16 2021-12-17 芯众享(成都)微电子有限公司 一种带有片内栅极回跳保护的常关型hmet器件
CN113809067B (zh) * 2021-11-16 2022-02-18 芯众享(成都)微电子有限公司 一种带有片内栅极回跳保护的常关型hemt器件
CN114256822A (zh) * 2021-12-21 2022-03-29 电子科技大学 一种新型的GaN基ESD保护电路
CN114256822B (zh) * 2021-12-21 2024-05-07 电子科技大学 一种GaN基ESD保护电路
CN116073768A (zh) * 2023-03-20 2023-05-05 成都明夷电子科技有限公司 射频低噪声放大器芯片的静电保护电路及射频放大电路

Similar Documents

Publication Publication Date Title
Wei et al. Charge Storage Mechanism of Drain Induced Dynamic Threshold Voltage Shift in ${p} $-GaN Gate HEMTs
JP6201422B2 (ja) 半導体装置
US9865722B2 (en) Avalanche energy handling capable III-nitride transistors
CN113394285A (zh) 一种具有ESD栅极防护的p-GaN HEMT器件
US8766275B2 (en) Composite semiconductor device
US9160326B2 (en) Gate protected semiconductor devices
CN109193601B (zh) 一种esd保护电路
CN114093864B (zh) 静电防护电路及电子装置
US9305917B1 (en) High electron mobility transistor with RC network integrated into gate structure
CN113161345A (zh) 一种新型的GaN基ESD防护电路
CN108807376B (zh) 一种低压mos辅助触发scr的双向瞬态电压抑制器
JP5424128B2 (ja) 保護素子およびそれを備えた半導体装置
CN107331704B (zh) 一种栅压控制晶闸管器件
CN113345964B (zh) 一种横向双扩散晶体管
US11476325B2 (en) Semiconductor device
CN114301044B (zh) 一种基于ⅲ族氮化物的esd保护电路
CN114256822B (zh) 一种GaN基ESD保护电路
CN113809067B (zh) 一种带有片内栅极回跳保护的常关型hemt器件
Chiu et al. A high protection voltage dual-gate GaN HEMT clamp for electric vehicle application
CN215378446U (zh) 一种p-GaN器件的片内过压保护电路
CN112466241B (zh) 基于双输出通道驱动ic的栅极驱动装置
CN113345881A (zh) 控制电路
CN113675269A (zh) 一种抑制短沟道效应的p-GaN HEMT器件
CN103337520A (zh) 双跨导半导体开关器件及其制造方法
CN113381735A (zh) D触发器电路

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20210914

RJ01 Rejection of invention patent application after publication