CN113380789A - 减小电路组件应力的装置和方法 - Google Patents

减小电路组件应力的装置和方法 Download PDF

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CN113380789A
CN113380789A CN202110211930.1A CN202110211930A CN113380789A CN 113380789 A CN113380789 A CN 113380789A CN 202110211930 A CN202110211930 A CN 202110211930A CN 113380789 A CN113380789 A CN 113380789A
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integrated circuit
circuit
trenches
platform
stress sensitive
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P·菲茨杰拉德
G·R·小斯波尔丁
J·E·D·赫维茨
M·J·弗林
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Analog Devices International ULC
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Abstract

本公开涉及减小电路组件应力的装置和方法。本公开涉及包括各种结构元件的集成电路，这些结构元件被设计成减少应变对电路的电子部件的影响。特别是，将沟槽和空腔的组合用于将集成电路与周围的基板机械隔离。沟槽可以形成为使得它们围绕集成电路，并且空腔可以形成在集成电路之下。这样，可以在形成平台的基板的一部分上形成集成电路。为了使平台不移动，可以将其系到周围的基板。通过包括这样的机械元件，减小集成电路的电特性的变化。

Description

减小电路组件应力的装置和方法
技术领域
本申请涉及用于减小电路部件上的应力的装置和方法。
背景技术
集成电路(“IC”)通常会由于构成IC封装的不同材料的物理性能差异而遭受机械应变。这些材料包括半导体材料、氧化物材料、金属和各种用于封装IC的塑料。这些材料具有不同的膨胀温度系数(“TCE”)、吸湿性和粘弹性、会随温度、湿度和时间的变化而对IC施加机械应变。
机械应变会导致IC内电路组件的电气特性发生变化。在制造过程中，可以进行校准，以尽量减少机械应变对电气特性的影响。但是，制造后，IC仍会因温度、湿度和时间而变化。此外，IC封装上的外力会影响IC的应变。例如，在IC测试期间，机械处理器可以将外力施加到IC上。
申请人的在先公开US2013/0292793提出在IC周围使用沟槽，以将IC与周围基板中的机械应变隔离开。然而，在本领域中需要改进的技术以最小化由于应变导致的IC封装内的电敏电路组件的电特性变化。
发明内容
本公开涉及包括各种结构元件的集成电路，这些结构元件被设计成减少应变对电路的电子部件的影响。特别是，将沟槽和空腔的组合用于将集成电路与周围的基板机械隔离。沟槽可以形成为使得它们围绕集成电路，并且空腔可以形成在集成电路之下。这样，可以在形成平台的基板的一部分上形成集成电路。为了使平台不移动，可以将其系绳固定到周围的基板上。通过包含这样的机械元件，可以最大程度地减少应力和应变向敏感电路的传递，并减少集成电路电气特性的变化。
在第一方面，本公开提供集成电路，包括：集成电路管芯，具有一个或多个应力敏感电路组件，所述应力敏感电路组件在所述集成电路管芯的第一表面上或附近形成；在所述一个或多个应力敏感电路组件周围形成一个或多个沟槽；和在所述一个或多个应力敏感电路组件下面形成一个或多个空腔。
在第二方面，本公开提供一种制造集成电路的方法，该方法包括：提供集成电路管芯；在所述集成电路管芯的第一表面上或附近形成一个或多个应力敏感电路组件；在所述一个或多个组件附近形成一个或多个沟槽；在所述一个或多个应力敏感电路组件下面形成空腔。
在第三方面，本公开提供一种制造集成电路的方法，该方法包括：提供在其第一表面中形成有空腔的晶片；将集成电路管芯结合到第一表面；在所述集成电路管芯的第一表面中形成一个或多个沟槽；其中在所述一个或多个沟槽形成的区域内，在所述集成电路管芯的第一表面上或附近形成一个或多个应力敏感组件。
本公开的其他实施例和特征在所附权利要求中定义。
附图说明
现在将结合附图仅以示例的方式描述本公开，其中：
图1是根据本公开的实施例的集成电路的截面图；
图2A至2E是图1的集成电路的剖视图，示出了制造过程中的各个步骤。
图3是示出图2A至2E的制造过程的流程图。
图4是根据本公开实施例的集成电路的平面图。
图5是根据本公开实施例的集成电路的平面图。
图6是示出图5的集成电路所经受的应力的模拟；
图7是根据本公开实施例的集成电路的平面图。
图8A至图8F是根据本公开的另外的实施例的集成电路的平面图。
图9是根据本公开的实施例的集成电路的截面图。
图10是根据本公开实施例的集成电路的平面图。
图11A至11C是另一实施例的集成电路的截面图，示出了制造过程中的各个步骤。
图12是另一实施例中的集成电路的平面图，示出了各种导电迹线的布线。
图13是根据本公开的实施例的集成电路的横截面。
具体实施方式
本公开涉及用于减少集成电路所经受的机械应力的各种机构。集成电路通常使用硅晶片形成。通过用杂质掺杂半导体，在诸如硅的半导体层中形成有源电路组件，例如晶体管。可以使用在介电层中形成的金属化层(例如在硅上方形成的氧化硅)来形成与有源组件的连接。一些集成电路对外部影响敏感，例如温度和机械应力。当温度或机械应力变化时，此类电路的电气特性也会发生变化，对于给定的输入，这可能导致电路输出的变化。电子电路中普遍希望减少这种外部影响的影响。例如，对于某些电路(例如电压或电流参考)而言，输出与所需输出的差异不大是特别重要的。如果需要参考电压来提供一伏输出，则无论温度或机械应力如何，都希望输出始终为一伏。
有多种不同形式的机械应力可能会影响敏感电路的输出。例如，当从生产集成电路的硅晶片上切出单个集成电路时，切割过程会导致电路特性的变化。由于在切割过程中会发生变化，因此即使不是不可能，也很难校准一次电路。另外，管芯封装过程，印刷电路板安装过程，水分进入IC，温度变化或外部引起的机械应变都会导致管芯应力发生变化，从而影响集成电路的输出。
申请人先前已经认识到其中一些问题，如美国专利公开号No.US 2013/0292793A1。在本公开中，提出了提供穿过介电层和硅层的沟槽以将敏感集成电路与周围半导体中的应力隔离。尽管沟槽有助于减轻机械应力的影响，但申请人仍在进行进一步的改进以创建更好的机械隔离。特别地，本公开涉及在灵敏集成电路下方的空间中提供一个或多个空腔。可以通过以类似于在US 2013/0292793A1中描述的方式在敏感集成电路周围形成沟槽，然后使用该沟槽对集成电路下方的硅进行各向同性或各向异性蚀刻来产生腔。如将意识到的，代替围绕集成电路的单个沟槽，可以使用部分地围绕集成电路的一个或多个沟槽。通过选择性地在集成电路下各向同性地进行蚀刻，在其上形成集成电路的半导体部分有效地漂浮在剩余的硅上方，并通过一个或多个系绳耦合到硅。通过完全切除集成电路，在集成电路和硅之间仅保留最少的系绳材料，可以显着改善与机械应力的隔离。现在将描述机械隔离的电路的各种示例及其制造方法。
可以在集成电路周围形成沟槽，从而在一侧或多侧上屏蔽沟槽以防止基板中的应变。例如，沟槽可以形成为在所有侧面上屏蔽集成电路，使得集成电路位于平台上。但是，可以在平台和周围基板之间形成系绳，以支撑平台，并提供沿其可以进行电连接的导管。
使用沟槽作为到达平台下方的点的路径，可以使用各向同性蚀刻在平台下方形成空腔。可以形成单个空腔，以完全底切平台。可替代地，可以形成多个空腔，这些空腔不完全底切平台。例如，可以在平台的下方并在平台的中央形成基座，以便为平台提供支撑。
通过利用沟槽和空腔的组合，可以实现机械应变隔离的显着改善。基座和系绳的使用为集成电路平台提供了足够的支撑，而系绳还为电导体提供了将电路耦合到外部连接的导管。
本公开特别适合与包括许多有源组件的有源电路一起使用，这些有源组件可能易于改变其特性。例如，有源电路可以包括利用双极结型晶体管，场效应晶体管和运算放大器的组合的电路。它们可能包括放大器电路、电源管理电路、基准电压源、转换器或隔离器、以及许多其他众所周知的电路。
本公开可以与各种不同的半导体制造工艺一起使用。例如，它可以与CMOS和双极结型晶体管制造工艺一起使用。然而，本公开发现了BiCMOS制造工艺的特定应用。在同一IC上结合了BJT和CMOS器件的BiCMOS器件对器件参数的变化特别敏感。因此，机械隔离对于BiCMOS电路可能起特别重要的作用。
图1示出了集成电路100。集成电路100可以包括电路组件101。电路组件101可以例如是参考电路的组件。组件101可以经由未示出的金属迹线连接到其他电路组件。集成电路100可以由绝缘体上硅(SOI)晶片形成。即，半导体晶片包括操作硅的基层，器件硅的层以及在它们之间形成的绝缘氧化物的层。SOI晶片在集成电路设计中越来越普遍，并且对于本公开特别有用。如图1所示，存在一层处理硅102，以及在处理硅102上方形成的氧化物层103。氧化层103是介电绝缘体，并且可以例如是氧化硅。一层器件硅104形成在氧化物层103上方。另一层氧化物105形成在器件硅104之上。氧化物层104可以包括氧化物和金属化的多层，并且可以包括层间电介质(ILD)和金属间电介质(IMD)。集成电路100的组件101可以形成在器件硅层104和氧化物层105中。组件101的形成方式对于本领域技术人员而言将是熟悉的，并且在这里将不再进一步详细描述。
沟槽106A和106B使用深硅蚀刻形成在电路组件101的任一侧。下面将描述处理步骤的更多细节。在该示例中，示出了两个沟槽，它们不外接电路组件，而是彼此分开。将理解的是，可以提供沟槽的数量、沟槽的形状和沟槽的接近度的各种不同组合，并且这将在下面更详细地描述。沟槽106A、106B分别设置有侧壁保护107A、107B、107C和107D。侧壁保护可以是在形成沟槽之后沉积的氧化物层。集成电路100还设有空腔108。如图1所示，沟槽一直延伸到氧化物层103。空腔形成在处理硅层102中的电路组件101下方的空间中。在该示例中，在使用各向同性蚀刻形成沟槽之后形成空腔。下面将进一步描述。尽管未示出，但是电路组件101通过由沟槽之间的区域形成的系绳被束缚到集成电路100的其余部分。可以将集成电路100上形成有组件101的部分视为应力隔离表109。因为该表109通过沟槽106A和106B与操作硅102隔离并且与器件硅和氧化物的周围层隔离，所以组件101比上述现有技术的器件易受明显更少的机械应力。
现在将参考图2和图3描述制造图1所示的集成电路100的过程。
图2A示出了过程中的第一步中的集成电路100，其中提供包括电路组件101的SOI晶片(S300)。在该过程的此阶段，集成电路100与没有本公开的机械应力隔离方面的任何其他集成电路相同。如图2B所示，使用掩模在氧化物层105上提供光致抗蚀剂层110，以暴露将在其中形成沟槽的区域(S301)。从图2B中可以看出，有两个开口111A和111B。然后，使用深硅蚀刻来形成沟槽，以将其切下至操纵硅102(S302)。
然后去除光刻胶层110，并且在沟槽106A、106B衬有侧壁保护，这可以通过在沟槽的侧壁上沉积氧化物层来实现(S303)。可以看出，侧壁保护107A、107B、107C和107D形成在沟槽106A和106B的壁上。
一旦侧壁保护就位，就可以开始腔蚀。这通过沟槽106A和106B两者使用受控的各向同性蚀刻来完成(S304)。以这种方式蚀刻有效地在每个沟槽中产生两个空腔，并且随着空腔尺寸的增加，它们在中间接合以对电路组件101进行底切。
在接近诸如晶体管的有源电路组件的附近形成沟槽的问题之一是泄漏电流会传播通过沟槽壁。使用钝化层保护沟槽壁，以减少泄漏电流。
将认识到，上述过程可以从非SOI晶片开始，并且可以使用公认的制造技术来制造硅和氧化物的各种层。
图4是图1所示的集成电路100的平面图。图1所示的截面由虚线AA-表示。如图4所示，示出了沟槽106A和106B。在这些沟槽之间是电路组件101。另外，还示出了沟槽112A和112B。这些未在图1中标识，因为它们在横截面AA-中不存在。沟槽112A和112B在尺寸和形状上可以与沟槽106A和106B相同，但是它们与沟槽106A和106B正交。这些沟槽也可以用来形成空腔108(图4中未示出)，并因此向下延伸至空腔108。沟槽106A、106B、112A和112B限定了工作台109的周边。工作台109通过系绳113A至113D物理地耦合至周围结构。沟槽和系绳的图案是在制造过程的光致抗蚀剂阶段由掩模形成的。
上述集成电路100非常好地将电路组件101与周围结构所经受的机械应力隔离开。因为工作台109与周围结构之间的唯一物理耦合是通过系绳113A至113D，所以可以将机械应力从周围结构传递到工作台109的物理连接被最小化。
本公开还提供了许多沟槽和系绳的替代布置，这些替代布置被认为在将平台109与机械应力隔离方面特别好。
图5示出了将系绳的数量最小化为两个的布置。通过使用两个系绳，可以将系绳元件制成足够弱的结构，以将最小的应力传递到工作台上，但是要足够坚固，以机械方式支撑工作台。图5示出了包括电路组件501的集成电路500。在该示例中，以使台503通过两个系绳504A和504B耦合到周围结构的方式形成两个沟槽502A和502B。系绳都是S形的，每个都将工作台503的各个角连接到工作台503的相邻角附近的周围结构上的一点。每个沟槽包括第一部分505A和505B，它们并排延伸并限定了相对的位置。每个沟槽都包括另一部分506A、506B，其沿着并排延伸并限定了桌面503的正交侧和相对侧。部分506A、506B耦合到相应的部分505A和505B，使得每个沟槽以L形围绕工作台503的两个相邻侧。每个沟槽还包括部分507A、507B，其在部分505A、505B与部分506A和506B的相对端处与每个相应的沟槽接合。部分507A、507B平行于部分506A、506B并且正交于部分505A和505B，并且进一步限定了S形系绳504A和504B。这种布置在将平台503与周围结构隔离方面提供了优点。
图6是模拟图，示出了具有系留台的集成电路所经受的机械应力。该布置类似于下面的图8A所示。仿真显示了在很大的机械应力下桌子周围的区域。以白色显示。尽管周围结构和系绳的某些区域承受压力，但桌子的大部分本身并未承受较大的压力。这样，该桌子适用于容纳具有应力相关特性的组件。
图7示出了包括电路组件701的集成电路700的示例。在该示例中，在台703的三个侧面上提供了单个沟槽702。在台703的一侧上向下延伸的单个系绳704被提供。沟槽702包括部分705A、705B、705C。部分705B来自系绳704的对面，其中部分705A和705C彼此平行地形成，并且与部分705B正交。这种布置形成了用于反向C形沟槽的悬臂。
图8A至8F示出了集成电路、平台和系绳的布置的各种其他示例。图8A示出了集成电路800A，其类似于集成电路500，除了它包括四个系绳而不是两个。集成电路800A包括电路组件801A。在该示例中，以这样的方式形成四个沟槽802A、803A、804A和805A，使得工作台806A通过四个系绳807A、808A、809A和810A耦合到周围结构。系绳及其各自的沟槽为L形。每个系绳将桌子806A的各个角耦接到周围结构上靠近桌子806A的相邻角的点。每个沟槽沿着工作台806A的两个相邻侧面延伸。这种布置进一步使工作台806A与周围结构中的机械应力隔离。
图8B示出了集成电路800B的另一示例。在该示例中，该表在几个方面与图8A所示的相似。通用组件将使用相同的附图标记表示，包括“B”后缀而不是“A”后缀。除了图8A所示的特征之外，集成电路800B包括五组组件，由数字801B-1至801B-5表示。在这组组件之间是四个开口或沟槽811B-1至811B-4。这种布置使得能够在桌子上形成多于一组的组件，并且开口811B-1至811B-1的作用进一步减小了应力对每组的影响。将理解的是，取决于桌子806B的尺寸，可以实现开口的数量和组件的组的不同数量和布置。
图8C示出了集成电路800C的另一示例。在该示例中，该表在几个方面与图8A所示的相似。通用组件将使用相同的附图标记表示，包括“C”后缀而不是“A”后缀。在该示例中，电路800C包括六个沟槽802C、803C-1、803C-2、804C-1、804C-2和805C，以及六个系绳807C、808C-1、808C-2、809C-1、809C-2和810C。桌子806C在竖直方向上是细长的，从而为部件提供了额外的空间。这样，在该示例中，表格包括组件801C-1和801C-2的组。
图8D示出了集成电路800D的另一示例。在该示例中，该表在几个方面与图8A所示的相似。通用组件将使用相同的附图标记表示，包括“D”后缀而不是“A”后缀。该示例也类似于图7，并且示出了单个系绳807D和单个沟槽802D。部件和开口的布置类似于图8B所示。
图8E和8F示出了集成电路800E和800F的另外两个例子。在这些示例中，这些表在某些方面与图8A所示的表相似。通用组件将使用相同的附图标记表示，并将包括“E”或“F”后缀而不是“A”后缀。这些示例显示了单个系绳布置，其中系绳在桌子周围形成螺旋形。
以上所有示例均显示了各种使表格与周围结构隔离的布置。优选的布置将根据许多要求而变化，例如电路组件、尺寸限制和其他设计考虑。将理解，本公开不限于这些布置中的任何布置，并且在权利要求的范围内其他设计是可能的。
图9示出了根据本公开的另一替代示例的集成电路900的横截面。此示例类似于图1中所示的示例，但是空腔并未完全切入工作台。集成电路900包括处理硅902、氧化层903、器件硅层904和上介电层905。图9还以类似于图1所示的方式示出了两个沟槽906A、906B，但是在该示例中，沟槽将完全围绕工作台909，这将在下面更详细地描述。沟槽衬有保护性氧化物层907A至907D，并且沟槽908形成在工作台909下方。基座910形成在工作台909下方。
图10示出了图9的集成电路900的平面图。图10示出了围绕台909的单个沟槽，并且包括来自图9的沟槽906A和906B。在台909的中心处的虚线是由空腔908形成的台座910。可以看出，在这种布置中，工作台909与周围结构之间没有系绳，工作台与该结构的其余部分之间唯一的物理连接是基座910。将理解的是，需要在电路901和外部连接之间进行电连接，并且这可以通过结合线(未示出)来完成，所述结合线耦合在工作台909上的连接与周围结构上的连接之间。作为替代方案，可以在桌子和周围结构之间的单个点处提供半导体结构中的物理系绳，以便进行电连接。在这方面，也可以使用金属桥接结构。
图11A至11C示出了制造包括机械隔离的部件的集成电路的替代方法。在形成沟槽之后，不是使用各向同性蚀刻来形成空腔，而是向晶片提供了预先形成的空腔。如图11A所示，该过程的第一步是提供一种在其上表面上形成有凹槽1101的晶片。然后将包括电路组件的标准电路晶片粘结到晶片1100的上表面。这在图11B中示出，其中电路晶片1102与晶片1100结合以形成空腔1101。然后以与图1所示的集成电路100相同的方式形成沟槽1103A和1103B。这样，包括电路组件1105的工作台1104形成在空腔1101上方。与前面的示例一样，沟槽和空腔的布置可以采取许多不同的形式。
图12示出了集成电路1200的另一示例，类似于图5中所示的集成电路。图12示出了包括电路组件1201的集成电路1200。在该示例中，两个沟槽1202A和1202B以桌子1203通过两个系绳1204A和1204B耦合到周围结构的方式形成。系绳均为S形，每个系绳将工作台1203的各个角耦接到周围结构上工作台1203的相邻角附近的点。每个沟槽包括第一部分1205A和1205B，第一部分1205A和1205B并排延伸并限定台1203的相对侧。每个沟槽包括另外的部分1206A、1206B，其并排延伸并限定台1203的正交和相对侧。部分1206A、1206B耦合到相应的部分1205A和1205B，使得每个沟槽以L形围绕工作台1203的两个邻接侧。每个沟槽还包括部分1207A、1207B，其在部分1205A、1205B与部分1206A和1206B的相对端处与每个相应的沟槽接合。部分1207A、1207B平行于部分1206A、1206B并且正交于部分1205A和1205B，并且进一步限定了S形系绳1204A和1204B。
另外，导电迹线嵌入在系绳中，以便为电路组件1201提供外部连接。特别地，电路包括导电迹线1210A、1210B和1210C。这些迹线可以是嵌入在基板层和绝缘材料之间的金属化层。每个轨道与外部连接1211A、1211B和1211C建立连接。
在以上示例中，SOI晶片用作隔离平台的起点。本公开还可以使用非SOI晶片来实现。图13示出了根据本公开的另一替代示例的集成电路1300的横截面。该示例与图9中所示的示例相似，但是硅基板不是绝缘体上硅(SOI)晶圆。集成电路1300包括硅基板1301和上介电层1302。图13还以与图9所示的方式相似的方式示出了两个沟槽1303，其完全围绕工作台1304。这些沟槽衬有保护性氧化物层1305，并且在工作台1304下方形成了空腔1306。在工作台1304下方形成了基座1307。在硅基板1301的上部中形成集成电路组件1308。非SOI示例以与SOI晶片示例相似的方式制造。但是，因为沟槽穿透基板，所以可以使用定时蚀刻，而不是使用仅穿透硅层而不穿透下一层的仅硅或仅氧化物蚀刻。
应用范例
如上所述，本公开可以与参数可能受到应力或应变影响的任何电路一起使用。特别地，利用诸如晶体管的有源部件的电路可以在利用本公开的应力减轻装置中找到特别的益处。在下文中，我们提供了申请人已知的遭受应力引起的性能问题的电路的示例。
放大器：如果存在压力，放大器的精度可能会发生漂移。例如，精密运算放大器的输入级对输入级的晶体管参数非常敏感。如果差分输入级中晶体管的参数由于基板上的应力而有所不同，则放大器的整体精度将会漂移。其他放大器级也可能发生这种情况。
参考电路：参考电路也可以使用差分电路，包括差分晶体管配置。当应力施加于差动装置时，基准的输出可能会漂移。
数模转换器(DAC)：DAC通常使用一串精密电阻。如果这些电阻承受压力，则电阻会发生变化，这会导致DAC精度下降。
振荡器电路：在数字、射频和动态应用中，诸如环形振荡器之类的振荡器电路使用晶体管和电阻器来产生参考频率或参考时钟。晶体管或电阻器中产生的应力可能导致参考频率或时钟漂移。
在以上每个示例中，可以使用应力降低来提高电路的精度。图12的电路组件1201可以代表任何上述电路的组件。本公开适用于各种集成电路，特别是应力敏感有源电路组件的那些集成电路。为了提高精度，可以使用本公开来实现被设计为使用晶体管和电阻器来产生精确输出的任何电路。应当理解，除了上面列出的那些之外，应力还可能影响广泛的电路的参数，并且本公开不限于这里列出的任何示例。
根据本申请的一方面，提供了集成电路，包括：集成电路管芯，具有一个或多个应力敏感电路，所述应力敏感电路包括在所述集成电路管芯的第一表面上或附近形成的有源电路组件；在所述一个或多个应力敏感电路周围形成一个或多个沟槽；和在所述一个或多个应力敏感电路下面形成一个或多个空腔。在一些实施方案中，所述一个或多个空腔物理上耦合到所述一个或多个沟槽。在上述实施方案的任一个中，一个或多个空腔可以并且在至少一种实施方案中，在一个或多个沟槽下延伸。在上述实施方案的任一个中，一个或多个沟槽和一个或多个空腔可以并且在至少一种实施方案中，被配置为形成电路平台，在所述集成电路管芯中，所述一个或多个应力敏感电路形成在所述电路平台上。在一些实施方案中，例如上面所述，所述一个或多个沟槽和所述一个或多个空腔被配置为形成一个或多个系绳，每个系绳将所述电路平台物理耦合到周围的集成电路管芯。在一些实施方案中，例如上面所述，每个系绳将所述电路平台上的相应的第一点耦合到周围的集成电路管芯上的相应的第二点，所述第一和第二点位于不同的圆周位置。在一些实施方案中，例如上面所述，所述电路平台和所述周围的集成电路管芯具有多个拐角，所述电路平台的拐角与所述集成电路管芯的各个拐角对齐，并且其中所述一个或多个系绳中的每一个都耦合在所述电路平台的拐角和与该电路平台的各个拐角不对齐的集成电路管芯的拐角之间。在一些实施方案中，例如上面所述，每个系绳可以并且在一些实施方案中，包括主臂构件，该主臂构件布置成基本平行于所述电路平台的相应侧。在一些实施方案中，例如上面所述，集成电路还包括沿着所述一个或多个系绳形成的一个或多个导电轨道，用于将所述一个或多个应力敏感电路耦合到外部连接。在上述实施方案的任一个中，一个或多个沟槽可以并且在至少一种实施方案中，为L形；并且每个L形沟槽的拐角与所述电路平台的拐角对齐。在上述实施方案的任一个中，可以并且在至少一种实施方案中，在所述电路平台下方形成基座，所述电路平台耦合到所述集成电路管芯。在上述实施方案的任一个中，可以并且在至少一种实施方案中，所述一个或多个应力敏感电路包括无源电路组件，而所述有源或无源电路组件对应力敏感。在上述实施方案的任一个中，有源电路组件可以并且在至少一种实施方案中，包括下列中的一个或多个：晶体管、二极管、可变电容器、变容二极管、发光二极管和晶闸管；并且所述应力敏感电路包括下列中的一个或多个：放大器、参考电路、振荡器电路或数模转换器。在上述实施方案的任一个中，一个或多个应力敏感电路可以并且在至少一种实施方案中，包括以差分布置的两个或多个晶体管。在上述实施方案的任一个中，集成电路可以并且在至少一种实施方案中，还包括形成在所述一个或多个应力敏感电路上方的微机电系统(MEMS)盖。
根据本申请的一方面，提供一种制造集成电路的方法，包括：提供集成电路管芯；在所述集成电路管芯的第一表面上或附近形成包括有源电路组件的一个或多个应力敏感电路；在所述一个或多个应力敏感电路附近形成一个或多个沟槽；和在所述一个或多个应力敏感电路下面形成空腔。在一些实施方案中，所述集成电路管芯由硅制成，并且所述一个或多个沟槽使用深硅蚀刻形成。在上述实施方案中，空腔可以并且在至少一种实施方案中，经由所述一个或多个沟槽利用各向同性蚀刻形成，并且其中所述一个或多个沟槽和所述空腔形成平台，在该平台上形成一个或多个应力敏感电路。
根据本申请的一方面，提供一种制造集成电路的方法，包括：提供在其第一表面中形成有空腔的晶片；将集成电路管芯结合到所述晶片的第一表面；和在所述集成电路管芯的第一表面中形成一个或多个沟槽。在所述一个或多个沟槽形成的区域内，在所述集成电路管芯的第一表面上或附近形成包括有源电路组件的一个或多个应力敏感电路。在一些实施方案中，所述一个或多个沟槽穿过所述集成电路管芯延伸到所述空腔；和由所述一个或多个沟槽形成的区域是由所述一个或多个沟槽和所述空腔限定的平台；和其中在结合到所述晶片之前，在所述集成电路管芯上形成所述一个或多个应力敏感电路；或在结合到所述所述晶片之后但在形成所述一个或多个沟槽之前形成所述有源电路组件。
上面已经使用术语“上方”和“下方”来表示某些图中各个组件的相对方向。将理解的是，这些术语仅用于描述相对于附图的取向，并且在实际的实施方式中，取向可以不同。

Claims (20)

1.集成电路，包括：
集成电路管芯，具有一个或多个应力敏感电路，所述应力敏感电路包括在所述集成电路管芯的第一表面上或附近形成的有源电路组件；
在所述一个或多个应力敏感电路周围形成一个或多个沟槽；和
在所述一个或多个应力敏感电路下面形成一个或多个空腔。
2.权利要求1所述的集成电路，其中所述一个或多个空腔物理上耦合到所述一个或多个沟槽。
3.权利要求1所述的集成电路，其中所述一个或多个空腔在所述一个或多个沟槽下延伸。
4.权利要求1所述的集成电路，其中所述一个或多个沟槽和所述一个或多个空腔被配置为形成电路平台，在所述集成电路管芯中，所述一个或多个应力敏感电路形成在所述电路平台上。
5.权利要求4所述的集成电路，其中所述一个或多个沟槽和所述一个或多个空腔被配置为形成一个或多个系绳，每个系绳将所述电路平台物理耦合到周围的集成电路管芯。
6.权利要求5所述的集成电路，其中每个系绳将所述电路平台上的相应的第一点耦合到周围的集成电路管芯上的相应的第二点，所述第一和第二点位于不同的圆周位置。
7.权利要求6所述的集成电路，其中所述电路平台和所述周围的集成电路管芯具有多个拐角，所述电路平台的拐角与所述集成电路管芯的各个拐角对齐，并且其中所述一个或多个系绳中的每一个都耦合在所述电路平台的拐角和与该电路平台的各个拐角不对齐的集成电路管芯的拐角之间。
8.权利要求7所述的集成电路，其中每个系绳包括主臂构件，该主臂构件布置成基本平行于所述电路平台的相应侧。
9.权利要求5所述的集成电路，还包括沿着所述一个或多个系绳形成的一个或多个导电轨道，用于将所述一个或多个应力敏感电路耦合到外部连接。
10.权利要求4所述的集成电路，其中所述一个或多个沟槽为L形；并且每个L形沟槽的拐角与所述电路平台的拐角对齐。
11.权利要求4所述的集成电路，其中在所述电路平台下方形成基座，所述电路平台耦合到所述集成电路管芯。
12.权利要求1所述的集成电路，其中所述一个或多个应力敏感电路包括无源电路组件，而所述有源或无源电路组件对应力敏感。
13.权利要求1所述的集成电路，其中所述有源电路组件包括下列中的一个或多个：晶体管、二极管、可变电容器、变容二极管、发光二极管和晶闸管；并且所述应力敏感电路包括下列中的一个或多个：放大器、参考电路、振荡器电路或数模转换器。
14.权利要求1所述的集成电路，其中所述一个或多个应力敏感电路包括以差分布置的两个或多个晶体管。
15.权利要求1所述的集成电路，还包括形成在所述一个或多个应力敏感电路上方的微机电系统(MEMS)盖。
16.一种制造集成电路的方法，该方法包括:
提供集成电路管芯；
在所述集成电路管芯的第一表面上或附近形成包括有源电路组件的一个或多个应力敏感电路；
在所述一个或多个应力敏感电路附近形成一个或多个沟槽；和
在所述一个或多个应力敏感电路下面形成空腔。
17.根据权利要求16所述的方法，其中所述集成电路管芯由硅制成，并且所述一个或多个沟槽使用深硅蚀刻形成。
18.根据权利要求16所述的方法，其中所述空腔经由所述一个或多个沟槽利用各向同性蚀刻形成，并且其中所述一个或多个沟槽和所述空腔形成平台，在该平台上形成一个或多个应力敏感电路。
19.一种制造集成电路的方法，该方法包括：
提供在其第一表面中形成有空腔的晶片；
将集成电路管芯结合到所述晶片的第一表面；和
在所述集成电路管芯的第一表面中形成一个或多个沟槽；
其中，在所述一个或多个沟槽形成的区域内，在所述集成电路管芯的第一表面上或附近形成包括有源电路组件的一个或多个应力敏感电路。
20.根据权利要求19所述的方法，其中所述一个或多个沟槽穿过所述集成电路管芯延伸到所述空腔；并且由所述一个或多个沟槽形成的区域是由所述一个或多个沟槽和所述空腔限定的平台；并且其中在结合到所述晶片之前，在所述集成电路管芯上形成所述一个或多个应力敏感电路；或在结合到所述所述晶片之后但在形成所述一个或多个沟槽之前形成所述有源电路组件。
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