EP0495005A1 - Die attach structure - Google Patents
Die attach structureInfo
- Publication number
- EP0495005A1 EP0495005A1 EP19900916935 EP90916935A EP0495005A1 EP 0495005 A1 EP0495005 A1 EP 0495005A1 EP 19900916935 EP19900916935 EP 19900916935 EP 90916935 A EP90916935 A EP 90916935A EP 0495005 A1 EP0495005 A1 EP 0495005A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- die
- substrate
- die attach
- central portion
- joint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000009826 distribution Methods 0.000 abstract description 6
- 239000011159 matrix material Substances 0.000 abstract 10
- 238000012546 transfer Methods 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000012815 thermoplastic material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8314—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Definitions
- This invention pertains generally to semiconductor devices and, more particularly to a structure and method for attaching a semiconductor die to a substrate.
- both the transfer of heat between the die and the substrate and the level of stress in the joint are dependent upon the thickness of the joint, with a thinner joint providing better heat transfer but higher stress.
- the thickness of the joint represents a compromise between adequate heat transfer and an acceptable level of stress. This is difficult to realize in practice, particularly with large, high powered chips.
- the invention provides an improved die attach structure and method in which the joint between the die and the substrate is formed in a manner which provides a more uniform temperature distribution in the die and reduces stress in the joint near the edge of the die.
- the substrate is for ed with a non-planar surface in the die attach area, and the joint between the die and the substrate is thicker toward the edge of die than at the center.
- different die attach materials are employed to make the joint stiffer toward the center of the die and more flexible toward the edges.
- both the thickened joint and the different die attach materials are employed.
- Figure 1 is an enlarged fragmentary sectional view of one embodiment of a die attach structure according to the invention.
- Figures 2-4 are views similar to Figure 1 of additional embodiments of a die attach structure according to the invention.
- the invention is illustrated in connection with a generally rectangular semiconductor die 11 and a generally planar substrate 12.
- the die has a planar lower surface 13, and the substrate has a die attach area 14 in which the die is received.
- the die attach area has a raised central portion 16 and a recessed outer portion 17, with the central portion of the die being positioned above the raised central portion of the die attach area and the edges of the die being positioned above the recessed portion of the area.
- the die is bonded to the substrate by a die attach material 19 which fills the region between the lower surface of the die and the surface of the substrate in the die attach area, with a relatively thin joint 21 thus being formed beneath the central portion of the die and a thicker joint 22 being formed beneath the edge portions.
- the raised portion of the die attach area has a planar surface 23, and the recessed portion of the area has a planar surface 24 which is positioned somewhat below the surface of the raised area.
- the lower surface of the die is parallel to these surfaces.
- the thinner joint at the center of the die provides better heat transfer between the die and the substrate in that area and results in a more uniform temperature across the die.
- the thicker joint toward the edges of the die reduces stresses near the edges, although it may make the temperature of the die somewhat higher at the edges than it would be with a thinner joint.
- the higher edge temperature is not a problem, however, and the peak die temperature is actually reduced because of the thinner joint at the center.
- the embodiment of Figure 2 is generally similar to the embodiment of Figure 1, and like reference numerals designate corresponding elements in the two embodiments.
- the edges 26 of the raised central portion of the die attach area are relieved or rounded, and the recessed portion of the area is formed with a concave surface 27. This contouring of the surfaces permits optimization of the temperature and/or stress distribution across the die.
- the upper surface 31 of the central portion of the die attach area has a convex curvature, and the recessed portion has a concave curvature as in the embodiment of Figure 2.
- This contouring of the surfaces permits optimization of the temperature and/or stress distribution over the entire surface of the die.
- the embodiment of Figure 4 is generally similar to the embodiment of Figure 3, and like reference numerals once again designate corresponding elements.
- the edge portions of the die extend beyond the recessed portion of the attach area, and the die is supported by the floor 33 of the attach area. This eliminates the need for a fixture or tooling to hold the die in a level position during assembly, but it does introduce a high stress concentration at the edges of the die.
- the adhesive employed in this embodiment is selected to fail before the edge portions of the die break.
- the thicker and thinner joints can be formed by configuring the lower surface of the die with a non-planar surface rather than forming the contoured mounting surface in the die attach area of the substrate.
- the die and the substrate can both be formed with non-planar or contoured surfaces.
- the die attach material which bonds the die to the substrate can be any suitable material for this purpose.
- Such materials include solder, filled organic adhesives, glass/metal frits, and the like.
- Improved temperature distribution and stress relief can also be provided by using different die attach materials for different portions of the die.
- a relatively strong, stiff material can be employed in the central region where stress is minimal, with a weaker, more flexible material toward the edges where stress is greater.
- the material employed in the center preferably has a high thermal conductivity, and the material employed at the edges can have a lower thermal conductivity.
- Suitable materials include a high strength silver or diamond filled epoxy for the central region, and a modified low-modulus epoxy or a thermoplastic material for the outer region. As will be apparent to those familiar with the art, these are just a few examples of the numerous materials which can be used as the die attach materials.
- the invention has a number of important features and advantages. It improves the joint between a die and a substrate and provides greater tolerance to mechanical stresses in the joint while providing good heat transfer across the joint. Making the joint thicker near the edge of the die than it is near the center reduces stresses near the edge of the die and allows greater heat transfer at the center. The use of a stronger, more thermally conductive die attach material at the center of the joint and a weaker, more flexible material toward the edges can also permit greater heat transfer toward the center and greater tolerance to stresses near the edges. Combining the tapered joint with different attach materials in different regions provides an even greater degree of control over temperature and stress distribution.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Structure et procédé de fixation de matrice dans lesquels la jointure entre une matrice (11) et un substrat (12) est formée de manière assurant une répartition de température uniforme dans la matrice, et réduisant la contrainte dans la jointure à proximité du bord de la matrice. Dans certains modes de réalisation, le substrat se compose d'une surface non plane dans la zone de fixation (14) de la matrice, et la jointure entre ladite matrice et ledit substrat est plus épaisse vers le bord de la matrice qu'au niveau du centre. Dans d'autres modes de réalisation, on emploie différents matériaux (19) de fixation de matrice afin de rendre la jointure plus dure vers le centre de la matrice, et plus souple vers les bords. Dans certains modes de réalisation, on emploie à la fois la jointure épaissie et les différents matériaux de fixation de matrice.A matrix fixing structure and method in which the joint between a matrix (11) and a substrate (12) is formed so as to provide a uniform temperature distribution in the matrix, and reducing stress in the joint near the edge of the matrix. In certain embodiments, the substrate consists of a non-planar surface in the fixing zone (14) of the matrix, and the joint between said matrix and said substrate is thicker towards the edge of the matrix than at the level of the Center. In other embodiments, different matrix fastening materials (19) are used to make the joint harder toward the center of the matrix, and more flexible toward the edges. In some embodiments, both the thickened joint and the various matrix attachment materials are used.
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US41773089A | 1989-10-05 | 1989-10-05 | |
US417730 | 1989-10-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0495005A1 true EP0495005A1 (en) | 1992-07-22 |
Family
ID=23655191
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19900916935 Withdrawn EP0495005A1 (en) | 1989-10-05 | 1990-10-05 | Die attach structure |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0495005A1 (en) |
JP (1) | JPH06502962A (en) |
WO (1) | WO1991005368A1 (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5239131A (en) * | 1992-07-13 | 1993-08-24 | Olin Corporation | Electronic package having controlled epoxy flow |
US20040041254A1 (en) * | 2002-09-04 | 2004-03-04 | Lewis Long | Packaged microchip |
US7166911B2 (en) | 2002-09-04 | 2007-01-23 | Analog Devices, Inc. | Packaged microchip with premolded-type package |
US6946742B2 (en) | 2002-12-19 | 2005-09-20 | Analog Devices, Inc. | Packaged microchip with isolator having selected modulus of elasticity |
DE102004055817B3 (en) * | 2004-11-18 | 2006-01-12 | Danfoss Silicon Power Gmbh | Manufacture procedure for heavy-duty semiconductor modules involves mass of solder to produce solder connection and particles of copper are sprayed into place on solder |
US20060118601A1 (en) * | 2004-12-06 | 2006-06-08 | Brandenburg Scott D | Epoxy-solder thermally conductive structure for an integrated circuit |
JP5252024B2 (en) * | 2011-04-12 | 2013-07-31 | 富士電機株式会社 | Semiconductor device |
JP2014060211A (en) * | 2012-09-14 | 2014-04-03 | Omron Corp | Substrate structure, semiconductor chip mounting method and solid state relay |
JP2014093356A (en) * | 2012-11-01 | 2014-05-19 | Toyota Motor Corp | Semiconductor device |
US9676614B2 (en) | 2013-02-01 | 2017-06-13 | Analog Devices, Inc. | MEMS device with stress relief structures |
US10167189B2 (en) | 2014-09-30 | 2019-01-01 | Analog Devices, Inc. | Stress isolation platform for MEMS devices |
DE102015200980A1 (en) * | 2015-01-22 | 2016-07-28 | Robert Bosch Gmbh | Connecting arrangement between a support element and an electronic circuit component and electronic assembly |
US10131538B2 (en) | 2015-09-14 | 2018-11-20 | Analog Devices, Inc. | Mechanically isolated MEMS device |
JP6163246B1 (en) * | 2016-12-06 | 2017-07-12 | 西村陶業株式会社 | Manufacturing method of ceramic substrate |
US11417611B2 (en) | 2020-02-25 | 2022-08-16 | Analog Devices International Unlimited Company | Devices and methods for reducing stress on circuit components |
US11981560B2 (en) | 2020-06-09 | 2024-05-14 | Analog Devices, Inc. | Stress-isolated MEMS device comprising substrate having cavity and method of manufacture |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59208735A (en) * | 1983-05-13 | 1984-11-27 | Hitachi Ltd | Semiconductor device |
JPS63237534A (en) * | 1987-03-26 | 1988-10-04 | Nec Corp | Die pad structure of lsi chip |
US4903118A (en) * | 1988-03-30 | 1990-02-20 | Director General, Agency Of Industrial Science And Technology | Semiconductor device including a resilient bonding resin |
-
1990
- 1990-10-05 WO PCT/US1990/005731 patent/WO1991005368A1/en not_active Application Discontinuation
- 1990-10-05 EP EP19900916935 patent/EP0495005A1/en not_active Withdrawn
- 1990-10-05 JP JP2515543A patent/JPH06502962A/en active Pending
Non-Patent Citations (1)
Title |
---|
See references of WO9105368A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO1991005368A1 (en) | 1991-04-18 |
JPH06502962A (en) | 1994-03-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0495005A1 (en) | Die attach structure | |
JP3336095B2 (en) | Semiconductor module manufacturing method | |
US5150197A (en) | Die attach structure and method | |
JPH0222540B2 (en) | ||
US20070007280A1 (en) | Method for producing a circuit module | |
CA2512845A1 (en) | Semiconductor package having non-ceramic based window frame | |
GB2450230A (en) | Patterned die attach layer | |
JPS61166051A (en) | Resin seal type semiconductor device | |
KR100330614B1 (en) | Method of improved cavity bga circuit package | |
JP2725448B2 (en) | Semiconductor device | |
JP2655426B2 (en) | Semiconductor device | |
JPH07263618A (en) | Hybrid integrated circuit device | |
JPS6159660B2 (en) | ||
US5757069A (en) | Semiconductor lead frame and packaging method | |
KR100201384B1 (en) | Semiconductor package having a transparency lid | |
JPH08111493A (en) | Semiconductor device | |
JPS63293963A (en) | Resin-sealed semiconductor device | |
JPS6313337A (en) | Process of mounting semiconductor element | |
JP3049410B2 (en) | Semiconductor package | |
JP3482837B2 (en) | Semiconductor device | |
JP2596387B2 (en) | Resin-sealed semiconductor device | |
JP2504465B2 (en) | Semiconductor device | |
JPH0212953A (en) | Package for semiconductor device | |
JPH1027810A (en) | Semiconductor device and manufacture thereof | |
JPH07176563A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19920501 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB IT |
|
17Q | First examination report despatched |
Effective date: 19931125 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
|
18W | Application withdrawn |
Withdrawal date: 19940713 |