JPS63237534A - Die pad structure of lsi chip - Google Patents

Die pad structure of lsi chip

Info

Publication number
JPS63237534A
JPS63237534A JP62072386A JP7238687A JPS63237534A JP S63237534 A JPS63237534 A JP S63237534A JP 62072386 A JP62072386 A JP 62072386A JP 7238687 A JP7238687 A JP 7238687A JP S63237534 A JPS63237534 A JP S63237534A
Authority
JP
Japan
Prior art keywords
lsi chip
die pad
solder
adhesive
pad structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62072386A
Other languages
Japanese (ja)
Inventor
Tsuneaki Tajima
田島　恒明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62072386A priority Critical patent/JPS63237534A/en
Publication of JPS63237534A publication Critical patent/JPS63237534A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To suppress a temperature of a mounted LSI chip low and to improve reliability of products, by forming a central part of a LSI chip's mounting surface so as to be higher than its peripheral part. CONSTITUTION:A die pad 3 is coated with solder or an adhesive 4, and a LSI chip 5 is mounted on the solder or the adhesive 4 so as to be fixed with them. In this case the LSI chip 5 is lightly pressed on the die pad 3. Voids produced under the die pad 3 by this pressing are extruded from a central part 8 to the peripheral part 9 and arrive outside the peripheral part 9. Heat resistance thus becomes small and so a rise in temperature of the LSI chip 5 is suppressed low to improve reliability.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、ＬＳＩチップのダイパッド構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a die pad structure of an LSI chip.

［従来の技術〕 従来、この種のＬＳＩチップのダイパッド構造は、第２
図に示す如き構造となっていた。即ち。[Prior Art] Conventionally, the die pad structure of this type of LSI chip is
The structure was as shown in the figure. That is.

ダイパッド１０は、セラミック基板ｌに積層した多層配
線層２上に形成してあり、ダイパッド１０上には、多層
配線層２上のＯＬＢパッド７にり一ド６を接続させたＬ
ＳＩチップ５が半田又は接着剤４を介して搭載しである
。また、ダイパッド１０は搭載するＬＳＩチップ５の裏
面よりやや大きな面積をもつ平面構造となっていた。The die pad 10 is formed on a multilayer wiring layer 2 laminated on a ceramic substrate l, and on the die pad 10 there is an L in which a lead 6 is connected to an OLB pad 7 on the multilayer wiring layer 2.
An SI chip 5 is mounted via solder or adhesive 4. Furthermore, the die pad 10 had a planar structure with an area slightly larger than the back surface of the LSI chip 5 to be mounted.

［解決すべき問題点］ 上述した如く、従来のダイパッド１０の構造は、平面構
造となっていたため、ＬＳＩチップ５を半田又は接着剤
でダイパッド１０上に固着する場合において、ボイドが
ＬＳＩチップ５とダイパッド１０の間に閉込められ、Ｌ
ＳＩチップ５から発生した熱をダイパッド１０に伝導さ
せる伝熱面積が小さくなる。この結果、熱抵抗が大きく
なり、ＬＳＩチップ５内の温度が上昇し信頼性が低下す
るという欠点がある。また、半田４付けの時のフラック
スや接着剤４の溶剤のガスが前記ボイド部に溜ると、こ
れらフラックスやガスが徐々に浸出し、ＯＬＢパッド７
とリード６とのコンタクト部分に悪影響を及ぼすという
欠点がある。[Problems to be Solved] As mentioned above, the structure of the conventional die pad 10 is a planar structure, so when the LSI chip 5 is fixed onto the die pad 10 with solder or adhesive, voids may be formed between the LSI chip 5 and the die pad 10. Trapped between the die pads 10, L
The heat transfer area for conducting heat generated from the SI chip 5 to the die pad 10 becomes smaller. As a result, the thermal resistance increases, the temperature inside the LSI chip 5 increases, and the reliability decreases. Additionally, if the flux from the solder 4 attachment or the solvent gas from the adhesive 4 accumulates in the void, these fluxes and gases will gradually leak out and cause the OLB pad 7 to leak out.
This has the disadvantage that it has an adverse effect on the contact portion between the lead 6 and the lead 6.

［問題点の解決手段］ 本発明は、上記従来の問題点を解決するためになされた
もので、そのための解決手段として、セラミック基板面
に積層した多層配線層上に形成され、かつ上面がＩ、Ｓ
Ｉチップの搭載面とされたＬＳＩチップのダイパッド構
造において、上記ＬＳＩチップの搭載面中央部を、その
外周部より厚高に形成したことを特徴とするＬＳＩチッ
プのダイパッド構造を提供するものである。[Means for Solving Problems] The present invention has been made in order to solve the above-mentioned problems of the conventional art. , S
The present invention provides a die pad structure for an LSI chip, which is used as a mounting surface for an I chip, in which a central portion of the mounting surface of the LSI chip is formed thicker and higher than its outer peripheral portion. .

［実施例］ 次に、本発明の実施例について図面を参照して説明する
。[Example] Next, an example of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例に係るＬＳＩチップのダイパ
ッド構造を示す断面図である。FIG. 1 is a sectional view showing a die pad structure of an LSI chip according to an embodiment of the present invention.

セラミック基板１表面の多層配線層２上にダイパッド３
が取付けてあり、該ダイパッド３上には、半田又は接着
剤４によりＬＳＩチップ５が固着しである。該ＬＳＩチ
ップ５は、リード６を介して多層配線層２上のＯＬＢパ
ー２ドアと接続している。A die pad 3 is placed on the multilayer wiring layer 2 on the surface of the ceramic substrate 1.
is attached, and an LSI chip 5 is fixed onto the die pad 3 with solder or adhesive 4. The LSI chip 5 is connected to the OLB par 2 door on the multilayer wiring layer 2 via leads 6.

ダイパッド３は、メッキにより形成してあり、その中央
部８が外周部９に比してやや厚高に形成しである。前記
の如く、ダイパッド３はメッキにより形成するが、その
メッキ方法は第１のメッキによりダイパッド３全面をメ
ッキし、第２のメッキによりダイパッド３の中央部のみ
をメッキすることにより行なう。これにより、中央部８
が外周部９より厚高のダイパッド３の構造を得ることが
できる。The die pad 3 is formed by plating, and the central portion 8 is slightly thicker than the outer peripheral portion 9. As described above, the die pad 3 is formed by plating, and the plating method is such that the entire surface of the die pad 3 is plated with the first plating, and only the central portion of the die pad 3 is plated with the second plating. As a result, the central part 8
It is possible to obtain a structure of the die pad 3 which is thicker and taller than the outer peripheral portion 9.

本実施例のダイパラ丁′３上へのＬＳＩチップ５の実装
は、次のように行なう。The LSI chip 5 is mounted on the die plate 3 in this embodiment as follows.

ダイパッド３上に半田又は接着剤４を塗布し、該半田又
は接着剤４上にＬＳＩチップ５をａ置し、半田又は接着
剤４で固着する。このとき、ＬＳＩチップ５を軽くダイ
パッド３に押付ける。Solder or adhesive 4 is applied onto the die pad 3, and the LSI chip 5 is placed a on the solder or adhesive 4 and fixed with the solder or adhesive 4. At this time, the LSI chip 5 is lightly pressed against the die pad 3.

この押付けによってダイパッド３の下に発生したボイド
は、ダイパッド３の中央部８から外周部９に押出され、
外周部９から外部に至る。この結果、ＬＳＩチップ５と
ダイパッド３の間にボイドが存在しなくなり、ボイドに
よる悪影響は回避される。このように、ＬＳＩチップ５
をダイパッド３に固着した後、ＬＳＩチップ５のリード
６をＯＬＢパッド７に接続することによりＬＳＩチップ
５の実装は完了する。The voids generated under the die pad 3 due to this pressing are pushed out from the center part 8 of the die pad 3 to the outer peripheral part 9,
It extends from the outer peripheral portion 9 to the outside. As a result, no void exists between the LSI chip 5 and the die pad 3, and the adverse effects of the void are avoided. In this way, LSI chip 5
After fixing the LSI chip 5 to the die pad 3, the leads 6 of the LSI chip 5 are connected to the OLB pad 7, thereby completing the mounting of the LSI chip 5.

［発明の効果］ 以上説明したように本発明は、ダイパッドのＬＳＩチッ
プ搭載面中央部を外周部より厚高に形成した構造となっ
ているため、搭載したＬＳＩチップの温度を低く押える
ことができ、この結果、製品の信頼性を高めることがで
きる効果がある。[Effects of the Invention] As explained above, the present invention has a structure in which the central part of the LSI chip mounting surface of the die pad is formed thicker and higher than the outer peripheral part, so that the temperature of the mounted LSI chip can be kept low. As a result, the reliability of the product can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例に係るＬＳＩチップのダイパ
ッド構造を示す断面図、第２図は従来のＬＳＩチップの
ダイパッド構造を示す断面図である。FIG. 1 is a sectional view showing the die pad structure of an LSI chip according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the die pad structure of a conventional LSI chip.

Claims (1)

【特許請求の範囲】[Claims] 　セラミック基板面に積層した多層配線層上に形成され
、かつ上面がＬＳＩチップの搭載面とされたＬＳＩチッ
プのダイパッド構造において、上記ＬＳＩチップの搭載
面中央部を、その外周部より厚高に形成したことを特徴
とするＬＳＩチップのダイパッド構造。In a die pad structure of an LSI chip formed on a multilayer wiring layer laminated on a ceramic substrate surface and with the upper surface serving as a mounting surface for the LSI chip, the center part of the mounting surface of the LSI chip is formed thicker and higher than the outer peripheral part thereof. The die pad structure of an LSI chip is characterized by:
JP62072386A 1987-03-26 1987-03-26 Die pad structure of lsi chip Pending JPS63237534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62072386A JPS63237534A (en) 1987-03-26 1987-03-26 Die pad structure of lsi chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62072386A JPS63237534A (en) 1987-03-26 1987-03-26 Die pad structure of lsi chip

Publications (1)

Publication Number Publication Date
JPS63237534A true JPS63237534A (en) 1988-10-04

Family

ID=13487790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62072386A Pending JPS63237534A (en) 1987-03-26 1987-03-26 Die pad structure of lsi chip

Country Status (1)

Country Link
JP (1) JPS63237534A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150197A (en) * 1989-10-05 1992-09-22 Digital Equipment Corporation Die attach structure and method
JPH06502962A (en) * 1989-10-05 1994-03-31 ディジタル　イクイプメント　コーポレイション Die fixing structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150197A (en) * 1989-10-05 1992-09-22 Digital Equipment Corporation Die attach structure and method
JPH06502962A (en) * 1989-10-05 1994-03-31 ディジタル　イクイプメント　コーポレイション Die fixing structure

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