JPH04124843A - Semiconductor circuit device - Google Patents

Semiconductor circuit device

Info

Publication number
JPH04124843A
JPH04124843A JP2244522A JP24452290A JPH04124843A JP H04124843 A JPH04124843 A JP H04124843A JP 2244522 A JP2244522 A JP 2244522A JP 24452290 A JP24452290 A JP 24452290A JP H04124843 A JPH04124843 A JP H04124843A
Authority
JP
Japan
Prior art keywords
leads
circuit device
pads
semiconductor circuit
frame member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2244522A
Other languages
Japanese (ja)
Inventor
Iwao Takiguchi
滝口　岩夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2244522A priority Critical patent/JPH04124843A/en
Publication of JPH04124843A publication Critical patent/JPH04124843A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a semiconductor circuit device of a hybrid integrated circuit device which improves its operability and stabilizes its quality by providing bonding pads of an Al coating layer at the ends of leads. CONSTITUTION:Bonding pads 10 made of aluminum coating layers are provided at the ends of leads 3. For example, an alumina board 5 is made to adhere to a heat sink 7 with silicon resin layer 6, brass leads 3 are fitted in parallel with one set of opposed sides of a frame member 8 of a thermoplastic resin package, and the ends of the leads 3 are secured to both ends of the sink 7. The pads 10 made of the Al coating layers are formed at the ends of the leads 3, an Al base 2 is soldered 4 to conductors made of silver-palladium alloy formed at both ends of the board 5 oppositely to the pads 10, and the pads 10 are connected to the base 2 via Al bonding wires 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は例えば自動車電装品に使用される混成集積回路
装置等の半導体回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor circuit device such as a hybrid integrated circuit device used for example in automobile electrical components.

〔従来の技術〕[Conventional technology]

第４図は従来の半導体回路装置としての混成集積回路装
置の縦断面図であり、第５図は第４図の一部拡大断面図
、第６図は従来の混成集積回路装置の部分破断平面図で
ある。FIG. 4 is a vertical cross-sectional view of a hybrid integrated circuit device as a conventional semiconductor circuit device, FIG. 5 is a partially enlarged cross-sectional view of FIG. 4, and FIG. 6 is a partially broken plane of the conventional hybrid integrated circuit device. It is a diagram.

図中５は例えばアルミナ製の基板であり、基板５は大き
さが基板５より大であるヒートシンク７上にシリコン系
樹脂層６により接着されている。In the figure, reference numeral 5 denotes a substrate made of, for example, alumina, and the substrate 5 is bonded to a heat sink 7, which is larger in size than the substrate 5, with a silicon resin layer 6.

図中８は熱可塑性樹脂製パッケージの枠部材であり、枠
部材８の一組の対向側面には夫々例えば黄銅製のリード
（インサートと称する）３．３・・・が平行に挿嵌され
ており、リード３，３・・・の端部はヒートシンク７の
両側の端部に固定されている。In the figure, reference numeral 8 denotes a frame member of a thermoplastic resin package, and leads (referred to as inserts) 3, 3, etc. made of brass, for example, are inserted and fitted in parallel to a pair of opposing side surfaces of the frame member 8, respectively. The ends of the leads 3, 3, . . . are fixed to both ends of the heat sink 7.

ヒートシンク７は枠部材８の下面内側に設けられた凹み
に嵌め込まれ、接着されている。The heat sink 7 is fitted into a recess provided on the inner side of the lower surface of the frame member 8 and is bonded.

また枠部材８の上面内側にも凹みが設けられており、こ
こにパッケージのカバー９が嵌め込まれている。A recess is also provided inside the upper surface of the frame member 8, into which a package cover 9 is fitted.

リード３，３・・・の端部にはアルミニウム（八１）台
２，２・・・がはんだ（４）付けされている。基板５の
両端には図示しない銀とパラジウムとの合金製の導体部
が印刷焼成されでおり、該導体部には前記Ａ１台２．２
・・・と対向するようにしてＡ１台２，２・・・がはん
だ（４）付けされている。Aluminum (81) bases 2, 2, . . . are soldered (4) to the ends of the leads 3, 3, . Conductor parts made of an alloy of silver and palladium (not shown) are printed and fired on both ends of the substrate 5, and the conductor parts have the above-mentioned A1 unit 2.2.
. . . A1 units 2, 2 . . . are soldered (4) so as to face each other.

そしてリード３．３・・・にはんだ付けされたＡ１台２
，２・・・と基板５の導体部にはんだ付けされたＡ１台
２，２・・・とは、ＡＩ製のボンディングパッド１．１
・・・により接続されている。And A1 unit 2 soldered to lead 3.3...
, 2... and the A1 units 2, 2... soldered to the conductor part of the board 5 are bonding pads 1.1 made of AI.
It is connected by...

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述の混成集積回路装置では、基板５の導体部とリード
３，３・・・とをはんだ付は等により直接接続すると、
夫々の熱膨張係数の差により基板５の導体部が剥離する
という問題があるのでこれらは超音波ワイヤボンディン
グにより接続されている。In the hybrid integrated circuit device described above, when the conductor portion of the board 5 and the leads 3, 3, etc. are directly connected by soldering or the like,
Since there is a problem that the conductor portions of the substrate 5 may peel off due to the difference in their respective thermal expansion coefficients, these are connected by ultrasonic wire bonding.

このときり一部３．３・・・及び基板５の導体部は、ボ
ンディングパッド１，１・・・と直接接続することは材
質が異なるため困難であり、夫々Ａ１台２，２・・・を
してボンディングパッド１．１・・・と接続されている
。At this time, it is difficult to directly connect the cutout parts 3.3... and the conductor parts of the substrate 5 to the bonding pads 1, 1... because they are made of different materials, and the A1 units 2, 2... and are connected to bonding pads 1.1...

そしてリード３，３・・・に４１台２，２・・・をはん
だ付けするときには、４１台２，２・・・の表面が平坦
であり清浄であること、はんだ付けの位置が正確である
こと等が要求されており、これらにばらつきがあると品
質が安定しないという問題があった。When soldering 41 units 2, 2... to leads 3, 3..., the surfaces of 41 units 2, 2... must be flat and clean, and the soldering positions must be accurate. There is a problem that if there are variations in these, the quality will be unstable.

本発明は斯かる事情に鑑みてなされたものであり、例え
ばインサート等のリードの端部にＡ１台をはんだ付けす
る代わりに、ＡＩ！被覆層からなるポンディングパッド
を形成することにより、作業性が向上し、品質が安定す
る、例えば混成集積回路装置等の半導体回路装置を提供
することを目的とする。The present invention was made in view of the above circumstances, and instead of soldering an A1 unit to the end of a lead such as an insert, for example, an AI! It is an object of the present invention to provide a semiconductor circuit device, such as a hybrid integrated circuit device, in which workability is improved and quality is stabilized by forming a bonding pad made of a covering layer.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係る半導体回路装置は、リードの端部にｉ台を
はんだ付けする代わりに、ｉ蒸着又はへｌクラッドによ
りホンディングパットとしての１［被覆層を形成したも
のである。In the semiconductor circuit device according to the present invention, instead of soldering the i-mount to the end of the lead, a covering layer is formed as a bonding pad by i-evaporation or heli-cladding.

〔作用〕[Effect]

本発明の半導体回路装置にあっては、予め前工程として
、リードにすべき板材の端部にＩｆ蒸着又はＡ１クラッ
ドによりＡｌ被覆層を形成してからリードを製造するの
で、リードにｉ台をはんだ付けする場合の作業の煩雑さ
、困難性がない。In the semiconductor circuit device of the present invention, as a pre-process, an Al coating layer is formed on the end of the plate material to be made into a lead by If vapor deposition or A1 cladding, and then the leads are manufactured. There is no complexity or difficulty in soldering work.

〔実施例〕〔Example〕

以下、本発明をその実施例を示す図面に基づいて具体的
に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof.

第１図に本発明に係る半導体回路装置としての混成集積
回路装置の縦断面図を示す。FIG. 1 shows a longitudinal sectional view of a hybrid integrated circuit device as a semiconductor circuit device according to the present invention.

第２図は第１図の一部拡大断面図である。FIG. 2 is a partially enlarged sectional view of FIG. 1.

図中５は例えばアルミナ製の基板であり、基板５は大き
さが基板５より大であるヒートシンク７上にシリコン系
樹脂層６により接着されている。In the figure, reference numeral 5 denotes a substrate made of, for example, alumina, and the substrate 5 is bonded to a heat sink 7, which is larger in size than the substrate 5, with a silicon resin layer 6.

図中８は熱可塑性樹脂製パッケージの枠部材であり、枠
部材８の一組の対向側面には夫々例えば黄銅製のリード
（インサートと称する）３，３・・・が平行に挿嵌され
ており、リード３，３・・・の端部はヒートシンク７の
両側の端部に固定されている。8 in the figure is a frame member of a thermoplastic resin package, and leads (referred to as inserts) 3, 3, etc. made of brass, for example, are inserted and fitted in parallel to a pair of opposing side surfaces of the frame member 8, respectively. The ends of the leads 3, 3, . . . are fixed to both ends of the heat sink 7.

ヒートシンク７は枠部材８の下面内側に設けられた凹み
に嵌め込まれ、接着されている。The heat sink 7 is fitted into a recess provided on the inner side of the lower surface of the frame member 8 and is bonded.

また枠部材８の上面内側にも凹みが設けられており、こ
こにパッケージのカバー９が嵌め込まれている。A recess is also provided inside the upper surface of the frame member 8, into which a package cover 9 is fitted.

リード３．３・・・の端部にはＡｌ被覆層からなるポン
ディングパッド１０，１０・・・が形成されている。Bonding pads 10, 10, . . . made of an Al coating layer are formed at the ends of the leads 3, 3, .

ホンディングパット１０．１０・・・の厚みはＡ１蒸着
により形成した場合３〜５μｍであり、ｉクラッドによ
り形成した場合５０〜１００　μｍである。基板５の両
端には図示しない銀とパラジウムとの合金からなる導体
部が印刷焼成されており、該導体部にはホンディングパ
ット１０．１０・・・と対向するようにして４１台２，
２・・・がはんだ（４）付けされている。The thickness of the honding pads 10, 10, . . . is 3 to 5 μm when formed by A1 vapor deposition, and 50 to 100 μm when formed by i-cladding. Conductor parts made of an alloy of silver and palladium (not shown) are printed and fired on both ends of the substrate 5, and 41 units 2, 2, and 41 are mounted on the conductor parts so as to face the bonding pads 10, 10, and so on.
2... is soldered (4).

そしてホンディングパット１０１０・・・とＡβ台２゜
２・・・とはＡＩ製のボンディングパッド１．１・・・
により接続されている。And the bonding pad 1010... and the Aβ stand 2゜2... are the AI bonding pads 1.1...
connected by.

第３図は本発明の混成集積回路装置の製造工程を示す平
面図である。まず、第３図（ａ）に示したように例えば
黄銅製のリード材の一端部に蒸着によりＡＡ蒸着膜を形
成する。次に第３図（ｂｌに示したようにリード材の他
端部を固定して打抜きを行い、櫛状の打抜き材を形成す
る。そして第３図（Ｃ１に示したようにリード３．３・
・・が枠部材８の対向する１組の側面に夫々挿嵌された
形にモールド成形し、前記他端部を切断する。FIG. 3 is a plan view showing the manufacturing process of the hybrid integrated circuit device of the present invention. First, as shown in FIG. 3(a), an AA vapor deposition film is formed on one end of a lead material made of brass, for example, by vapor deposition. Next, as shown in Figure 3 (bl), the other end of the lead material is fixed and punched to form a comb-shaped punched material.Then, as shown in Figure 3 (C1), the lead material 3.・
... are respectively inserted and fitted into a pair of opposing side surfaces of the frame member 8, and the other end portions are cut.

次にヒートシンク７を枠部材８の下面内側の凹みに貼設
してリード３．３・・・をヒートシンク７の両端の上に
固定し、リード３．３・・・のホンディングパット１０
．１０・・・と基板５の導体部に設けられたｉ台２，２
・・・とをボンディングパッド１，１・・・により超音
波ワイヤボンディングする。そして、枠部材８の上面内
側の凹みにカバー９を貼設する。Next, the heat sink 7 is attached to the recess on the inside of the lower surface of the frame member 8, the leads 3.3... are fixed on both ends of the heat sink 7, and the honda pads 10 of the leads 3.3...
．． 10... and i stands 2, 2 provided on the conductor part of the board 5
. . . are subjected to ultrasonic wire bonding using bonding pads 1, 1 . Then, a cover 9 is attached to the recess inside the upper surface of the frame member 8.

以上の如くして本発明ではリート３，３・・・の端部に
容易にホンディングパッド１０．１０・・・を形成する
ことができる。As described above, according to the present invention, the bonding pads 10, 10, . . . can be easily formed at the ends of the reams 3, 3, .

なお、上述の第３図の説明ではＡ１蒸着によりポンディ
ングパッドを形成する場合につき説明しているが、何ら
これに限定されるものではなく、リードに被覆Ａβ板を
密着させ、熱間圧延する方法（クラッド）を採用するこ
とにしてもよい。In addition, in the explanation of FIG. 3 above, the case where the bonding pad is formed by A1 vapor deposition is explained, but the invention is not limited to this in any way. You may decide to adopt the method (cladding).

さらに本発明の実施例では混成集積回路装置として構成
した場合につき説明しているが、何らこれに限定される
ものではなく、他の半導体回路装置に適用できることは
言うまでもない。Furthermore, although the embodiments of the present invention have been described with reference to a case where the present invention is configured as a hybrid integrated circuit device, it goes without saying that the present invention is not limited to this and can be applied to other semiconductor circuit devices.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く、本発明の半導体回路装置では、予め
リードにすべき板材の端部にＡｆｆｉ着又はへｌクラッ
ドによりへｐ被覆層を形成してからリードを構成するの
で、リードにへ１台をはんだ付けする場合の作業の煩雑
さ、困難性がなくなり、また安価にホンディングパッド
を設けることがてきる。As described in detail above, in the semiconductor circuit device of the present invention, since the lead is formed after forming the hep coating layer on the end of the plate material to be made into the lead by Affi deposition or hel cladding, the lead is The complexity and difficulty of soldering the base are eliminated, and the soldering pad can be provided at low cost.

そして従来のようにはんだ付けの位置がばらつく等の問
題がなくなるので装置の品質が安定する等、本発明は優
れた効果を奏するものである。Further, the present invention has excellent effects such as the quality of the device being stabilized since there are no problems such as variations in soldering positions as in the conventional method.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明に係る混成集積回路装置の縦断面図、第
２図は第１図の一部拡大断面図、第３図は本発明に係る
混成集積回路装置の製造工程を示す平面図、第４図は従
来の混成集積回路装置の縦断面図、第５図は第４図の一
部拡大断面図、第６図は従来の混成集積回路装置の部分
破断平面図である。 １・・・ボンディングパッド　２・・・ｉ台　３・・・
リード　４・・・はんだ層　５・・・基板　６・・・シ
リコン系樹脂層　７・・・ヒートシンク　８・・・枠部
材　９・・・カバー　１０・・・ホンディングパッド なお、図中、同一符号は同一、又は相当部分を示す。 代理人　　　大　　　岩　　　増　　　雄１０・・・ボ
“ンデンンク″ハ９ヅド 第 を 図 ｒ〜 図FIG. 1 is a vertical cross-sectional view of a hybrid integrated circuit device according to the present invention, FIG. 2 is a partially enlarged cross-sectional view of FIG. 1, and FIG. 3 is a plan view showing the manufacturing process of the hybrid integrated circuit device according to the present invention. , FIG. 4 is a longitudinal sectional view of a conventional hybrid integrated circuit device, FIG. 5 is a partially enlarged sectional view of FIG. 4, and FIG. 6 is a partially cutaway plan view of the conventional hybrid integrated circuit device. 1... Bonding pad 2... i unit 3...
Lead 4...Solder layer 5...Substrate 6...Silicon resin layer 7...Heat sink 8...Frame member 9...Cover 10...Honding pad Note that the same reference numerals are used in the drawings. indicate the same or equivalent part. Agent Masuo Oiwa 10...Bondennku's 9th figure.

Claims (1)

【特許請求の範囲】[Claims] （１）リードの端部にアルミニウム被覆層からなるボン
ディングパッドを設けたことを特徴とする半導体回路装
置。(1) A semiconductor circuit device characterized in that a bonding pad made of an aluminum coating layer is provided at the end of a lead.
JP2244522A 1990-09-14 1990-09-14 Semiconductor circuit device Pending JPH04124843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2244522A JPH04124843A (en) 1990-09-14 1990-09-14 Semiconductor circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2244522A JPH04124843A (en) 1990-09-14 1990-09-14 Semiconductor circuit device

Publications (1)

Publication Number Publication Date
JPH04124843A true JPH04124843A (en) 1992-04-24

Family

ID=17119939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2244522A Pending JPH04124843A (en) 1990-09-14 1990-09-14 Semiconductor circuit device

Country Status (1)

Country Link
JP (1) JPH04124843A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000036511A (en) * 1998-07-01 2000-02-02 Motorola Inc Manufacture of electronic part
US6042442A (en) * 1996-02-28 2000-03-28 Nec Corporation Enhancement in bonding strength in field emission electron source

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6042442A (en) * 1996-02-28 2000-03-28 Nec Corporation Enhancement in bonding strength in field emission electron source
JP2000036511A (en) * 1998-07-01 2000-02-02 Motorola Inc Manufacture of electronic part

Similar Documents

Publication Publication Date Title
KR930024140A (en) Semiconductor device and manufacturing method
JPH04124843A (en) Semiconductor circuit device
JPH01313979A (en) Apparatus for avoiding piezoelectric effect created in electric elic element in semiconductor material and its forming
JPS6227544B2 (en)
JP2000031308A (en) Semiconductor component and method for coupling semiconductor element
JP3295987B2 (en) Method for manufacturing semiconductor device
JPH0442937Y2 (en)
JPH0442938Y2 (en)
JPS6334281Y2 (en)
JPH0631723Y2 (en) Semiconductor device
JPS6130286Y2 (en)
JP2542227B2 (en) Hybrid IC board device
JPH023954A (en) Integrated circuit device
JPH04116965A (en) Thin film semiconductor device
JPS63248155A (en) Semiconductor device
JPH0536893A (en) Hybrid integrated circuit
JPH0519975Y2 (en)
JPH0241863Y2 (en)
JPS6292354A (en) Hybrid ic
JPH0794670A (en) Hybrid integrated circuit device
JPH0687486B2 (en) IC card module
US20020081779A1 (en) Device comprising an electrical circuit carried by a carrier element and method for the manufacture of such a device
JPS61239693A (en) Multilayer interconnection board and making thereof
JPS6077448A (en) Hybrid integrated circuit device
JPS63276250A (en) Semiconductor integrated circuit device