JPH0519975Y2 - - Google Patents
Info
- Publication number
- JPH0519975Y2 JPH0519975Y2 JP1987065646U JP6564687U JPH0519975Y2 JP H0519975 Y2 JPH0519975 Y2 JP H0519975Y2 JP 1987065646 U JP1987065646 U JP 1987065646U JP 6564687 U JP6564687 U JP 6564687U JP H0519975 Y2 JPH0519975 Y2 JP H0519975Y2
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- film conductor
- principal plane
- hole
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 10
- 239000000919 ceramic Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 10
- 239000011521 glass Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 230000004907 flux Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 150000007513 acids Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は、混成集積回路に関し、特にそれに使
用される厚膜回路基板の構造に関するものであ
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a hybrid integrated circuit, and particularly to the structure of a thick film circuit board used therein.
一主平面を接地面とし、この接地面に金属放熱
体を半田付する厚膜混成集積回路においては、第
３図に示すように、接地面の厚膜導体３ともう一
方の主平面上の膜回路を形成する厚膜導体２とを
接続するための誘電体基板１内のスルーホール部
分で厚膜導体２，３はスルーホールの角の部分で
薄くなるために放熱体（図示せず）に厚膜導体３
を半田付けする時に、半田くわれを起し厚膜導体
３がスルーホールの角部で断線し易い。これを防
止するために、従来は接地面のスルーホールの周
囲にガラス膜７を被覆することが行われている。
In a thick film hybrid integrated circuit in which one main plane is a ground plane and a metal heat sink is soldered to this ground plane, as shown in FIG. At the through-hole part in the dielectric substrate 1 for connecting the thick-film conductor 2 forming the membrane circuit, the thick-film conductors 2 and 3 become thinner at the corners of the through-hole, so a heat sink (not shown) is used. Thick film conductor 3
When soldering, the thick film conductor 3 tends to break at the corner of the through hole due to solder cracks. In order to prevent this, conventionally, a glass film 7 is coated around the through hole in the ground plane.
１ スルーホール保護に用いられるガラス膜７の
熱膨張係数が回路基板１に使用されるアルミナ
等のセラミツクの熱膨張係数と異る。そのため
混成集積回路製造工程中でガラス膜７にクラツ
クを生じる。
1. The thermal expansion coefficient of the glass film 7 used to protect the through holes is different from that of the ceramic such as alumina used for the circuit board 1. Therefore, cracks occur in the glass film 7 during the hybrid integrated circuit manufacturing process.
２ ガラスは体質的に酸に弱い。このため、半田
付時に使用するフラツクス中の酸によつてガラ
ス膜７が溶解される場合がある。これを避ける
ためにはフラツクスの種類が限定される。2 Glass is inherently susceptible to acids. Therefore, the glass film 7 may be dissolved by the acid in the flux used during soldering. To avoid this, the types of fluxes are limited.
本考案によれば、誘電体基板と、誘電体基板の
一主平面と他の主平面とを貫通するスルーホール
と、一主平面上の第１の厚膜導体と、他の主面上
の第２の厚膜導体と、第１の厚膜導体及び第２の
厚膜導体を接続しスルーホール内に形成された配
線導体とを有し、第２の厚膜導体上に金属放熱体
が半田付された混成集積回路において、他の主面
上で第２の厚膜導体下にスルーホールを覆つて形
成されたセラミツクス層を有する混成集積回路が
得られる。
According to the present invention, a dielectric substrate, a through hole penetrating one principal plane and the other principal plane of the dielectric substrate, a first thick film conductor on one principal plane, and a first thick film conductor on the other principal plane. It has a second thick film conductor and a wiring conductor that connects the first thick film conductor and the second thick film conductor and is formed in the through hole, and a metal heat sink is provided on the second thick film conductor. In the soldered hybrid integrated circuit, a hybrid integrated circuit is obtained having a ceramic layer formed over the through hole on the other major surface under the second thick film conductor.
本考案につき図面を用いて説明する。 The present invention will be explained using drawings.
第１図は本考案の第１の実施例の断面図であ
る。誘電体（アルミナ）基板１に印刷された厚膜
導体２及び３がスルーホールを通じて接続されて
いる。スルーホール部はアルミナ膜４で覆われ、
その上から厚膜導体５が印刷される。アルミナ膜
４は通常用いられる印刷法で形成し、10〜50μ程
度の厚さとする。 FIG. 1 is a sectional view of a first embodiment of the present invention. Thick film conductors 2 and 3 printed on a dielectric (alumina) substrate 1 are connected through through holes. The through hole part is covered with an alumina film 4,
A thick film conductor 5 is printed over it. The alumina film 4 is formed by a commonly used printing method, and has a thickness of about 10 to 50 μm.
第２図に本考案の第２の実施例を示す。アルミ
ナ膜６の厚さを薄くし、スルーホール部とその周
辺の領域のみにアルミナ膜６を施した例である。 2 shows a second embodiment of the present invention, in which the thickness of the alumina film 6 is reduced and the alumina film 6 is provided only on the through-hole portion and its surrounding area.
第１の実施例及び第２の実施例においては、基
板の下面に設けたアルミナ膜４，６が基板面から
突出することのない構造となつているため、厚膜
導体５に放熱体を半田付する際厚膜導体５と放熱
体との密着性がよく、放熱効果が優れるため、信
頼性の高い混成集積回路が得られる。この点、第
３図に示した従来例では絶縁基体１の裏面がガラ
ス膜７によつて平坦性を失なわれているので、放
熱板との密着性が悪く放熱効果が劣るものであ
る。 In the first and second embodiments, the structure is such that the alumina films 4 and 6 provided on the bottom surface of the substrate do not protrude from the surface of the substrate, so it is not necessary to solder the heat sink to the thick film conductor 5. When attached, the thick film conductor 5 and the heat sink have good adhesion and the heat dissipation effect is excellent, so that a highly reliable hybrid integrated circuit can be obtained. In this regard, in the conventional example shown in FIG. 3, the flatness of the back surface of the insulating substrate 1 is lost due to the glass film 7, so the adhesion to the heat sink is poor and the heat dissipation effect is poor.
〔考案の効果〕 本考案により以下の効果がある。[Effect of idea] The present invention has the following effects.
１ 回路基板とスルーホール部保護膜に同じアル
ミナ等のセラミツクスを用いることにより、混
成集積回路の製造工程中の熱履歴により保護膜
部にクラツクを生じることがない。また、セラ
ミツクスは化学的に安定しているので、半田付
のフラツクスに侵されない。このため半田付中
に半田クワレが発生しないので、製品の歩留、
信頼度が向上する。1. By using the same ceramics such as alumina for the circuit board and the through-hole protective film, cracks will not occur in the protective film due to thermal history during the manufacturing process of the hybrid integrated circuit. Furthermore, since ceramics are chemically stable, they are not attacked by soldering flux. As a result, solder cracks do not occur during soldering, reducing product yield.
Improves reliability.
第１図は本考案の第１の実施例の混成集積回路
の断面図、第２図は本考案の第２の実施例の混成
集積回路の断面図、第３図は従来の混成集積回路
の断面図である。
１……誘電体基板、２，３，５……厚膜導体、
４……アルミナ膜、６……薄いアルミナ膜、７…
…ガラス膜。
FIG. 1 is a cross-sectional view of a hybrid integrated circuit according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a hybrid integrated circuit according to a second embodiment of the present invention, and FIG. 3 is a cross-sectional view of a conventional hybrid integrated circuit. FIG. 1... Dielectric substrate, 2, 3, 5... Thick film conductor,
4...Alumina film, 6...Thin alumina film, 7...
...Glass membrane.
Claims (1)
主平面とを貫通するスルーホールと、前記一主平
面上の第１の厚膜導体と、前記他の主平面上の第
２の厚膜導体と、前記第１の厚膜導体及び前記第
２の厚膜導体を接続し前記スルーホール内に形成
された配線導体とを有し、前記第２の厚膜導体上
に金属放熱体が半田付された混成集積回路におい
て、前記他の主平面上で前記第２の厚膜導体下に
前記スルーホールを覆つて形成されたセラミツク
ス層を有することを特徴とする混成集積回路。 a dielectric substrate, a through hole penetrating one principal plane and another principal plane of the dielectric substrate, a first thick film conductor on the one principal plane, and a second thick film conductor on the other principal plane. a thick film conductor; a wiring conductor connecting the first thick film conductor and the second thick film conductor and formed in the through hole; and a metal heat sink on the second thick film conductor. 2. A hybrid integrated circuit to which is soldered a ceramic layer, further comprising a ceramic layer formed on the other principal plane under the second thick film conductor and covering the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987065646U JPH0519975Y2 (en) | 1987-04-28 | 1987-04-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987065646U JPH0519975Y2 (en) | 1987-04-28 | 1987-04-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63172173U JPS63172173U (en) | 1988-11-09 |
| JPH0519975Y2 true JPH0519975Y2 (en) | 1993-05-25 |
Family
ID=30902914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987065646U Expired - Lifetime JPH0519975Y2 (en) | 1987-04-28 | 1987-04-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0519975Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5245059A (en) * | 1975-10-07 | 1977-04-08 | Fujitsu Ltd | Method of producing ceramic circuit substrate |
| JPS5384165A (en) * | 1976-12-29 | 1978-07-25 | Mitsumi Electric Co Ltd | Method of producing hyb ic |
-
1987
- 1987-04-28 JP JP1987065646U patent/JPH0519975Y2/ja not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5245059A (en) * | 1975-10-07 | 1977-04-08 | Fujitsu Ltd | Method of producing ceramic circuit substrate |
| JPS5384165A (en) * | 1976-12-29 | 1978-07-25 | Mitsumi Electric Co Ltd | Method of producing hyb ic |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63172173U (en) | 1988-11-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0052920B1 (en) | Electronic circuit interconnection system | |
| JPH08213510A (en) | Semiconductor chip package with intensified heat conductivity | |
| JP2003502852A (en) | Configuration for mounting chips on multilayer printed circuit boards | |
| US5109601A (en) | Method of marking a thin film package | |
| JP3016910B2 (en) | Semiconductor module structure | |
| JPS59126665A (en) | Thick film hybrid integrated circuit | |
| JPH0519975Y2 (en) | ||
| US4965700A (en) | Thin film package for mixed bonding of chips | |
| JP2636602B2 (en) | Semiconductor device | |
| JPS6359535B2 (en) | ||
| JPS5847713Y2 (en) | Thin film hybrid circuit for thermal recording head | |
| JPH0636592Y2 (en) | Hybrid integrated circuit device | |
| JPH0735413Y2 (en) | Mounting structure for chip electronic components in hybrid integrated circuits | |
| JPH0636601Y2 (en) | Circuit board | |
| JPH0423322Y2 (en) | ||
| JPH0729660Y2 (en) | Circuit device | |
| JPH05211378A (en) | Semiconductor device | |
| JPS61245555A (en) | Terminal connecting structure for semiconductor | |
| JPH10163002A (en) | Chip electronic component and its manufacture | |
| JPH11111737A (en) | Semiconductor device | |
| JP2863358B2 (en) | Ceramic multilayer substrate | |
| JPH0231794Y2 (en) | ||
| JPS6141238Y2 (en) | ||
| JPH065731A (en) | Ceramic package and semiconductor device | |
| JPS59124789A (en) | Hybrid integrated circuit unit |