JPS63172173U - - Google Patents
Info
- Publication number
- JPS63172173U JPS63172173U JP6564687U JP6564687U JPS63172173U JP S63172173 U JPS63172173 U JP S63172173U JP 6564687 U JP6564687 U JP 6564687U JP 6564687 U JP6564687 U JP 6564687U JP S63172173 U JPS63172173 U JP S63172173U
- Authority
- JP
- Japan
- Prior art keywords
- hole
- dielectric substrate
- principal plane
- wiring conductor
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
第１図は本考案の第１の実施例の混成集積回路
の断面図、第２図は本考案の第２の実施例の混成
集積回路の断面図、第３図は従来の混成集積回路
の断面図である。
１……誘電体基板、２，３，５……厚膜導体、
４……アルミナ膜、６……薄いアルミナ膜、７…
…ガラス膜。
FIG. 1 is a cross-sectional view of a hybrid integrated circuit according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a hybrid integrated circuit according to a second embodiment of the present invention, and FIG. 3 is a cross-sectional view of a conventional hybrid integrated circuit. FIG. 1... Dielectric substrate, 2, 3, 5... Thick film conductor,
4...Alumina film, 6...Thin alumina film, 7...
...Glass membrane.
Claims (1)
主平面とを電気的に接続するために前記誘電体基
板に設けられたスルーホールと、前記一主平面側
より前記スルーホール内に延在して設けられた配
線導体と、前記スルーホール及び前記スルーホー
ル近傍の前記配線導体を覆つて設けられたセラミ
ツクス層とを有することを特徴とする混成集積回
路。 A dielectric substrate, a through hole provided in the dielectric substrate for electrically connecting one principal plane and another principal plane of the dielectric substrate, and a through hole formed in the through hole from the one principal plane side. 1. A hybrid integrated circuit comprising an extending wiring conductor, and a ceramic layer provided to cover the through hole and the wiring conductor in the vicinity of the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987065646U JPH0519975Y2 (en) | 1987-04-28 | 1987-04-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987065646U JPH0519975Y2 (en) | 1987-04-28 | 1987-04-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63172173U true JPS63172173U (en) | 1988-11-09 |
| JPH0519975Y2 JPH0519975Y2 (en) | 1993-05-25 |
Family
ID=30902914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987065646U Expired - Lifetime JPH0519975Y2 (en) | 1987-04-28 | 1987-04-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0519975Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5245059A (en) * | 1975-10-07 | 1977-04-08 | Fujitsu Ltd | Method of producing ceramic circuit substrate |
| JPS5384165A (en) * | 1976-12-29 | 1978-07-25 | Mitsumi Electric Co Ltd | Method of producing hyb ic |
-
1987
- 1987-04-28 JP JP1987065646U patent/JPH0519975Y2/ja not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5245059A (en) * | 1975-10-07 | 1977-04-08 | Fujitsu Ltd | Method of producing ceramic circuit substrate |
| JPS5384165A (en) * | 1976-12-29 | 1978-07-25 | Mitsumi Electric Co Ltd | Method of producing hyb ic |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0519975Y2 (en) | 1993-05-25 |