JPS6141238Y2 - - Google Patents
Info
- Publication number
- JPS6141238Y2 JPS6141238Y2 JP1981169488U JP16948881U JPS6141238Y2 JP S6141238 Y2 JPS6141238 Y2 JP S6141238Y2 JP 1981169488 U JP1981169488 U JP 1981169488U JP 16948881 U JP16948881 U JP 16948881U JP S6141238 Y2 JPS6141238 Y2 JP S6141238Y2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- wiring board
- wiring layer
- circuit chip
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 5
- 238000001816 cooling Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- -1 For example Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
【考案の詳細な説明】
〔考案の利用分野〕
本考案は集積回路を搭載する配線基板の構造に
係り、特に集積回路が発生する熱を効果的に取り
去るモジユールの構造に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to the structure of a wiring board on which an integrated circuit is mounted, and particularly to the structure of a module that effectively removes heat generated by the integrated circuit.
第１図は従来の集積回路モジユールのチツプ接
続部分に構造の１例を示している。第１図におい
て集積回路チツプ１は電極２を介して多層配線基
板３に接続される。多層配線基板３には通常セラ
ミツク材料が用いられる。集積回路チツプ１内で
発生した熱は電極２、配線基板３を経由してヒー
トシンク４に伝えられるが、集積回路チツプ間を
接続する配線の量が多くなるに従い配線基板３を
厚くする必要があり、冷却性能が悪くなる欠点が
ある。これは、例えば、アイイーイーイー トラ
ンザクシヨン オン コンポーネンツ、ハイブリ
ツズ アンド マニユフアクチアリング テクノ
ロジー、シーエイチエムテー３巻１号、1980年３
月、89〜93頁（IEEE，trans.on components，
hybrids，and manufacturing technology，Vol
CHMT−３ No.１，March 1980，pp89〜93）に
記載がある。
FIG. 1 shows an example of a structure at a chip connection portion of a conventional integrated circuit module. In FIG. 1, an integrated circuit chip 1 is connected to a multilayer wiring board 3 via electrodes 2. As shown in FIG. The multilayer wiring board 3 is usually made of ceramic material. Heat generated within the integrated circuit chip 1 is transmitted to the heat sink 4 via the electrodes 2 and the wiring board 3, but as the amount of wiring connecting between the integrated circuit chips increases, the thickness of the wiring board 3 must be increased. , which has the disadvantage of poor cooling performance. This can be seen, for example, in IEE Transactions on Components, Hybrids and Manufacture Technology, CHP Vol. 3, No. 1, 1980.
May, pp. 89-93 (IEEE, trans.on components,
hybrids, and manufacturing technology, Vol.
CHMT-3 No. 1, March 1980, pp. 89-93).
第２図は従来の集積回路モジユールのチツプ接
続部分の構造の他の例を示す。この方式において
は熱伝導率の高い支持基板２２上に形成された高
分子材料やガラス等を絶縁材料とする薄膜多層配
線基板２１に集積回路チツプ１を接続する。薄膜
配線基板２１は配線パタンの微細化が可能であ
り、第１図の配線基板３に比較して薄くすること
が可能である反面、高分子材料やガラスは一般に
熱伝導率が低く、この方式も第１図の方式と同様
冷却性能が低いという欠点がある。 FIG. 2 shows another example of the structure of the chip connection portion of a conventional integrated circuit module. In this method, the integrated circuit chip 1 is connected to a thin film multilayer wiring board 21 formed on a support substrate 22 having high thermal conductivity and made of an insulating material such as a polymeric material or glass. The thin film wiring board 21 allows for miniaturization of the wiring pattern and can be made thinner than the wiring board 3 in FIG. 1. However, polymer materials and glass generally have low thermal conductivity, and this method Similar to the method shown in FIG. 1, this method also has the disadvantage of low cooling performance.
かかる点に鑑み本考案は、集積回路チツプ間の
接続のための多量の配線を収容するとともに集積
回路チツプ内で発生した熱を効果的に外部に伝え
ることのできる集積回路モジユールを提供するこ
とを目的とする。
In view of this, the present invention aims to provide an integrated circuit module that can accommodate a large amount of wiring for connection between integrated circuit chips and can effectively transfer heat generated within the integrated circuit chips to the outside. purpose.
上記の目的を達成するために、本考案は、集積
回路チツプで発生した熱を多層配線基板を介さず
に外部に伝えるよう、多層配線基板に設けた開口
部内に集積回路チツプを配置することを特徴とす
る。
In order to achieve the above object, the present invention proposes a method for arranging an integrated circuit chip within an opening provided in a multilayer wiring board so that the heat generated by the integrated circuit chip is transferred to the outside without going through the multilayer wiring board. Features.
以下、本考案を実施例を用いて詳細に説明す
る。第３図は本考案の一実施例の構成を示す図で
ある。図において、３３は熱伝導率の高い支持基
板であり、図からわかるように配線が内部に設け
られていない。支持基板表面にSiO2を絶縁層と
する配線層３２を設け、さらにその上にポリイミ
ド等の高分子材料を絶縁材料とする薄膜多層配線
基板３１が形成されている。配線基板３１には、
所定箇所に開口部５が形成されており、この開口
部５内に集積回路チツプ１が配置される。集積回
路チツプ１は電極２を介して配線層３２に接続さ
れ、さらに多量の配線を収容することのできる薄
膜多層配線基板３１に接続される。配線層３２は
電極２と多層配線基板３１を接続するのみに使わ
れるため、多くの配線層を必要とせず、薄くてよ
い。この構成によつて、集積回路チツプ１で発生
した熱は電極２、配線層３２、支持基板３３を経
由してヒートシンク４に伝えられる。配線層３２
の絶縁材料であるSiO2は熱伝導率が低いが薄く
てよいため大きな熱抵抗とはならず、全体として
高い冷却性能が得られる。
Hereinafter, the present invention will be explained in detail using examples. FIG. 3 is a diagram showing the configuration of an embodiment of the present invention. In the figure, 33 is a support substrate with high thermal conductivity, and as can be seen from the figure, no wiring is provided inside. A wiring layer 32 made of SiO 2 as an insulating layer is provided on the surface of the support substrate, and a thin film multilayer wiring board 31 made of a polymeric material such as polyimide as an insulating material is further formed thereon. The wiring board 31 includes
An opening 5 is formed at a predetermined location, and an integrated circuit chip 1 is placed within this opening 5. The integrated circuit chip 1 is connected to a wiring layer 32 via an electrode 2, and is further connected to a thin film multilayer wiring board 31 capable of accommodating a large amount of wiring. Since the wiring layer 32 is used only to connect the electrode 2 and the multilayer wiring board 31, it does not require many wiring layers and can be thin. With this configuration, heat generated in the integrated circuit chip 1 is transmitted to the heat sink 4 via the electrodes 2, the wiring layer 32, and the support substrate 33. Wiring layer 32
SiO 2 , which is the insulating material of the device, has low thermal conductivity, but since it can be made thin, it does not have a large thermal resistance, and overall high cooling performance can be obtained.
なお配線層３２にはSiO2以外の絶縁材料、た
とえばアルミナセラミツクを用いてもよい。また
多層配線基板３１はポリイミド以外の絶縁材料、
たとえばガラスセラミツクを用いてもよい。また
ヒートシンク４を設けるかわりに水その他の液体
を使つて支持基板３３を冷却する方式をとつても
よい。 Note that the wiring layer 32 may be made of an insulating material other than SiO 2 , such as alumina ceramic. In addition, the multilayer wiring board 31 is made of an insulating material other than polyimide,
For example, glass ceramic may be used. Further, instead of providing the heat sink 4, a method may be adopted in which the support substrate 33 is cooled using water or other liquid.
以上述べたごとく本考案によれば、集積回路チ
ツプで発生した熱を多層配線基板を介さずに外部
に伝えるため、高い冷却性能が得られるととも
に、集積回路チツプ間接続のため、多量の配線を
設けることが可能である。
As described above, according to the present invention, the heat generated in the integrated circuit chips is transferred to the outside without going through the multilayer wiring board, so high cooling performance can be obtained, and a large amount of wiring is required to connect the integrated circuit chips. It is possible to provide
第１図および第２図はそれぞれ従来の集積回路
モジユールの一例を示す図、第３図は本考案の一
実施例の構成を示す図である。
FIGS. 1 and 2 each show an example of a conventional integrated circuit module, and FIG. 3 shows the configuration of an embodiment of the present invention.
Claims (1)
けられた配線層と、該配線層上に設けられ、所定
箇所に開口を有する多層配線基板と、該開口内に
配置された集積回路チツプとを具備し、該集積回
路チツプを、該配線層を介して該多層配線基板に
電気的に接続したことを特徴とする集積回路モジ
ユール。 A support substrate with high thermal conductivity, a wiring layer provided on the support substrate, a multilayer wiring board provided on the wiring layer and having an opening at a predetermined location, and an integrated circuit chip placed in the opening. An integrated circuit module comprising: the integrated circuit chip electrically connected to the multilayer wiring board via the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981169488U JPS5874346U (en) | 1981-11-16 | 1981-11-16 | integrated circuit module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981169488U JPS5874346U (en) | 1981-11-16 | 1981-11-16 | integrated circuit module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5874346U JPS5874346U (en) | 1983-05-19 |
| JPS6141238Y2 true JPS6141238Y2 (en) | 1986-11-25 |
Family
ID=29961476
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1981169488U Granted JPS5874346U (en) | 1981-11-16 | 1981-11-16 | integrated circuit module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5874346U (en) |
-
1981
- 1981-11-16 JP JP1981169488U patent/JPS5874346U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5874346U (en) | 1983-05-19 |
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