JPS5936916Y2 - High frequency hybrid integrated circuit board - Google Patents

High frequency hybrid integrated circuit board

Info

Publication number
JPS5936916Y2
JPS5936916Y2 JP3586880U JP3586880U JPS5936916Y2 JP S5936916 Y2 JPS5936916 Y2 JP S5936916Y2 JP 3586880 U JP3586880 U JP 3586880U JP 3586880 U JP3586880 U JP 3586880U JP S5936916 Y2 JPS5936916 Y2 JP S5936916Y2
Authority
JP
Japan
Prior art keywords
hybrid integrated
integrated circuit
board
circuit board
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3586880U
Other languages
Japanese (ja)
Other versions
JPS5649147U (en
Inventor
忠 松本
邦夫 森屋
孝明 大崎
晃 出村
Original Assignee
日本電信電話株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電信電話株式会社 filed Critical 日本電信電話株式会社
Priority to JP3586880U priority Critical patent/JPS5936916Y2/en
Publication of JPS5649147U publication Critical patent/JPS5649147U/ja
Application granted granted Critical
Publication of JPS5936916Y2 publication Critical patent/JPS5936916Y2/en
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 本考案はトラスジスタチップをケースなしで使用する高
周波回路用の混成集積回路基板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit board for high frequency circuits that uses a transistor chip without a case.

従来、混成集積回路に使用されているトラスジスタチッ
プは高い信頼度が要求される場合にセラミックまたは金
属のケース、民生品の場合に樹脂ケース等を用いて外気
よりトランジスタチップを保護している。
Conventionally, transistor chips used in hybrid integrated circuits have been protected from the outside air by using a ceramic or metal case when high reliability is required, and a resin case for consumer products.

第1図および第2図に示すようにこのケースCのために
トランジスタチップは形状が大きくなり、使用周波数が
高くなってくると寄生素子の影響で特性が劣化する。
As shown in FIGS. 1 and 2, due to this case C, the size of the transistor chip becomes large, and as the operating frequency increases, the characteristics deteriorate due to the influence of parasitic elements.

またトランジスタチップの消費電力が大きい場合には、
熱放散を図るためケースに放熱用スタッドeやヒートシ
ンクfを設けるなど放熱上の工夫を必要とし、これが更
にケースbの形状を大きくしている。
Also, if the power consumption of the transistor chip is large,
In order to dissipate heat, it is necessary to take measures for heat dissipation, such as providing a heat dissipation stud e and a heat sink f in the case, which further increases the size of the case b.

この高周波化と熱放散を考慮して近年の混成集積回路は
熱伝導率の良いアルミナやベリリヤを基板として用い、
これらの基板にトランジスタチップを直接搭載する構成
が試みられているが、トランジスタチップを保護するた
めに、樹脂をコーティングするかまたは基板全体をケー
スに封止している。
In consideration of this higher frequency and heat dissipation, recent hybrid integrated circuits use alumina or beryllia as substrates, which have good thermal conductivity.
Attempts have been made to directly mount transistor chips on these substrates, but in order to protect the transistor chips, they are coated with resin or the entire substrate is sealed in a case.

前者は信頼度の点で問題があり、後者では回路の調整を
行なう場合に難点があった。
The former had problems in terms of reliability, and the latter had difficulties in making adjustments to the circuit.

また、高周波用の多層基板ではその基板面上の配線はス
トリップライン構造である。
Further, in a multilayer board for high frequency, the wiring on the board surface has a stripline structure.

このライン幅はフォト・エツチング等の製造条件と直列
抵抗を小さくするという条件から、その下限が定められ
る。
The lower limit of this line width is determined by manufacturing conditions such as photo-etching and the condition of reducing series resistance.

従って、高周波化を考慮すると多層基板の厚さにも下限
が定められ、多層基板上にトランジスタを直接搭載して
も熱放散の点で難があった。
Therefore, in consideration of higher frequencies, a lower limit is set for the thickness of the multilayer substrate, and even if transistors are directly mounted on the multilayer substrate, there is a problem in terms of heat dissipation.

本考案はこれらの欠点を解決するため、トランジスタチ
ップをアルミナまたはべりリアからなる多層縁線基板の
凹部に収納して封止用けたをがぶせて封止し、かつ、封
止後の基板厚みが一様になるようにしたことを特徴とし
、その目的はトランジスタチップを保護すると回持に寄
生素子を少なくして高周波化を図り、かつ熱放散を容易
にし、回路の特性調整も従来通り行いうる混成集積回路
基板を提供することにある。
In order to solve these drawbacks, the present invention has been developed by housing a transistor chip in a recess in a multilayer edge line board made of alumina or Berria, sealing it by covering it with a sealing girder, and reducing the thickness of the board after sealing. Its purpose is to protect the transistor chip, reduce the number of parasitic elements in the circulation, increase the frequency, facilitate heat dissipation, and adjust the circuit characteristics as usual. It is an object of the present invention to provide a hybrid integrated circuit board that can be used.

第3図は本考案による混成集積回路基板の断面図、第4
図は平面図である。
Figure 3 is a cross-sectional view of the hybrid integrated circuit board according to the present invention;
The figure is a plan view.

1はアルミナまたはべりリアの多層基板、2はトランジ
スタチップ、3はトランジスタコレクタ用導体バタン、
4は封じ用メタライズ部、5は封じ用ふた9のメタライ
ジ部、6および6′は基板表面との導通をとるためのス
ルーホール、7は基板表裏を導通するためのスルーホー
ル、8は回路の導体バタンをそれぞれ示す。
1 is an alumina or berria multilayer substrate, 2 is a transistor chip, 3 is a conductor button for a transistor collector,
4 is a metallized part for sealing, 5 is a metallized part of the sealing lid 9, 6 and 6' are through holes for establishing electrical conduction with the surface of the board, 7 are through holes for electrical conduction between the front and back sides of the board, and 8 is a through hole for the circuit. Each conductor button is shown.

第5図はべりリア基板の温度分布を示したものである。FIG. 5 shows the temperature distribution of the Berria substrate.

基板の大きさは50 X 50 mm、厚さ1.0mm
で基板中心に1.5 Wattの発熱体を置いた場合の
実測値である。
The size of the board is 50 x 50 mm, thickness 1.0 mm
This is an actual value when a 1.5 Watt heating element is placed at the center of the board.

横軸に発熱体中心からの距離を、縦軸に温度を示す。The horizontal axis shows the distance from the center of the heating element, and the vertical axis shows the temperature.

中止から基板の端迄の温度勾配は小さく、極めて熱伝達
の良いことが分かる。
It can be seen that the temperature gradient from the stop to the edge of the substrate is small, indicating extremely good heat transfer.

以下図にしたがって説明する。This will be explained below with reference to the figures.

第3図に示すようにトランジスタチップ2は基板1の表
面から2層の基板を除去して設けた中央部にある凹部1
0の底に直接ボンティングされるため、トランジスタの
熱放散が底面の基板を介して効率よくなされ、第5図に
示すように極めて良くトランジスタジャンクション温度
を小さく抑えることかで゛きる。
As shown in FIG. 3, the transistor chip 2 has a recess 1 in the center, which is formed by removing two layers of the substrate from the surface of the substrate 1.
Since the transistor is bonded directly to the bottom of the transistor, heat dissipation of the transistor is efficiently carried out through the bottom substrate, and as shown in FIG. 5, the transistor junction temperature can be kept extremely low.

またトランジスタチップ2は凹部10の中に、基板メタ
ライズ4と封じ用ふた9のメタライズ5とを金属ロウに
よって接着して封じられる。
Further, the transistor chip 2 is sealed in the recess 10 by bonding the substrate metallization 4 and the metallization 5 of the sealing lid 9 with metal solder.

第3図のような横紐とすることにより封じ用ふた9取付
は後の混成集積回路基板厚みは一様になり例えばタンタ
ル薄膜で混成集積回路を基板上に製造する際にエツチン
ク;等の製造工程が容易となる。
By using the horizontal strap as shown in Fig. 3, the thickness of the hybrid integrated circuit board after attaching the sealing lid 9 becomes uniform, making it convenient for etching, etc., when manufacturing a hybrid integrated circuit on a board using a tantalum thin film, for example. The process becomes easier.

トランジスタチップ2の電極引出しは四部の電極ランド
(導体パタン3)からスルーホール6を通り、必要な場
合は第4図のように導体パタン8で他のランドに接続す
ることができる。
The electrodes of the transistor chip 2 are drawn out from the four electrode lands (conductor patterns 3) through through holes 6, and can be connected to other lands by conductor patterns 8 as shown in FIG. 4, if necessary.

従って、トランジスタチップを使用しながらこのように
トランジスタ部のみを封じることが出来るため、従来と
全く同様な回路の調整を、トランジスタの信頼度を劣化
させずに行うことができる。
Therefore, since it is possible to seal only the transistor portion in this way while using a transistor chip, the circuit can be adjusted in exactly the same way as in the conventional circuit without deteriorating the reliability of the transistor.

またトランジスタチップを使用するので信号ループが短
くなり高周波化に適している。
Also, since a transistor chip is used, the signal loop is shortened, making it suitable for higher frequencies.

以上の説明から分かるように、消費電力の大きいトラン
ジスタチップを必要とし、かつトランジスタの高信頼度
を要する高周波回路用基板として有効である。
As can be seen from the above description, the present invention is effective as a substrate for a high frequency circuit that requires a transistor chip with large power consumption and requires high reliability of the transistor.

特に信号帰還ループを出来るだけ短くしたいFDM (
周波数分割多重)方式や高周波PCM(パルス符号変調
)方式用混成集積回路に対してその効果は顕著である。
Especially for FDM where you want to keep the signal feedback loop as short as possible (
This effect is remarkable for hybrid integrated circuits for frequency division multiplexing (frequency division multiplexing) and high frequency PCM (pulse code modulation) systems.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の混成集積回路用基板の断面図、第2図は
その平面図、第3図は本考案になる基板の断面図、第4
図はその平面図、第5図は本基板の温度分布図である。 符号の説明、1・・・・・・セラミック基板、2・・・
・・・トランジスタチップ、3・・・・・・導体パタン
、9・・・・・・封じ用ふた、10・・・・・・凹部。
Fig. 1 is a sectional view of a conventional hybrid integrated circuit board, Fig. 2 is a plan view thereof, Fig. 3 is a sectional view of a board according to the present invention, and Fig. 4 is a sectional view of a conventional board for hybrid integrated circuits.
The figure is a plan view thereof, and FIG. 5 is a temperature distribution diagram of this substrate. Explanation of symbols, 1... Ceramic substrate, 2...
...Transistor chip, 3...Conductor pattern, 9...Sealing lid, 10...Recessed portion.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 導体パタンを層間に有する多層構成の高周波用混成集積
回路基板において、上記基板の表面から一層以上の層を
除去して設けたトランジスタ収納用凹部を有し、上記凹
部には上記基板と同じ材料でなる封じ用ふたを設け、上
記ふたの厚みは封止後の上記基板の厚みが一様であるよ
うに選ばれてなることを特徴とする高周波用混成集積回
路基板。
A high-frequency hybrid integrated circuit board having a multilayer structure having a conductor pattern between layers, the board having a recess for storing a transistor formed by removing one or more layers from the surface of the board, and the recess being made of the same material as the board. 1. A high-frequency hybrid integrated circuit board, characterized in that a sealing lid is provided, and the thickness of the lid is selected so that the thickness of the substrate after sealing is uniform.
JP3586880U 1980-03-21 1980-03-21 High frequency hybrid integrated circuit board Expired JPS5936916Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3586880U JPS5936916Y2 (en) 1980-03-21 1980-03-21 High frequency hybrid integrated circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3586880U JPS5936916Y2 (en) 1980-03-21 1980-03-21 High frequency hybrid integrated circuit board

Publications (2)

Publication Number Publication Date
JPS5649147U JPS5649147U (en) 1981-05-01
JPS5936916Y2 true JPS5936916Y2 (en) 1984-10-12

Family

ID=29288149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3586880U Expired JPS5936916Y2 (en) 1980-03-21 1980-03-21 High frequency hybrid integrated circuit board

Country Status (1)

Country Link
JP (1) JPS5936916Y2 (en)

Also Published As

Publication number Publication date
JPS5649147U (en) 1981-05-01

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