JP2572645B2 - Heat dissipation structure of semiconductor device - Google Patents

Heat dissipation structure of semiconductor device

Info

Publication number
JP2572645B2
JP2572645B2 JP1090668A JP9066889A JP2572645B2 JP 2572645 B2 JP2572645 B2 JP 2572645B2 JP 1090668 A JP1090668 A JP 1090668A JP 9066889 A JP9066889 A JP 9066889A JP 2572645 B2 JP2572645 B2 JP 2572645B2
Authority
JP
Japan
Prior art keywords
heat dissipation
semiconductor
semiconductor device
semiconductor chip
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1090668A
Other languages
Japanese (ja)
Other versions
JPH02270356A (en
Inventor
一彦 野澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1090668A priority Critical patent/JP2572645B2/en
Publication of JPH02270356A publication Critical patent/JPH02270356A/en
Application granted granted Critical
Publication of JP2572645B2 publication Critical patent/JP2572645B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、フイルムキヤリアタイプ即ちTAB式の半
導体装置の熱放散構造に関するものである。
Description: TECHNICAL FIELD The present invention relates to a heat dissipation structure of a film carrier type, that is, a TAB type semiconductor device.

[従来の技術] 半導体装置は、一般にリードフレームに設けたダイパ
ッドに半導体チップを取り付け、この半導体チップの外
部電極とリードフレームの端子とをそれぞれのワイヤで
接続し、これを例えばエポキシ樹脂のような熱硬化性樹
脂でパッケージしたのち各端子を切断し、製造してい
る。
2. Description of the Related Art In general, a semiconductor device attaches a semiconductor chip to a die pad provided on a lead frame, connects an external electrode of the semiconductor chip to a terminal of the lead frame by respective wires, and connects the external electrode with, for example, an epoxy resin. After packaging with thermosetting resin, each terminal is cut and manufactured.

ところで、最近では電子機器の小形化、薄形化に伴
い、これに使用する半導体装置も高密度実装するため、
厚くかつ比較的大形な従来の半導体装置に代えて、薄く
かつ小形の半導体装置が望まれ、このような要請に応え
るために、キャリアテープ1のデバイスホールに半導体
チップ6を配設し、この半導体チップ6の電極4とキャ
リアテープ1のインナーリード3に設けたバンプとを直
接接続し、これに液状の樹脂(例えばエポキシ樹脂)か
らなる封止剤を印刷あるいはポッティングしてパッケー
ジした半導体装置Dが使用されるようになっている。
By the way, recently, with the miniaturization and thinning of electronic devices, semiconductor devices used for them are also mounted at high density.
A thin and small semiconductor device is desired instead of a thick and relatively large conventional semiconductor device. In order to meet such a demand, a semiconductor chip 6 is provided in a device hole of the carrier tape 1. A semiconductor device D in which the electrodes 4 of the semiconductor chip 6 and the bumps provided on the inner leads 3 of the carrier tape 1 are directly connected, and a sealing agent made of a liquid resin (for example, an epoxy resin) is printed or potted and packaged. Is used.

上記のようにして製造されたTAB式の半導体装置Dは
例えば第4図に示すように、プリント配線基板10上に、
能動面を該プリント配線基板10側に向けて搭載し、イン
ナーリード3とプリント配線基板10の表面に形成した導
電パターン11にそれぞれはんだ付けしたのち、スキージ
印刷やポッテイング等により半導体チップ6の周囲及び
導電パターン11をエポキシ樹脂等の封止剤12で封止す
る。
The TAB type semiconductor device D manufactured as described above is, for example, as shown in FIG.
After mounting the active surface toward the printed wiring board 10 side and soldering the inner lead 3 and the conductive pattern 11 formed on the surface of the printed wiring board 10, respectively, the periphery of the semiconductor chip 6 and the squeegee printing or potting are used. The conductive pattern 11 is sealed with a sealing agent 12 such as an epoxy resin.

このようにプリント配線基板10に実装されたTAB式の
半導体装置Dの放熱は半導体チップ6の能動面とは逆の
外部に露出した面で行っている。
In this way, the heat radiation of the TAB type semiconductor device D mounted on the printed wiring board 10 is performed on the surface exposed to the outside opposite to the active surface of the semiconductor chip 6.

[発明が解決しようとする課題] 上述したプリント配線基板10に実装された半導体装置
Dでは、半導体チップ6が例えばCMOSのSRAMの場合、そ
の駆動周波数が2MHz程度であれば、消費電力は約70mWで
あるので、半導体チップ6自身の発熱を半導体チップ6
の能動面とは逆側の外部に露出した面から放熱させて温
度上昇を抑制することができるが、CMOSのSRAMであって
も、その駆動周波数が10MHzとなると、消費電力は約350
mWとなり、半導体チップ6自身による放熱では不十分で
あった。
[Problem to be Solved by the Invention] In the semiconductor device D mounted on the printed wiring board 10 described above, when the semiconductor chip 6 is, for example, a CMOS SRAM, if the driving frequency is about 2 MHz, the power consumption is about 70 mW. Therefore, the heat generated by the semiconductor chip 6 itself is
Although the temperature rise can be suppressed by radiating heat from the surface exposed to the outside opposite to the active surface of the CMOS, even if it is a CMOS SRAM, if the driving frequency is 10 MHz, the power consumption will be about 350
mW, and the heat radiation by the semiconductor chip 6 itself was insufficient.

また、最近開発された半導体チップ6として、CMOSの
うちでも擬似SRAMはSRAMの約5倍の発熱量があり、更に
NMOSのDRAMの場合にはCMOSのSRAMの10〜20倍の発熱量が
あるため、使用できる半導体チップ6が制限されてしま
うという問題点があった。
In addition, as a recently developed semiconductor chip 6, pseudo-SRAM has approximately five times as much heat generation as SRAM among CMOS.
In the case of an NMOS DRAM, the amount of heat generated is 10 to 20 times that of a CMOS SRAM, so that there is a problem that the semiconductor chip 6 that can be used is limited.

この発明は上記のような課題を解決するためになされ
たもので、消費電力が多く、自己発熱が高い半導体チッ
プでも使用することができる半導体装置の放熱構造を得
ることを目的としている。
The present invention has been made to solve the above-described problems, and has as its object to obtain a heat dissipation structure of a semiconductor device which consumes a large amount of power and can be used even for a semiconductor chip which generates high self-heating.

[課題を解決するための手段] この発明に係る半導体装置の熱放散構造は、導電パタ
ーンが設置された基板、前記基板上に配置され、個々が
半導体チップを有しているN個のTAB式半導体装置、前
記半導体チップの前記基板と対向していない面に塗布さ
れる絶縁性及び熱伝導性良好な接着樹脂と、前記基板上
に配置されるM個(N≠M、N>M)の熱放散媒体を有
する半導体装置の放熱構造であって、前記熱放散媒体の
個々は、隣接する2個の前記TAB式半導体装置に前記接
着樹脂を介して接続され、前記半導体チップの前記熱放
散媒体と対向する面の面積よりも大きな面積を有する面
から構成されているものである。
[Means for Solving the Problems] A heat dissipation structure of a semiconductor device according to the present invention includes a substrate on which a conductive pattern is provided, and N TABs each of which has a semiconductor chip and is disposed on the substrate. A semiconductor device, an adhesive resin having good insulation and thermal conductivity applied to a surface of the semiconductor chip not facing the substrate, and M (N ≠ M, N> M) disposed on the substrate; A heat dissipation structure of a semiconductor device having a heat dissipation medium, wherein each of the heat dissipation media is connected to two adjacent TAB type semiconductor devices via the adhesive resin, and the heat dissipation medium of the semiconductor chip is provided. Is formed from a surface having an area larger than the area of the surface opposed to.

[作用] この発明においては、熱放散媒体の個々は、隣接する
2個のTAB式半導体装置に絶縁性及び熱伝導性良好な接
着樹脂を介して接続され、半導体チップの熱放散媒体と
対向する面の面積よりも大きな面積を有する面から構成
されているから、隣接する2個のTAB式半導体装置の各
半導体チップの自己発熱より発熱した熱は接着樹脂を経
て2つの半導体チップに接続された1つの熱放散媒体に
伝播し、2つの半導体チップより熱放散面積が大きく放
熱効果が良好な1つの熱放散媒体によりそれぞれ周囲の
空間に熱を放熱して半導体チップの温度上昇を抑制す
る。
[Function] In the present invention, each of the heat dissipation media is connected to two adjacent TAB semiconductor devices via an adhesive resin having good insulation and heat conductivity, and faces the heat dissipation media of the semiconductor chip. Since it is composed of a surface having an area larger than the area of the surface, the heat generated from the self-heating of each semiconductor chip of two adjacent TAB type semiconductor devices was connected to the two semiconductor chips via the adhesive resin. The heat is dissipated to one heat dissipation medium, and the heat dissipation medium having a larger heat dissipation area than the two semiconductor chips and a good heat dissipation effect radiates heat to the surrounding spaces, thereby suppressing a temperature rise of the semiconductor chip.

また、基板に実装されたそれぞれの隣接する2個のTA
B式半導体装置の各半導体チップの放熱を1つの熱放散
媒体により分散し、1つの熱放散媒体はそれぞれ共用す
る2つの半導体装置の半導体チップの熱を均一化する。
Also, each two adjacent TAs mounted on the board
The heat dissipation of each semiconductor chip of the B-type semiconductor device is dispersed by one heat dissipation medium, and one heat dissipation medium equalizes the heat of the semiconductor chips of the two semiconductor devices shared respectively.

[実施例] 第1図はこの発明の実施例の断面図である。図におい
て、従来例と同一の構成は同一符号を用いて重複した構
成の説明を省略する。15は絶縁性及び熱伝導性が良好な
例えばシリコン系樹脂等の常温硬化性の接着樹脂で、半
導体チップ6の能動面と逆の外部に露出した面に印刷あ
るいはポッティングで塗布されている。この接着樹脂15
はにより半導体チップ6の能動面と逆の面に熱放散媒体
である2つの金属板16が取り付けられている。
FIG. 1 is a sectional view of an embodiment of the present invention. In the figure, the same components as those of the conventional example are denoted by the same reference numerals, and the description of the duplicated components will be omitted. Reference numeral 15 denotes a room-temperature-curable adhesive resin such as a silicon-based resin having good insulation and thermal conductivity, which is applied by printing or potting to a surface exposed to the outside of the semiconductor chip 6 opposite to the active surface. This adhesive resin 15
On the other hand, two metal plates 16 serving as a heat dissipation medium are mounted on the surface of the semiconductor chip 6 opposite to the active surface.

上記のような構成の半導体装置の放熱構造では、半導
体チップ6の自己発熱による温度上昇が生じると、その
熱は半導体チップ6より熱伝導性が良好な接着樹脂15を
経て各々の金属板16に伝播し、2つの金属板16は半導体
チップ6より熱放散面積が大きく、これら金属板16より
絶縁性及び熱伝導性良好な周囲の空間に放散するため、
放熱効率が上昇した。
In the heat dissipation structure of the semiconductor device having the above-described configuration, when the temperature rise due to the self-heating of the semiconductor chip 6 occurs, the heat is transmitted to each metal plate 16 via the adhesive resin 15 having better thermal conductivity than the semiconductor chip 6. Propagation, the two metal plates 16 have a larger heat dissipation area than the semiconductor chip 6, and dissipate into the surrounding space having better insulation and heat conductivity than these metal plates 16,
Heat dissipation efficiency has increased.

従って、例えば300mW以上の消費電力の半導体チップ
6を有する半導体装置の場合でもその定格温度範囲の温
度を保ち、長期間の連続駆動に耐えて特性の変化が生じ
ることがない。
Therefore, even in the case of a semiconductor device having a semiconductor chip 6 with power consumption of, for example, 300 mW or more, the temperature is maintained within the rated temperature range, and the device does not change its characteristics while enduring long-term continuous driving.

第2図はこの発明の他の実施例の断面図、第3図は同
実施例の半導体装置が実装されたプリント配線基板の平
面図である。
FIG. 2 is a sectional view of another embodiment of the present invention, and FIG. 3 is a plan view of a printed wiring board on which the semiconductor device of the embodiment is mounted.

この実施例では、プリント配線基板10に12個のTAB式
半導体装置Dが実装されている。そして、第3図におい
て各々の左右方向に隣接する2つの半導体装置Dの半導
体チップ6のプリント配線基板10と対向していない面に
2つの半導体チップより表面積が広い1つの金属板6が
またがるように接着樹脂15でそれぞれ取り付けられてい
る。
In this embodiment, twelve TAB semiconductor devices D are mounted on a printed wiring board 10. In FIG. 3, one metal plate 6 having a larger surface area than the two semiconductor chips straddles the surface of the semiconductor chips 6 of the two semiconductor devices D that are adjacent to each other in the left-right direction and does not face the printed wiring board 10. Are respectively attached with adhesive resin 15.

即ち、第3図において、最上部の左側からプリント配
線基板10に実装されている3個のTAB式半導体装置D
を、例えば第1、第2及び第3TAB式半導体装置として説
明すると、第1及び第2のTAB式半導体装置Dの半導体
チップ6に接着樹脂15を介して2つの半導体チップより
表面積が広い第1熱放散媒体である金属板6が接続され
ており、第2及び第3のTAB式半導体装置Dの半導体チ
ップ6に接着樹脂15を介して2つの半導体チップ6より
表面積が広く、且つ第1熱放散媒体である金属板6とは
独立して第2熱放散媒体である金属板6が接続されてい
る。このように、各々の隣接する2つの半導体装置Dは
1つの金属板6を共用し、1つの金属板6は2つの半導
体装置Dの半導体チップ6の熱を放熱する。
That is, in FIG. 3, three TAB semiconductor devices D mounted on the printed wiring board 10 from the upper left side.
For example, as a first, second and third TAB type semiconductor device, the first and second TAB type semiconductor devices D may have a first chip having a larger surface area than the two semiconductor chips via the adhesive resin 15 on the semiconductor chip 6. The metal plate 6 serving as a heat dissipation medium is connected to the semiconductor chip 6 of the second and third TAB type semiconductor devices D via the adhesive resin 15 so as to have a larger surface area than the two semiconductor chips 6 and the first heat sink. The metal plate 6 as the second heat dissipation medium is connected independently of the metal plate 6 as the heat dissipation medium. As described above, two adjacent semiconductor devices D share one metal plate 6, and one metal plate 6 radiates heat of the semiconductor chips 6 of the two semiconductor devices D.

このように第3図に示す実施例は、熱放散媒体である
1つの金属板16が隣接する2個の半導体装置Dの半導体
チップ6にまたがって取り付けられ、1つの金属板16は
2つの半導体チップ6の金属板16と対向する面の面積よ
り表面積が広いために放熱効率の向上が図れると共に高
密度実装が可能となる。
Thus, in the embodiment shown in FIG. 3, one metal plate 16 serving as a heat dissipation medium is attached across the semiconductor chips 6 of two adjacent semiconductor devices D, and one metal plate 16 is composed of two semiconductor chips. Since the surface area is larger than the area of the surface of the chip 6 facing the metal plate 16, the heat radiation efficiency can be improved and high-density mounting is possible.

なお、半導体チップ6を有する複数の半導体装置Dと
金属板16とは、半導体装置Dの個数をN、金属板16の個
数をMとすると、両者の間には次の関係が成立する。
Note that the following relationship is established between the plurality of semiconductor devices D having the semiconductor chip 6 and the metal plate 16, where N is the number of semiconductor devices D and M is the number of metal plates 16.

N≠M,N>M また、実装の際に、熱放散媒体である金属板16の数が
減らされるため、製造の簡易化が図れる。
N ≠ M, N> M Further, at the time of mounting, since the number of the metal plates 16 as the heat dissipation medium is reduced, the production can be simplified.

さらに、プリント配線基板10に対して熱放散媒体であ
る金属板16は最上層に位置するため、熱放散媒体である
金属板16が邪魔することなく容易にTAB式の半導体装置
Dをプリント配線基板10に実装できる。しかも、TAB式
の半導体装置Dのプリント配線基板10への実装時から検
査時までの間、後から熱放散媒体である金属板16の取り
外しが容易に行える。
Further, since the metal plate 16 as the heat dissipation medium is located on the uppermost layer with respect to the printed wiring board 10, the TAB type semiconductor device D can be easily mounted on the printed wiring board without the metal plate 16 as the heat dissipation medium being disturbed. Can be implemented in 10. Moreover, the metal plate 16 as the heat dissipation medium can be easily removed later from the time of mounting the TAB type semiconductor device D on the printed wiring board 10 to the time of inspection.

このように、第3図に示す実施例は各々の隣接する2
つの半導体装置Dは1枚の金属板6を共用し、1つの金
属板16は2つの半導体装置Dの半導体チップ6の熱を分
散して放熱し、しかも各金属板16は金属板16を共用する
半導体装置Dの半導体チップ6の熱を均一化するため、
プリント配線基板10と金属板16との熱膨張率の差により
生じる応力が半導体装置Dに殆どかからなくなるもので
あるため、プリント配線基板に生じる反りを最小限に抑
えることができる。なお、上記第3図に示す実施例では
左右方向に互いに隣接する2つの半導体装置Dの半導体
チップ6に1つの金属板6がまたがるように接着樹脂15
でそれぞれ取り付けられているが、上下方向に互いに隣
接する2つの半導体装置Dの半導体チップ6に1つの金
属板6がまたがるように取り付けられてもよく、各々の
隣接する2つの半導体装置Dが1つの金属板6を共用す
るものであればよい。
Thus, the embodiment shown in FIG.
One semiconductor device D shares one metal plate 6, one metal plate 16 disperses and dissipates the heat of the semiconductor chips 6 of the two semiconductor devices D, and furthermore, each metal plate 16 shares the metal plate 16. In order to make the heat of the semiconductor chip 6 of the semiconductor device D uniform,
Since the stress generated by the difference in the coefficient of thermal expansion between the printed wiring board 10 and the metal plate 16 is hardly applied to the semiconductor device D, the warpage generated in the printed wiring board can be minimized. In the embodiment shown in FIG. 3, the adhesive resin 15 is arranged so that one metal plate 6 extends over the semiconductor chips 6 of two semiconductor devices D adjacent to each other in the left-right direction.
Each of the two semiconductor devices D may be attached so that one metal plate 6 straddles the semiconductor chips 6 of two semiconductor devices D adjacent to each other in the vertical direction. What is necessary is just to share the two metal plates 6.

[発明の効果] 以上のように、この発明によれば、熱放散媒体の個々
は、隣接する2個のTAB式半導体装置に絶縁性及び熱伝
導性が良好な接着樹脂を介して接続され、半導体チップ
の熱放散媒体と対向する面の面積よりも大きな面積を有
する面から構成されているので、隣接する2個のTAB式
半導体装置の各半導体チップの自己発熱より発熱した熱
は接着樹脂を経て2つの半導体チップに接続された1つ
の熱放散媒体に伝播し、2つの半導体チップより熱放散
面積が大きく放熱効果が良好な1つの熱放散媒体よりそ
れぞれ周囲の空間に熱を放熱させるため放熱効率が向上
し、自己発熱が高い半導体チップでも使用することがで
き、基板に対して熱放散媒体は最上層に位置するために
熱放散媒体が邪魔することなく容易に半導体装置を基板
に実装できるという効果を有する。
[Effects of the Invention] As described above, according to the present invention, each of the heat dissipation media is connected to two adjacent TAB type semiconductor devices via an adhesive resin having good insulation and heat conductivity, Since the semiconductor chip is composed of a surface having an area larger than the area of the surface facing the heat dissipation medium of the semiconductor chip, the heat generated by the self-heating of each semiconductor chip of the two adjacent TAB type semiconductor devices removes the adhesive resin. Then, the heat is transmitted to one heat dissipation medium connected to the two semiconductor chips, and the heat is dissipated to the surrounding space from one heat dissipation medium having a larger heat dissipation area than the two semiconductor chips and a good heat dissipation effect. Efficiency is improved and semiconductor chips with high self-heating can be used.Since the heat dissipation medium is located on the top layer with respect to the board, the semiconductor device can be easily mounted on the board without disturbing the heat dissipation medium. It has the effect of cutting.

また、基板に実装されたそれぞれ隣接する2個のTAB
式半導体装置の各半導体チップの放熱を1つの熱放散媒
体により分散し、1つの熱放散媒体はそれぞれ共用する
2つの半導体装置の半導体チップの熱を均一化するの
で、基板と熱放散媒体との熱膨張率の差により生じる応
力が半導体装置に殆どかからなくなるため、基板に生じ
る反りを最小限に抑えることができるという効果を有す
る。
Also, two adjacent TABs mounted on the board
The heat radiation of each semiconductor chip of the semiconductor device is dispersed by one heat dissipating medium, and one heat dissipating medium equalizes the heat of the semiconductor chips of the two shared semiconductor devices. Since the stress generated by the difference in the coefficient of thermal expansion is hardly applied to the semiconductor device, there is an effect that the warpage generated in the substrate can be minimized.

【図面の簡単な説明】[Brief description of the drawings]

第1図はこの発明の実施例の断面図、第2図はこの発明
の他の実施例の断面図、第3図は同実施例の半導体装置
が実装されたプリント基板の平面図、第4図は従来の半
導体装置の放熱構造を示す断面図である。 1……キャリアテープ、3……インナーリード、6……
半導体チップ、10はプリント配線基板、11は導電パター
ン、12……封止剤、15……接着樹脂、16……金属板(熱
放散媒体)。
1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of another embodiment of the present invention, FIG. 3 is a plan view of a printed circuit board on which the semiconductor device of the embodiment is mounted, and FIG. FIG. 1 is a sectional view showing a heat dissipation structure of a conventional semiconductor device. 1 ... Carrier tape, 3 ... Inner lead, 6 ...
Semiconductor chip, 10 is a printed wiring board, 11 is a conductive pattern, 12 is a sealant, 15 is an adhesive resin, 16 is a metal plate (heat dissipating medium).

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】導電パターンが設置された基板、 前記基板上に配置され、個々が半導体チップを有してい
るN個のTAB式半導体装置、 前記半導体チップの前記基板と対向していない面に塗布
される絶縁性及び熱伝導性良好な接着樹脂と、 前記基板上に配置されるM個(N≠M、N>M)の熱放
散媒体、 を有する半導体装置の熱放散構造であって、 前記熱放散媒体の個々は、隣接する2個の前記TAB式半
導体装置に前記接着樹脂を介して接続され、前記半導体
チップの前記熱放散媒体と対向する面の面積よりも大き
な面積を有する面から構成されることを特徴とする半導
体装置の熱放散構造。
A substrate provided with a conductive pattern; N TAB semiconductor devices each having a semiconductor chip disposed on the substrate; and a surface of the semiconductor chip not facing the substrate. A heat dissipation structure for a semiconductor device, comprising: an adhesive resin having good insulation and heat conductivity to be applied; and M (N ≠ M, N> M) heat dissipation media disposed on the substrate, Each of the heat dissipation media is connected to two adjacent TAB type semiconductor devices via the adhesive resin, and has a larger area than a surface of the semiconductor chip facing the heat dissipation medium. A heat dissipation structure for a semiconductor device, comprising:
JP1090668A 1989-04-12 1989-04-12 Heat dissipation structure of semiconductor device Expired - Fee Related JP2572645B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1090668A JP2572645B2 (en) 1989-04-12 1989-04-12 Heat dissipation structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1090668A JP2572645B2 (en) 1989-04-12 1989-04-12 Heat dissipation structure of semiconductor device

Publications (2)

Publication Number Publication Date
JPH02270356A JPH02270356A (en) 1990-11-05
JP2572645B2 true JP2572645B2 (en) 1997-01-16

Family

ID=14004918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1090668A Expired - Fee Related JP2572645B2 (en) 1989-04-12 1989-04-12 Heat dissipation structure of semiconductor device

Country Status (1)

Country Link
JP (1) JP2572645B2 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5553433A (en) * 1978-10-16 1980-04-18 Hitachi Ltd Manufacture of semiconductor device
JPS57162452A (en) * 1981-03-31 1982-10-06 Toshiba Corp Semiconductor device
JPS5897848U (en) * 1981-12-24 1983-07-02 セイコーエプソン株式会社 Outer lead bonding structure

Also Published As

Publication number Publication date
JPH02270356A (en) 1990-11-05

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