JPS58140143A - Composite type semiconductor device - Google Patents

Composite type semiconductor device

Info

Publication number
JPS58140143A
JPS58140143A JP2255682A JP2255682A JPS58140143A JP S58140143 A JPS58140143 A JP S58140143A JP 2255682 A JP2255682 A JP 2255682A JP 2255682 A JP2255682 A JP 2255682A JP S58140143 A JPS58140143 A JP S58140143A
Authority
JP
Japan
Prior art keywords
thin plate
semiconductor thin
conductive path
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2255682A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP2255682A priority Critical patent/JPS58140143A/en
Publication of JPS58140143A publication Critical patent/JPS58140143A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To contrive the super high density and enhance the mechanical strength, by solidly constituting a plurality of semiconductor substrates whereon a various kind of elements are formed. CONSTITUTION:The first semiconductor substrate 1 and the second semiconductor substrate 11 are so arranged that the main surfaces thereof become internal surfaces each other. The conduction guide 14 of the substrate 11 is connected to the conduction guide 4 of the substrate 1 corresponded thereto via a conductive ball 6 and soldering 7. Thereby, the both surfaces of the substrate 11 are used, and accordingly many circuit elements can be provided within a fixed space.

Description

【発明の詳細な説明】 本発明は複合した半導体集積回路装置に関し、これを立
体的に構成して超高密度化を図ろうとするものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a composite semiconductor integrated circuit device, and is intended to achieve ultra-high density by three-dimensionally configuring the device.

一つの半導体基板上に各種の素子を形成し、これらを基
板表面に印刷的に形成した導電路により回路を構成した
半導体集積回路(いわゆるIO)は電子回路装置の高密
度化を計る意図の下に開発されたものであるが、回路が
複雑化し、また、抵抗、容量等のごとき占有面積の比較
的大なるものを半導体基板上に設ける場合、どうしても
回路全体が大きくならざるを得ない。半導体基板は製造
技術の関係からその大きさに限りがあり、大きな回路を
作ろうとすれば、集積回路装置自体を複合化しなければ
ならない。
Semiconductor integrated circuits (so-called IO), in which various elements are formed on a single semiconductor substrate and circuits are constructed from conductive paths printed on the surface of the substrate, are developed with the intention of increasing the density of electronic circuit devices. However, the circuit becomes complicated, and when resistors, capacitors, etc. that occupy a relatively large area are provided on a semiconductor substrate, the entire circuit inevitably becomes larger. Semiconductor substrates are limited in size due to manufacturing technology, and if a large circuit is to be made, the integrated circuit device itself must be made into a composite device.

従来の集積回路装置の多くは素子を形成した主面の対向
主面をセラミック等のごとき強固な絶縁体支持板上に固
着せしめる構造となっているため複合化する場合、平面
的に横に拡がることになり、また、前記の対向主面を回
路として利用することができない。
Most conventional integrated circuit devices have a structure in which the main surface opposite the main surface on which the element is formed is fixed on a strong insulating support plate such as ceramic, so when compounded, it spreads horizontally in a plane. Therefore, the opposing principal surfaces cannot be used as a circuit.

本発明の目的は上述した欠点を解消し、容易に組立可能
で、機械的強度もあり、かつ電気的接続にも安定である
立体化された集積回路装置を提供するものである。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a three-dimensional integrated circuit device that can be easily assembled, has mechanical strength, and is stable in electrical connection.

そして本発明の複合型半導体装置は、主面に沿って配置
された複数の回路素子及びこの回路素子に接続する前記
主面上を延長する導電路を含む第1の半導体薄板と、少
なくとも一つの回路素子とこの回路素子に接続し主面上
を延長する他の導電路を含む第2の半導体薄板とを含み
、前記第1と第2の半導体薄板はその主面が互シ、)に
対面するように配置され前記第2の半導体薄板上の導電
路はそれに対応する前記第1の半導体薄板上の導電路に
導電材部分を介して接続されており、この導電材部分に
よって前記第1と第2の半導体薄板は互いに一体に固着
されて成ることを特徴とする。
The composite semiconductor device of the present invention includes a first semiconductor thin plate including a plurality of circuit elements disposed along a main surface and a conductive path extending on the main surface connected to the circuit elements, and at least one a second semiconductor thin plate including a circuit element and another conductive path connected to the circuit element and extending on the main surface, the first and second semiconductor thin plates having their main surfaces facing each other; The conductive path on the second semiconductor thin plate is connected to the corresponding conductive path on the first semiconductor thin plate via a conductive material portion, and the conductive path is connected to the first semiconductor thin plate through the conductive material portion. The second semiconductor thin plates are characterized in that they are integrally fixed to each other.

以下本発明による実施例を図面に従って説明する。Embodiments according to the present invention will be described below with reference to the drawings.

図において1及び11はそれぞれシリコン等より成る半
導体単結晶薄板で、薄板1はその一方の主面に配置され
た複数の回路素子2を含む。一方薄板11はその両主面
に沿ってそれぞれ−乃至複数の回路素子12を含む。回
路素子2及び12は不純物の選択拡散法によって形成さ
れたPn接合を用いたトランジスタ、ダイオード等の能
動素子あるいは抵抗コンデンサ等の受動素子である。各
薄板の主面はシリコン基板から熱生成したシリコン酸化
g5あるいは15で覆われている。絶縁膜3あるいは1
3として気相より沈着したsiagやシリコン窒化物で
も良い。各薄板上では各回路素子2あるいは12に接続
し絶縁膜3あるいは13上を鴬長する導電路4あるいは
14がそれぞれ設けられ、その上にさらに絶縁層5ある
いは15がそれぞれ被覆されている。絶縁層5あるいは
15としrP*oi、Room 、PbO等の成分を含
む一般的なガラスあるいは気相から沈着されたシリコン
窒化物を用いることができる。そして両生導体薄板1及
び11は互いにその主面が対面するように配置され、一
方の薄板の一主面上にある導電路は他方の薄板の一主面
上にある導電路に導電ボール6及び半田材7によって電
気的に接続され、しかも両薄板はこのような導電メール
6及び半田材7によって一体に固着されている。
In the figure, reference numerals 1 and 11 each represent a semiconductor single crystal thin plate made of silicon or the like, and the thin plate 1 includes a plurality of circuit elements 2 arranged on one main surface thereof. On the other hand, the thin plate 11 includes a plurality of circuit elements 12 along both main surfaces thereof. The circuit elements 2 and 12 are active elements such as transistors and diodes, or passive elements such as resistive capacitors, using Pn junctions formed by selective diffusion of impurities. The main surface of each thin plate is covered with silicon oxide G5 or 15 thermally generated from the silicon substrate. Insulating film 3 or 1
3 may be siag or silicon nitride deposited from the gas phase. On each thin plate, a conductive path 4 or 14 is provided which connects to each circuit element 2 or 12 and extends over an insulating film 3 or 13, and is further covered with an insulating layer 5 or 15, respectively. As the insulating layer 5 or 15, a common glass containing components such as rP*oi, Room, PbO or silicon nitride deposited from the vapor phase can be used. The bidirectional conductive thin plates 1 and 11 are arranged so that their main surfaces face each other, and the conductive path on one main surface of one thin plate is connected to the conductive ball 6 and the conductive path on one main surface of the other thin plate. They are electrically connected by solder material 7, and both thin plates are fixed together by such conductive mail 6 and solder material 7.

各i電路は半導体薄板の側面にあるいは他方の主面に電
極層を設けることにより外部回路に接続することができ
る。又回路素子として半導体薄板内に設けるかわりにガ
ラス層5あるいは15上に蒸着された抵抗材料層あるい
は金属層−誘電層−金属層の構造を有する受動素子を設
けても良い。
Each i-conductor can be connected to an external circuit by providing an electrode layer on the side surface of the semiconductor thin plate or on the other main surface. Further, instead of being provided as a circuit element in the semiconductor thin plate, a resistive material layer or a passive element having a metal layer-dielectric layer-metal layer structure may be provided on the glass layer 5 or 15.

本発明は以上説明したような構成を有しているので従来
の集積回路における構造に比して、(1)半導体薄板の
両面を使用できる、(2)一定空間内に多数の回路素子
を構成することができる、(3)回路素子間の電気的接
続を確実にかつ容易に行い得る、(4)機械的強度が大
である等の利点がある。
Since the present invention has the configuration described above, compared to the structure of conventional integrated circuits, (1) both sides of a semiconductor thin plate can be used, and (2) a large number of circuit elements can be configured within a certain space. (3) electrical connections between circuit elements can be made reliably and easily; and (4) mechanical strength is high.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による一実施例を示す断面図である。 1・・・・・・第1の半導体基板 11・・・・・・第2の半導体基板 2.12・・・・・・@路素子 3.13・・・・・・酸化膜 4.14・・・・・・導電路 5.15・・・・・・絶縁層 6・・・・・・導電接着材 7・・・・・・半田材 以上 FIG. 1 is a sectional view showing an embodiment according to the present invention. 1...First semiconductor substrate 11...Second semiconductor substrate 2.12... @ path element 3.13...Oxide film 4.14... Conductive path 5.15...Insulating layer 6... Conductive adhesive material 7...Solder material that's all

Claims (1)

【特許請求の範囲】[Claims] 主面に浦って配置された複数の回路素子及びこの回路素
子に接続する前記主面上を延長する導電路を含む第1の
半導体薄板と、少なくとも一つの回路素子とこの回路素
子に接続し主面上を延長する他の導電路を含む第2の半
導体薄板とを含み、前記第1と第2の半導体薄板はその
主面が互いに対面するように配置され前記第2の半導体
薄板上の導電路はそれに対応する前記第1の半導体薄板
上の導電路に導電材部分を介して接続されており、この
導電材部分によって前記第1と第2の半導体薄板は互い
に一体に固着されて成る複合型半導体装置。
a first semiconductor thin plate including a plurality of circuit elements arranged over a main surface and a conductive path extending on the main surface connected to the circuit elements; at least one circuit element and a conductive path connected to the circuit element; a second semiconductor thin plate including another conductive path extending on the main surface, the first and second semiconductor thin plates are arranged such that their main surfaces face each other, and the second semiconductor thin plate The conductive path is connected to the corresponding conductive path on the first semiconductor thin plate via a conductive material portion, and the first and second semiconductor thin plates are integrally fixed to each other by the conductive material portion. Composite semiconductor device.
JP2255682A 1982-02-15 1982-02-15 Composite type semiconductor device Pending JPS58140143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2255682A JPS58140143A (en) 1982-02-15 1982-02-15 Composite type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2255682A JPS58140143A (en) 1982-02-15 1982-02-15 Composite type semiconductor device

Publications (1)

Publication Number Publication Date
JPS58140143A true JPS58140143A (en) 1983-08-19

Family

ID=12086124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2255682A Pending JPS58140143A (en) 1982-02-15 1982-02-15 Composite type semiconductor device

Country Status (1)

Country Link
JP (1) JPS58140143A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1447849A3 (en) * 1997-03-10 2005-07-20 Seiko Epson Corporation Semiconductor device and circuit board having the same mounted thereon
KR101023991B1 (en) * 2002-06-27 2011-03-28 레이티언 캄파니 Multilayer stripline radio frequency circuits and interconnection methods

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1447849A3 (en) * 1997-03-10 2005-07-20 Seiko Epson Corporation Semiconductor device and circuit board having the same mounted thereon
EP1427016A3 (en) * 1997-03-10 2005-07-20 Seiko Epson Corporation Semiconductor device and circuit board mounted with the same
US6989605B2 (en) 1997-03-10 2006-01-24 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US7119445B2 (en) 1997-03-10 2006-10-10 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US7436071B2 (en) 1997-03-10 2008-10-14 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US7598619B2 (en) 1997-03-10 2009-10-06 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US7932612B2 (en) 1997-03-10 2011-04-26 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US8134237B2 (en) 1997-03-10 2012-03-13 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
KR101023991B1 (en) * 2002-06-27 2011-03-28 레이티언 캄파니 Multilayer stripline radio frequency circuits and interconnection methods

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