CN113299644A - 一种自带肖特基二极管结构的沟槽mos器件及制造方法 - Google Patents
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Abstract
本发明是自带肖特基二极管结构的沟槽MOS器件及制造方法,结构是有P‑wellMOSFET元胞和无P‑well肖特基元胞交错均匀分布。方法:1)准备外延片;2)外延片表面制作沟槽;3)沟槽内生成栅氧;4)沟槽MOSFET元胞区域P‑well光刻注入推进;5)N+source光刻注入推进;6)ILD淀积;7)欧姆接触孔光刻刻蚀;8)欧姆接触金属淀积光刻刻蚀;9)沟槽肖特基元胞区域肖特基接触孔光刻刻蚀;10)形成肖特基势垒;11)肖特基接触金属淀积光刻刻蚀;12)钝化层淀积光刻刻蚀;13)背金减薄。本发明优点:面积利用最大化,解决了欧姆接触和肖特基接触的矛盾;大幅缩短反向恢复时间,提高开关频率。
Description
技术领域
本发明涉及的是一种自带肖特基二极管结构的沟槽MOS器件及制造方法,具体涉及一种自带肖特基二极管结构的沟槽MOSFET器件的元胞结构及器件以及其工艺制作过程。
背景技术
沟槽MOSFET管是半导体常见的功率器件,包括源极、栅极和漏极三个接线端,其中栅极为控制端,通过向栅极加载电压,实现控制源极与漏极之间的通断,从而起到了控制器件开启和关断的目的。
现有技术沟槽MOSFET管存在开关频率较低的缺陷。
发明内容
本发明提出的是一种自带肖特基二极管结构的沟槽MOS器件及制造方法,其目的旨在克服现有技术存在的上述不足,利用肖特基二极管的特性大大缩短反向恢复时间,提高沟槽MOSFET管子的开关频率。
本发明的技术解决方案:自带肖特基二极管结构的沟槽MOSFET器件,其结构是沟槽MOSFET器件中集成有肖特基二极管。
优选的,由六角形元胞结构组成,六角形元胞结构包括有P-well的MOSFET元胞和无P-well的肖特基元胞。
优选的,所述的有P-well的MOSFET元胞和无P-well的肖特基元胞交错均匀分布于一个芯片中。
自带肖特基二极管结构的沟槽MOSFET器件的制造方法,包括以下工艺流程:
1)准备外延片;
2)在外延片表面制作沟槽;
3)在沟槽内生成栅氧;
4)对沟槽的MOSFET元胞区域进行P-well光刻、注入、推进;
5)对沟槽的MOSFET元胞区域进行N+source光刻、注入、推进;
6)对沟槽的MOSFET元胞区域进行ILD淀积;
7)对沟槽的MOSFET元胞区域进行欧姆接触孔的光刻、刻蚀;
8)对欧姆接触孔进行欧姆接触金属淀积、光刻、刻蚀;
9)对沟槽的肖特基元胞区域进行肖特基接触孔的光刻、刻蚀;
10)对肖特基接触孔进行肖特基势垒金属溅射,形成肖特基势垒;
11)对肖特基接触孔进行肖特基接触金属淀积、光刻、刻蚀;
12)进行钝化层淀积、光刻、刻蚀;
13)进行背金减薄。
优选的,所述的步骤1)具体是在外延设备中采用SiH4气氛、1100℃高温下在硅衬底上生长出外延。
优选的,所述的步骤2)中的沟槽的宽度为0.3~0.8μm、深度为0.8~1.7μm。
优选的,所述的步骤3)具体是在炉管设备中设置温度900~1100℃,并使用流量为4~12L/min的氧气,生长厚度为100~4000A。
优选的,所述的步骤4)中P-well注入剂量1E12~1E13,注入能量80~300KeV,推进温度1000~1100℃,推进时间30~60min。
优选的,所述的步骤5)中N+source注入剂量1E15~1E16,注入能量25~60KeV,推进温度900~1100℃,推进时间60s~30min。
优选的,所述的步骤6)中ILD二氧化硅采用APCVD方式淀积同时掺杂B、P元素,厚度为4000~15000A。
本发明的优点:结构设计合理,集成了肖特基器件于沟槽MOSFET器件中,采用六角交错结构将沟槽MOSFET元胞和肖特基元胞均匀分布于一个芯片中,面积利用最大化,过电流时电流均匀分布于芯片中;采用两次接触孔刻蚀、制作,很好的解决了欧姆接触和肖特基接触的矛盾;利用了沟槽MOS管的导通特性,按照沟槽肖特基的特性,应用最高电压达100V;肖特基二极管的N型电极与沟槽MOSFET管的漏极相连,P型电极与沟槽MOSFET管的源极相连;采用本发明复合结构可利用肖特基二极管的特性将反向恢复时间大大缩短,从而提高沟槽MOSFET管子的开关频率。
附图说明
图1是本发明自带肖特基二极管结构的沟槽MOSFET的结构示意图。
图2是本发明自带肖特基二极管结构的沟槽MOSFET的元胞结构的示意图。
图3是图2的剖面图。
图4是本发明自带肖特基二极管结构的沟槽MOSFET器件的工艺流程图。
图中的1是栅氧、2是多晶硅电极、3是P-well、4是N+source、5是欧姆接触孔、6是肖特基接触孔。
具体实施方式
下面结合实施例和具体实施方式对本发明作进一步详细的说明。
如图1所示,自带肖特基二极管结构的沟槽MOSFET器件,其结构是沟槽MOSFET器件中集成有肖特基二极管(肖特基器件)。
如图2、3所示,自带肖特基二极管结构的沟槽MOSFET器件。由六角形元胞结构组成,六角形元胞结构包括有P-well的MOSFET元胞和无P-well的肖特基元胞。
经实验证明,本发明采用六角形元胞结构并将有P-well的MOSFET元胞和无P-well的肖特基元胞交错均匀分布于一个芯片中。最终得到自带肖特基二极管结构的沟槽MOSFET器件,为本发明所实现的最优方案。
如图4所示,自带肖特基二极管结构的沟槽MOSFET器件的制造方法,包括以下工艺流程:
1)准备外延片(采购或自主生产),具体是在外延设备中采用SiH4等气体环境、1100℃高温下在硅衬底上生长出外延;
2)在外延片表面制作沟槽,沟槽的宽度为0.3~0.8μm、深度为0.8~1.7μm;
3)在沟槽内生成栅氧,具体是在炉管设备中设置温度900~1100℃,并使用流量为4~12L/min的氧气,生长厚度为100~4000A;
4)对沟槽的MOSFET元胞区域进行P-well光刻、注入、推进,P-well注入剂量1E12~1E13,注入能量80~300KeV,推进温度1000~1100℃,推进时间30~60min;
5)对沟槽的MOSFET元胞区域进行N+source光刻、注入、推进,N+source注入剂量1E15~1E16,注入能量25~60KeV,推进温度900~1100℃,推进时间60s~30min;
6)对沟槽的MOSFET元胞区域进行ILD淀积,ILD二氧化硅采用APCVD方式淀积同时掺杂B、P元素,厚度约为4000~15000A;
7)对沟槽的MOSFET元胞区域进行欧姆接触孔的光刻、刻蚀;
8)对欧姆接触孔进行欧姆接触金属淀积、光刻、刻蚀;
9)对沟槽的肖特基元胞区域进行肖特基接触孔的光刻、刻蚀;
10)对肖特基接触孔进行肖特基势垒金属溅射,形成肖特基势垒;
11)对肖特基接触孔进行肖特基接触金属淀积、光刻、刻蚀;
12)进行钝化层淀积、光刻、刻蚀;
13)进行背金减薄。
以上所述的仅是本发明的优选实施方式,应当指出,对于本领域的普通技术人员来说,在不脱离本发明创造构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。
Claims (10)
1.自带肖特基二极管结构的沟槽MOSFET器件,其特征是沟槽MOSFET器件中集成有肖特基二极管。
2.如权利要求1所述的自带肖特基二极管结构的沟槽MOSFET器件,其特征是由六角形元胞结构组成,六角形元胞结构包括有P-well的MOSFET元胞和无P-well的肖特基元胞。
3.如权利要求1所述的自带肖特基二极管结构的沟槽MOSFET器件,其特征是所述的有P-well的MOSFET元胞和无P-well的肖特基元胞交错均匀分布于一个芯片中。
4.如权利要求3所述的自带肖特基二极管结构的沟槽MOSFET器件的制造方法,其特征是该方法包括以下工艺流程:
1)准备外延片;
2)在外延片表面制作沟槽;
3)在沟槽内生成栅氧;
4)对沟槽的MOSFET元胞区域进行P-well光刻、注入、推进;
5)对沟槽的MOSFET元胞区域进行N+source光刻、注入、推进;
6)对沟槽的MOSFET元胞区域进行ILD淀积;
7)对沟槽的MOSFET元胞区域进行欧姆接触孔的光刻、刻蚀;
8)对欧姆接触孔进行欧姆接触金属淀积、光刻、刻蚀;
9)对沟槽的肖特基元胞区域进行肖特基接触孔的光刻、刻蚀;
10)对肖特基接触孔进行肖特基势垒金属溅射,形成肖特基势垒;
11)对肖特基接触孔进行肖特基接触金属淀积、光刻、刻蚀;
12)进行钝化层淀积、光刻、刻蚀;
13)进行背金减薄。
5.如权利要求3所述的自带肖特基二极管结构的沟槽MOSFET器件的制造方法,其特征是所述的步骤1)具体是在外延设备中采用SiH4气氛、1100℃高温下在硅衬底上生长出外延。
6.如权利要求3所述的自带肖特基二极管结构的沟槽MOSFET器件的制造方法,其特征是所述的步骤2)中的沟槽的宽度为0.3~0.8μm、深度为0.8~1.7μm。
7.如权利要求3所述的自带肖特基二极管结构的沟槽MOSFET器件的制造方法,其特征是所述的步骤3)具体是在炉管设备中设置温度900~1100℃,并使用流量为4~12L/min的氧气,生长厚度为100~4000A。
8.如权利要求3所述的自带肖特基二极管结构的沟槽MOSFET器件的制造方法,其特征是所述的步骤4)中P-well注入剂量1E12~1E13,注入能量80~300KeV,推进温度1000~1100℃,推进时间30~60min。
9.如权利要求3所述的自带肖特基二极管结构的沟槽MOSFET器件的制造方法,其特征是所述的步骤5)中N+source注入剂量1E15~1E16,注入能量25~60KeV,推进温度900~1100℃,推进时间60s~30min。
10.如权利要求3所述的自带肖特基二极管结构的沟槽MOSFET器件的制造方法,其特征是所述的步骤6)中ILD二氧化硅采用APCVD方式淀积同时掺杂B、P元素,厚度为4000~15000A。
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080246082A1 (en) * | 2007-04-04 | 2008-10-09 | Force-Mos Technology Corporation | Trenched mosfets with embedded schottky in the same cell |
CN102088020A (zh) * | 2009-12-08 | 2011-06-08 | 上海华虹Nec电子有限公司 | 功率mos晶体管内集成肖特基二极管的器件及制造方法 |
CN206134681U (zh) * | 2016-11-01 | 2017-04-26 | 西安后羿半导体科技有限公司 | 高速的沟槽mos器件 |
CN106876485A (zh) * | 2017-03-06 | 2017-06-20 | 北京世纪金光半导体有限公司 | 一种集成肖特基二极管的SiC双沟槽型MOSFET器件及其制备方法 |
CN107170836A (zh) * | 2017-05-17 | 2017-09-15 | 扬州扬杰电子科技股份有限公司 | 元胞版图、元胞结构及碳化硅结势垒肖特基二极管的制作方法 |
CN110517988A (zh) * | 2019-09-16 | 2019-11-29 | 富芯微电子有限公司 | 一种具有复合栅结构的igbt芯片及其加工工艺与加工设备 |
CN111446293A (zh) * | 2020-03-25 | 2020-07-24 | 浙江大学 | 一种增强体二极管的碳化硅功率mosfet器件 |
-
2021
- 2021-05-21 CN CN202110556172.7A patent/CN113299644A/zh active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080246082A1 (en) * | 2007-04-04 | 2008-10-09 | Force-Mos Technology Corporation | Trenched mosfets with embedded schottky in the same cell |
CN102088020A (zh) * | 2009-12-08 | 2011-06-08 | 上海华虹Nec电子有限公司 | 功率mos晶体管内集成肖特基二极管的器件及制造方法 |
CN206134681U (zh) * | 2016-11-01 | 2017-04-26 | 西安后羿半导体科技有限公司 | 高速的沟槽mos器件 |
CN106876485A (zh) * | 2017-03-06 | 2017-06-20 | 北京世纪金光半导体有限公司 | 一种集成肖特基二极管的SiC双沟槽型MOSFET器件及其制备方法 |
CN107170836A (zh) * | 2017-05-17 | 2017-09-15 | 扬州扬杰电子科技股份有限公司 | 元胞版图、元胞结构及碳化硅结势垒肖特基二极管的制作方法 |
CN110517988A (zh) * | 2019-09-16 | 2019-11-29 | 富芯微电子有限公司 | 一种具有复合栅结构的igbt芯片及其加工工艺与加工设备 |
CN111446293A (zh) * | 2020-03-25 | 2020-07-24 | 浙江大学 | 一种增强体二极管的碳化硅功率mosfet器件 |
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CN114664926A (zh) * | 2022-03-30 | 2022-06-24 | 电子科技大学 | 一种功率半导体器件结构 |
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