CN113223956A - Cmp研磨方法 - Google Patents
Cmp研磨方法 Download PDFInfo
- Publication number
- CN113223956A CN113223956A CN202110467282.6A CN202110467282A CN113223956A CN 113223956 A CN113223956 A CN 113223956A CN 202110467282 A CN202110467282 A CN 202110467282A CN 113223956 A CN113223956 A CN 113223956A
- Authority
- CN
- China
- Prior art keywords
- polysilicon
- film
- silicon oxide
- cmp
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 83
- 238000005498 polishing Methods 0.000 title claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 77
- 230000008569 process Effects 0.000 claims abstract description 65
- 229920005591 polysilicon Polymers 0.000 claims abstract description 57
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 37
- 238000000227 grinding Methods 0.000 claims abstract description 32
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 238000012545 processing Methods 0.000 claims abstract description 4
- 230000008021 deposition Effects 0.000 claims description 8
- 238000007667 floating Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000009279 wet oxidation reaction Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 2
- 239000002210 silicon-based material Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 42
- SJHPCNCNNSSLPL-CSKARUKUSA-N (4e)-4-(ethoxymethylidene)-2-phenyl-1,3-oxazol-5-one Chemical compound O1C(=O)C(=C/OCC)\N=C1C1=CC=CC=C1 SJHPCNCNNSSLPL-CSKARUKUSA-N 0.000 description 8
- 230000006872 improvement Effects 0.000 description 7
- 238000012876 topography Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010668 complexation reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
本发明公开了一种CMP研磨方法,首先,在炉管内淀积完多晶硅薄膜之后,进行氧化工艺,在多晶硅层的表面生成一层氧化硅薄膜;然后采用DSTI CMP工艺做研磨加工,去除凸起图形处多晶硅薄膜表面的氧化硅薄膜,包括STI区域、有源区以及隔离区;最后进行针对多晶硅薄膜的多晶硅CMP工艺。本发明利用氧化膜CMP工艺的高选择比先取出凸起处的氧化硅薄膜,研磨终止于多晶硅薄膜,然后再利用多晶硅CMP工艺的高选择比增加工艺窗口,去除残留的多晶硅,更有效地解决多晶硅残留问题,同时兼顾解决了研磨过度导致的凹陷的问题。
Description
技术领域
本发明涉及半导体制造领域,特别是指一种CMP研磨方法。
背景技术
化学机械研磨(CMP)是一种表面全局平坦化技术,它通过硅片和一个抛光头之间的相对运动来平坦化硅片表面。在抛光头和硅片之间有磨料,并同时施加下压力。
CMP在进行制品研磨前,先要确定一套研磨工艺参数(包括:流量、压力和转速等),然后使用该套参数对同膜种的无图形片进行研磨,计算出该套工艺的研磨速率:(研磨前膜厚-研磨后膜厚)/研磨时间=研磨速率。
再根据制品所需要的研磨量,计算出所需研磨时间: 研磨量/研磨速率=研磨时间。由于研磨部件属于消耗品,因此研磨速率会有波动,从而导致CMP后的实际膜厚与理论膜厚存在偏差。通过计算这个偏差值, integrated Advanced Process Control software(iAPC)会对研磨时间进行调整,使CMP后的薄膜膜厚与目标值相近。
多晶硅化学机械研磨(CMP)在IC加工工艺中的用途日益广泛,但CMP固有的图形载入效应,会造成不同大小图形之间的研磨速率差异,严重影响了工艺的均匀性和工艺控制窗口。
如图1~3所示,以ETOX闪存(ETOX:EPROM with Tunnel Oxide或者ErasableProgrammable Read Only Memorywith Tunnel Oxide,可擦除可编程只读寄存器隧道氧化层NOR(或非)型闪存属于一种非易失性闪存,其特点是应用程序可以直接在闪存内运行,不必再把代码读到系统随机存储器中,从而使其具有较高的传输效率,因此,该类型闪存的应用比较广泛)结构中浮栅多晶硅(FGPL)CMP工艺为例, STI区域 CMP不足会导致多晶硅残留,而同时有源区(AA)区域 CMP OP过度则会导致沟渠型的凹陷形貌。即在芯片结构布局中的结构密集区CMP不足会导致多晶硅残留,而相对比较宽松的隔离区ISO区域CMP过度会导致凹陷型形貌。
随着芯片技术的发展,传统的改善方法,比如增加Dummy图形,规范设计尺寸规则等,也越来越不能满足实际应用的需要。
发明内容
本发明所要解决的技术问题在于提供一种CMP研磨方法,能有效去除多晶硅解决多晶硅残留问题,同时兼顾研磨过度导致的凹陷问题。
为解决上述问题,本发明所述的一种CMP研磨方法,CMP研磨方法,其特征在于:首先,在炉管内淀积完多晶硅薄膜之后,进行氧化工艺,在多晶硅层的表面生成一层氧化硅薄膜。
然后采用D-STI CMP工艺做研磨加工,去除凸起图形处多晶硅薄膜表面的氧化硅薄膜,包括STI区域、有源区以及隔离区。
D-STI CMP工艺一种先进的STI CMP工艺,采用带有压力敏感大分子添加剂的研磨液,可以实现所谓的“Auto-stop(自动终止)“功能,即对图形突起部分有高研磨速率的同时,对图形低洼处通过大分子络合进行保护,实现超平的研磨效果。D-STI CMP工艺与传统的STI CMP工艺的主要区别就在于这个“D”上,D是指“Direct”,即在绝缘层淀积之后通过直接的CMP工艺来完成STI的制作。本发明在多晶硅薄膜的表面形成的一层氧化硅薄膜很薄,采用D-STI CMP工艺很有必要。
最后进行针对多晶硅薄膜的多晶硅CMP工艺。
进一步的改进是,所述的氧化硅薄膜的淀积厚度要完全填充覆盖多晶硅薄膜表面的凹陷或者狭缝区域,淀积完后形成的氧化硅薄膜表面形貌尽可能平坦。
进一步的改进是,所述的DSTI CMP工艺,利用氧化硅与多晶硅材料之间的高选择比,去除凸起图形区域多晶硅薄膜表面的氧化硅薄膜。
进一步的改进是,所述多晶硅层的CMP加工,有源区内的多晶硅薄膜上方保留有氧化硅薄膜,利用多晶硅CMP工艺的高选择比,增加工艺窗口,有效减少STI区域的多晶硅研磨残留问题。
进一步的改进是,所述多晶硅CMP工艺的选择比为2:1~200;一般大于50:1。
进一步的改进是,所述的在多晶硅薄膜表面形成氧化硅薄膜,采用干法氧化工艺或者是湿法氧化工艺。。
本发明所述的CMP研磨方法,增加一步氧化膜淀积工艺,利用氧化膜CMP工艺的高选择比先取出凸起处的氧化硅薄膜,研磨终止于多晶硅薄膜,然后再利用多晶硅CMP工艺的高选择比增加工艺窗口,去除残留的多晶硅,更有效地解决多晶硅残留问题,同时兼顾解决了研磨过度导致的凹陷的问题。
附图说明
图1 是ETOX闪存在多晶硅薄膜淀积之前的形貌示意图。
图2 是ETOX闪存在多晶硅薄膜淀积之后的形貌示意图。
图3 是ETOX闪存在多晶硅薄膜CMP工艺之后的形貌示意图。
图4 是ETOX闪存在多晶硅薄膜淀积之后再淀积一层氧化硅薄膜的形貌示意图。
图5是图4所示结构进行氧化硅CMP工艺之后的形貌示意图。
图6 是图5所示工艺之后再进行多晶硅CMP工艺之后的形貌示意图。
图7 是本发明工艺流程示意图。
具体实施方式
以下结合附图给出本发明的具体实施方式,对本发明中的技术方案进行清楚、完整的描述,但本发明不限于以下的实施方式。显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比率,仅用于方便、明晰地辅助说明本发明实施例的目的。本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例,都属于本发明保护的范围。
本发明能够以不同形式实施,而不应当解释为局限于这里提出的实施例。相反地,提供这些实施例将使公开彻底和完全,并且将本发明的范围完全地传递给本领域技术人员。在附图中,为了清楚,层和区的尺寸以及相对尺寸可能被夸大,自始至终相同附图标记表示相同的元件。空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等,在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白,除了图中所示的取向以外,空间关系术语意图还包括使用和操作中的器件的不同取向。例如,如果附图中的器件翻转,然后,描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此,示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
本发明所述的CMP研磨方法,针对传统的具有凹凸不平表面形貌的多晶硅CMP研磨工艺容易出现的研磨不足导致多晶硅残留,而研磨过度又会出现凹陷的问题,本发明提出一种新的工艺方法,在多晶硅薄膜表面再形成一层氧化硅薄膜,然后先利用氧化硅薄膜的CMP研磨工艺先进行氧化硅的研磨,再利用多晶硅CMP研磨工艺来针对多晶硅薄膜进行CMP,最后能解决多晶硅研磨的残留问题,同时兼顾解决过度研磨所带来的凹陷问题。
以ETOX 闪存的浮栅多晶硅CMP工艺来说,首先基于传统工艺,如图1及图2所示,在器件的浮栅多晶硅炉管工艺的生长之后,即在图2所示的工艺形成的器件形貌之后,在器件表面形成了一层多晶硅薄膜,如图4所示。所述多晶硅薄膜在后面的工艺中将被刻蚀形成浮栅。本发明工艺再在多晶硅薄膜的表面淀积一层一定厚度的氧化硅薄膜,图中氧化硅薄膜需要完全覆盖住多晶硅薄膜,包括凸起的部分。氧化硅薄膜的形成工艺包括采用干法氧化工艺,湿法氧化工艺或者CVD工艺。具体如采用炉管热氧化,包括在多晶硅炉管工艺中的原位氧化,或者是快速热氧化RTO,或者ISSG工艺。
如图5所示,再采用D-STI CMP进行一次研磨工艺,利用其氧化硅CMP工艺针对氧化硅与多晶硅之间的高选择比,去除凸起图形处多晶硅表面的氧化硅薄膜,研磨中止于露出的多晶硅薄膜层。以ETOX 闪存的浮栅多晶硅 CMP工艺来说,STI区域处于凸起处,可以去除氧化膜,而像PIP电容这样的区域位于有源区AA内,相比其周围的STI区域,可以保留氧化硅薄膜。
如图6所示,再进行多晶硅CMP工艺,因为有源区AA区域有保留的氧化硅薄膜,利用多晶硅CMP工艺对多晶硅与氧化硅研磨的高选择比,多晶硅与氧化硅的研磨选择比为2:1~200;一般大于50:1,可以增加研磨的工艺窗口,更加有效地解决多晶硅的残留问题,同时兼顾解决过度研磨导致的凹陷问题。如图6中所示的多晶硅CMP研磨之后,整体表面平坦,且无多晶硅残留,也没有产生过度研磨所出现凹陷现象。
多晶硅刻蚀完成之后形成浮栅等后续的结构工艺。
以上仅为本发明的优选实施例,并不用于限定本发明。对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (7)
1.一种CMP研磨方法,其特征在于:首先,在晶圆上制作STI,划分有源区以及隔离区,所述有源区及隔离区有不同的器件密度;利用炉管工艺在所述晶圆上淀积一层多晶硅薄膜;多晶硅薄膜淀积完成之后,再进行氧化工艺,在多晶硅薄膜的表面再形成一层氧化硅薄膜;
然后采用D-STI CMP工艺做研磨加工,去除凸起图形处多晶硅薄膜表面的氧化硅薄膜,包括STI区域、有源区以及隔离区;
最后进行针对多晶硅薄膜的多晶硅CMP工艺。
2.如权利要求1所述的CMP研磨方法,其特征在于:所述的氧化硅薄膜的淀积厚度要完全填充覆盖多晶硅薄膜表面的凹陷或者狭缝区域,淀积完后形成的氧化硅薄膜表面形貌尽可能平坦。
3.如权利要求1所述的CMP研磨方法,其特征在于:所述的D-STI CMP工艺,利用氧化硅与多晶硅材料之间的高选择比,去除凸起图形区域多晶硅薄膜表面的氧化硅薄膜,研磨中止于多晶硅薄膜表面。
4.如权利要求1所述的CMP研磨方法,其特征在于:所述多晶硅薄膜的CMP加工,有源区内的多晶硅薄膜上方保留有氧化硅薄膜,利用多晶硅CMP工艺的高选择比,增加工艺窗口,有效减少STI区域的多晶硅研磨残留问题。
5.如权利要求4所述的CMP研磨方法,其特征在于:所述多晶硅CMP工艺的选择比为2:1~200:1。
6.如权利要求1所述的CMP研磨方法,其特征在于:所述的在多晶硅薄膜表面形成氧化硅薄膜,采用干法氧化工艺,湿法氧化工艺或者CVD工艺;包括在多晶硅炉管工艺中的原位氧化,或者是快速热氧化RTO,或者ISSG工艺。
7.如权利要求1所述的CMP研磨方法,其特征在于:所述的氧化硅薄膜刻蚀完成之后形成浮栅以及后段结构工艺。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110467282.6A CN113223956A (zh) | 2021-04-28 | 2021-04-28 | Cmp研磨方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110467282.6A CN113223956A (zh) | 2021-04-28 | 2021-04-28 | Cmp研磨方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113223956A true CN113223956A (zh) | 2021-08-06 |
Family
ID=77089697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110467282.6A Withdrawn CN113223956A (zh) | 2021-04-28 | 2021-04-28 | Cmp研磨方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN113223956A (zh) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101071786A (zh) * | 2006-05-09 | 2007-11-14 | 茂德科技股份有限公司(新加坡子公司) | 在集成电路制造工艺中平坦化一表面的方法 |
-
2021
- 2021-04-28 CN CN202110467282.6A patent/CN113223956A/zh not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101071786A (zh) * | 2006-05-09 | 2007-11-14 | 茂德科技股份有限公司(新加坡子公司) | 在集成电路制造工艺中平坦化一表面的方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7452817B2 (en) | CMP method providing reduced thickness variations | |
KR100799151B1 (ko) | 플래시 메모리 소자의 소자 분리막 형성방법 | |
US8143156B2 (en) | Methods of forming high density semiconductor devices using recursive spacer technique | |
US20070264827A1 (en) | Method for achieving uniform chemical mechanical polishing in integrated circuit manufacturing | |
CN104979295B (zh) | 嵌入式分栅闪存器件的制造方法 | |
CN102254867B (zh) | 快闪存储器的制作方法 | |
US7589022B2 (en) | Method of chemical mechanical polishing and method of fabricating semiconductor device using the same | |
CN102361021A (zh) | 一种嵌入式闪存的制作方法 | |
CN102361022B (zh) | 一种嵌入式闪存的制作方法 | |
CN113223956A (zh) | Cmp研磨方法 | |
CN104576539B (zh) | 半导体结构形成方法 | |
US6190999B1 (en) | Method for fabricating a shallow trench isolation structure | |
CN105140176B (zh) | 一种半导体器件及其制造方法和电子装置 | |
CN110265294B (zh) | 一种提高浮栅厚度均匀性的方法及一种半导体结构 | |
US20100093165A1 (en) | Method of fabricating integrated circuit semiconductor device having gate metal silicide layer | |
CN108389790B (zh) | 浮栅的形成方法和浮栅型存储器 | |
Boyd et al. | A One‐Step Shallow Trench Global Planarization Process Using Chemical Mechanical Polishing | |
US6133114A (en) | Method for fabricating a shallow trench isolation | |
US8288280B2 (en) | Conductor removal process | |
US6897121B2 (en) | Method of removing HDP oxide deposition | |
CN108598082A (zh) | 闪存制备方法 | |
CN103943571A (zh) | 非易失性存储器的制造方法 | |
KR100373355B1 (ko) | 반도체소자의 평탄화방법 | |
CN110797341B (zh) | 闪存器件及其制作方法 | |
CN115692180A (zh) | 增加闪存器件工艺窗口的方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WW01 | Invention patent application withdrawn after publication | ||
WW01 | Invention patent application withdrawn after publication |
Application publication date: 20210806 |