CN113161316A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113161316A
CN113161316A CN202011409949.9A CN202011409949A CN113161316A CN 113161316 A CN113161316 A CN 113161316A CN 202011409949 A CN202011409949 A CN 202011409949A CN 113161316 A CN113161316 A CN 113161316A
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China
Prior art keywords
electrode
wire
semiconductor device
semiconductor
bonding
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CN202011409949.9A
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English (en)
Inventor
丸山一哉
佐野努
西城淳一
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Kioxia Corp
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Kioxia Corp
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Publication of CN113161316A publication Critical patent/CN113161316A/zh
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Abstract

实施方式的半导体装置具备第1电极、第2电极、以及在所述第1电极与所述第2电极之间延伸的导线。所述导线包含：第1导电体，与所述第1电极及所述第2电极相接；以及第2导电体，以不与所述第1电极及所述第2电极相接的方式设置在所述第1导电体内。

Description

半导体装置
相关申请案的引用
本申请案基于2020年01月07日提出申请的在先日本专利申请案第2020-000795号的优先权而主张优先权利益，通过引用将其全部内容并入本文中。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
作为将电极间电连接的方法，已知有导线接合。
发明内容
一实施方式提供一种半导体装置，使半导体装置的导线及焊垫间的接合可靠性提高。
实施方式的半导体装置具备第1电极、第2电极、以及在所述第1电极与所述第2电极之间延伸的导线。所述导线包含：第1导电体，与所述第1电极及所述第2电极相接；以及第2导电体，以不与所述第1电极及所述第2电极相接的方式设置在所述第1导电体内。
根据所述构成，可提供一种使导线及焊垫间的接合可靠性提高的半导体装置。
附图说明
图1是表示实施方式的半导体装置的整体构成的俯视图。
图2是沿图1的II-II线的半导体装置的剖视图。
图3是将图2的区域III放大后的半导体装置的剖视图。
图4是用来说明实施方式的半导体装置的制造工程中的导线接合处理的流程图。
图5是用来示意性地说明实施方式的半导体装置的制造工程中的导线接合处理的部分的剖视图。
图6是变化例的半导体装置的剖视图。
图7是用来说明变化例的半导体装置的制造工程中的导线接合处理的流程图。
图8是应用例的半导体装置的框图。
具体实施方式
以下，参考附图对实施方式进行说明。各实施方式例示出用来使发明的技术思想具体化的装置或方法。附图是示意性或概念性的图，各附图的尺寸及比率等未必与实际情况相同。本发明的技术思想并非由构成要素的形状、构造、配置等来特定。
另外，以下的说明中，某物质的“直径”是指该物质的与延伸方向垂直的截面上该物质的外侧直径的平均值。
1.实施方式 对实施方式的半导体装置进行说明。
1.1构成 首先，对实施方式的半导体装置的构成进行说明。
1.1.1半导体装置 图1是用来说明实施方式的半导体装置的构成的俯视图。图1中，为了方便说明，省略覆盖半导体装置的绝缘体而图示。
如图1所示，半导体装置1具备半导体衬底10、半导体芯片20、多个引线端子30、及多条导线40。半导体芯片20积层在半导体衬底10上。以下的说明中，将半导体芯片20在半导体衬底10上积层的方向设为上方向。即，半导体芯片20设置在半导体衬底10的上表面上。
半导体芯片20经由对应的导线40分别与多个引线端子30电连接。由此，半导体芯片20可经由多个引线端子30与半导体装置1的外部进行信息通信，而且可从半导体装置1的外部供给电源。
此外，图1中，作为半导体装置1的一例，例示出用于车载设备、移动设备等的QFN(Quad Flat Non-leaded package，无引线四方扁平封装)，但并不限于此。例如，半导体装置1也可以是设置在半导体衬底10上的多个半导体装置中的一个。该情况下，引线端子30也可并非设置在引线框架上的端子，而是设置在半导体衬底10上的其它半导体装置的端子。引线端子30也可设置在配线衬底(例如所谓的印刷衬底)上。
图2是沿图1的II-II线切开半导体装置1所得的剖视图。
如图2所示，半导体衬底10、半导体芯片20、多个引线端子30、及多条导线40由绝缘体50密封。
在半导体芯片20的上表面上，设置着多个焊垫电极21。1个焊垫电极21与1个引线端子30例如对应地设置，且它们经由至少1条导线40物理连接且电连接。即，导线40是包含与对应的焊垫电极21接合的第1端、及与对应的引线端子30接合的第2端的导电体。
1.1.2接合部分的详情 图3是半导体装置1的局部剖视图，将图2的区域III放大表示。图3中，主要图示出焊垫电极21与导线40的第1端的接合部分的详情。
如图3所示，在半导体芯片20的上表面中未设置焊垫电极21的区域上，例如设置着包含聚酰亚胺的绝缘体22。绝缘体22例如具有厚度D4。由此，焊垫电极21的上表面被设计成位于距绝缘体22的上表面为D4的下方。
导线40包含芯材41及涂覆材42。
芯材41例如是包含选自铜(Cu)、金(Au)、银(Ag)、及铝(Al)中的至少1种金属的导电体，具有作为焊垫电极21及引线端子30间的通信路径的功能。
涂覆材42例如是包含钯(Pd)的导电体，通过被覆芯材41的外周而抑制芯材41与导线40的外部(尤其是焊垫电极21)相接。因此，导线40中，与该导线40的外部相接的部分是涂覆材42，芯材41是除导线40的切断面以外不与该导线40的外部相接(分离)。涂覆材42的厚度D3例如比芯材41的直径D1及D2薄。
导线40的第1端包含具有切断面的部分40A、朝引线端子30延伸的部分40C、以及设置在部分40A及40C之间且具有与焊垫电极21的接合面的部分40B。导线40的第1端的部分40B的直径D2例如小于部分40C的直径D1。更具体而言，例如，直径D2可设定为直径D1的1/5以上1/2以下的范围(D1×1/5≦D2≦D1×1/2)。另外，例如，直径D2设定为大于绝缘体22的厚度D4(D2＞D4)。
此处，直径D1能应用任意的大小，根据半导体装置1的用途而设计成适当的大小。例如，在半导体装置1是功耗量较大的功率半导体的情况下，直径D1可设计为100微米(μm)以上500微米(μm)以下的范围。另外，例如，在半导体装置1是功耗量较小的闪速存储器、集成电路、分立半导体、或LED(Light emitting diode，发光二极管)之类的半导体存储装置的情况下，直径D1可设计为15微米(μm)以上80微米(μm)以下的范围。
在导线40的第1端的部分40B中包含与焊垫电极21的接合面的区域，直径D2均匀。换句话说，导线40的第1端在部分40B，具有与焊垫电极21的上表面实质上平行的上表面。
在导线40与焊垫电极21的接合面，焊垫电极21与涂覆材42相接。涂覆材42在该接合面存在于芯材41与焊垫电极21之间，因此焊垫电极21与芯材41不相接。
这样，导线40构成为在与焊垫电极21接合的部分40B能够区分芯材41与涂覆材42。该构造是通过楔形接合而非球形接合来实现，所述球形接合是使熔融成球形状的导线的第1端与焊垫电极接合，所述楔形接合是通过将导线压接在焊垫电极上而使导线的第1端不熔融地接合到焊垫电极上。
此外，对于导线40的第2端的与引线端子30的接合部，也可应用所述楔形接合(省略图示)。由此，涂覆材42在与引线端子30的接合部，也和图3所示的与焊垫电极21的接合部同样，与引线端子30接合，但芯材41不与引线端子30相接。
1.2制造方法 以下，对实施方式的半导体装置的制造工程中的焊垫电极间的导线接合处理的一例进行说明。图4是用来说明实施方式的半导体装置的导线接合处理的流程图。图5是用来示意性地说明图4所示的导线接合处理中针对焊垫电极21的导线接合处理的剖视图。
实施方式的半导体装置的导线接合处理例如是使用了能够执行球形接合处理的接合装置(未图示)的楔形接合处理。此外，接合装置所含的构成中，作为导线与焊垫的接口发挥功能的焊针在图4及图5中，图示为焊针60。另外，设定在焊针60且成为导线40的材料的导线在图4及图5中，图示为包含芯材41'、及被覆该芯材41'之涂覆材42'的导线40'。
首先，参考图4说明导线接合处理的流程。
如图4所示，步骤ST11中，将导线40'设定在焊针60。具体而言，例如，导线40'设定为穿过焊针60内、且从焊针60的前端延伸特定长度的状态。
步骤ST12中，接合装置控制焊针60，将焊针60前端的导线40'的涂覆材42'与焊垫电极21接合。更具体而言，例如，接合装置一面施加超音波振动一面将焊针60前端的导线40'压抵在焊垫电极21上。由此，压抵在焊垫电极21上的导线40'一方面芯材41'塑性变形，一方面涂覆材42'接合到焊垫电极21上。
步骤ST13中，接合装置一面将导线40'从焊针60的前端卷出一面使焊针60从焊垫电极21的上方移动到引线端子30的上方。由此，导线40'中，接合到焊垫电极21的部分、与焊针60的前端之间的部分在焊垫电极21与引线端子30之间构成环路。
步骤ST14中，接合装置控制焊针60，将焊针60前端的导线40'的涂覆材42'与引线端子30接合。更具体而言，例如，接合装置一面施加超音波振动一面将焊针60前端的导线40'压抵在引线端子30上。由此，压抵在引线端子30上的导线40'中，一方面主要芯材41'塑性变形，一方面涂覆材42'接合到引线端子30上。
步骤ST15中，接合装置控制焊针60，将导线40'在接合到引线端子30的部分与焊针60的前端之间切断。由此，形成具有接合到焊垫电极21的第1端、及接合到引线端子30的第2端的导线40。
通过以上操作，导线接合处理结束。
接下来，参考图5，对图4所示的流程中步骤ST12中的焊针60、导线40'、及焊垫电极21的状态进行说明。
如图5所示，将导线40'接合到焊垫电极21时，导线40'在绝缘体22的上方位于焊针60的外部，且具有包含切断面的部分40A'、夹在焊针60的前端与焊垫电极21之间的部分40B'、及收纳在焊针60内部的40C'。如上所述，导线40'的部分40B'利用来自焊针60的压力及超音波振动而接合到焊垫电极21上。当接合时，通过将该压力及超音波振动控制为特定值，而使导线40'的部分40B'处的直径D2从导线40'的部分40C'处的直径D1的1/2以上变形成1/5以下的厚度。然而，涂覆材42'并未被切断，而是保持为大致固定的厚度D3。由此，导线40'的部分40B'中，芯材41'并未直接与焊垫电极21相接，而是经由涂覆材42'与焊垫电极21接合。
另外，焊针60中将导线40'压抵于焊垫电极21的部分具有相对于焊针的按压方向大致平行的面。因此，导线40'的部分40B'遍及与焊垫电极21的接合面受到均匀的压力，而形成为均匀的厚度D2。
此外，以上说明的制造工程只是一例，也可以在各制造工程之间插入其它处理，还可以在不产生问题的范围内改变制造工程的顺序。
1.3本实施方式的效果 根据本实施方式，导线40通过楔形接合而与焊垫电极21及引线端子30接合。换句话说，在将导线40与焊垫电极21及引线端子30接合时，并未应用球形接合。由此，导线40可不熔融成球形状便与焊垫电极21接合。因此，在与焊垫电极21接合的部分40B，可将涂覆材42以与芯材41分离的状态与焊垫电极21相接，并且将芯材41与焊垫电极21及导线40的外部分离设置。因此，可提高导线40及焊垫电极21间的接合可靠性。
补充而言，芯材41所含的金属可能会被存在于导线40外部的氯(Cl)或硫(S)等物质腐蚀，但涂覆材42所含的金属可采用对该物质所造成的腐蚀的耐性高于芯材41的物质。由此，涂覆材42可保护芯材41免受该物质的腐蚀。根据本实施方式，芯材41在与部分40B接合时并未熔融成球形状，所以芯材41不会与涂覆材42混杂。由此，芯材41可在保持与导线40的外部相接的可能性比球形接合时低的状态的情况下与焊垫电极21接合。因此，可抑制芯材41所含的金属被导线40外部的物质腐蚀。因而，可抑制该腐蚀所导致的导线40及焊垫电极21间的接合可靠性的劣化。
另外，再补充而言，有如下情况，即，芯材41所含的金属因与焊垫电极21所含的铝(Al)接触而与该铝(Al)形成合金层。该合金层有可能使导线40及焊垫电极21间的接合可靠性恶化，故不佳。根据本实施方式，芯材41在与部分40B接合时并未熔融成球形状，所以芯材41不会与涂覆材42混杂。由此，芯材41可在保持与焊垫电极21相接的可能性比球形接合时低的状态的情况下与焊垫电极21接合。因此，可抑制芯材41所含的金属与焊垫电极21之间形成合金层。因而，可抑制该腐蚀所导致的导线40及焊垫电极21间的接合可靠性的劣化。
另外，本实施方式的导线接合处理可使用能够进行球形接合的球形接合机来执行。由此，该导线接合处理对于楔形接合机无法应用的较细(15微米(μm)以上80微米以下(μm)程度的)直径的导线也能应用。因此，本实施方式的导线接合处理不仅可应用于使用直径较粗的导线的功率半导体的制造，而且也可应用于使用直径较细的导线的闪速存储器等半导体装置的制造。
1.4变化例 此外，所述实施方式能进行各种变化。
所述实施方式中，对导线40在该导线40的第1端及第2端这2点进行楔形接合的情况进行了说明，但并不限于此。例如，导线除了1条导线的第1端及第2端以外，也可在该第1端及第2端之间的至少1个部分再进行楔形接合。以下的说明中，对于与所述实施方式相同的构成及制造方法省略说明，主要对与所述实施方式不同的构成及制造方法进行说明。
1.4.1半导体装置的构成 图6是变化例的半导体装置的剖视图。
如图6所示，半导体装置1A具备半导体衬底10、多个半导体芯片20-1、20-2、20-3、及20-4以及70、以及至少1条导线80。此外，图6中虽予以省略，但也可以还具备如图2所记载的引线端子，且半导体装置1A内的各芯片也可以与该引线端子以第1实施方式中所说明的形态经由未图示的导线而接合。
半导体芯片20-1设置在半导体衬底10的上表面上。半导体芯片20-2设置在半导体芯片20-1的上表面上。半导体芯片20-3设置在半导体芯片20-2的上表面上。半导体芯片20-4设置在半导体芯片20-3的上表面上。半导体芯片20-1～20-4例如具有相同的尺寸及性能。半导体芯片20-1～20-4中相邻的两个是以下方侧的半导体芯片的上表面的一部分不与上方侧的半导体芯片的下表面相接的方式相互错开积层。以下，将下方侧的半导体芯片的上表面中不与上方侧的半导体芯片的下表面相接的区域称为“阶台区域”。
半导体芯片20-1在半导体芯片20-1的阶台区域具有焊垫电极21-1。半导体芯片20-2在半导体芯片20-2的阶台区域具有焊垫电极21-2。半导体芯片20-3在半导体芯片20-3的阶台区域具有焊垫电极21-3。半导体芯片20-4在半导体芯片20-2的阶台区域具有焊垫电极21-4。
另外，半导体芯片70与半导体芯片20-1同样地设置在半导体衬底10的上表面上。在半导体芯片70的上表面上，设置着焊垫电极71。
在半导体衬底10上构成的多个半导体芯片20-1～20-4及70例如通过至少1条导线80而物理连接且电连接。在图6的示例中，导线80在第1端通过楔形接合而接合到焊垫电极21-4上，在第2端通过楔形接合而接合到焊垫电极71上。另外，导线80在第1端与第2端之间通过楔形接合而接合到焊垫电极21-2上，在第1端与和焊垫电极21-2的接合部之间通过楔形接合而接合到焊垫电极21-3上，在第2端与焊垫电极21-1之间通过楔形接合而接合到焊垫电极21-1上。
导线80具备与实施方式中的导线40相同的构成。即，导线80包含芯材81、及涂覆材82。芯材81例如是包含选自铜(Cu)、金(Au)、银(Ag)、及铝(Al)中的至少1种金属的导电体，且具有作为焊垫电极21-1～21-4及71间的通信路径的功能。
涂覆材82例如是包含钯(Pd)的导电体，通过被覆芯材81的外周而抑制芯材81与导线80的外部相接。因此，导线80中与该导线80的外部相接的部分是涂覆材82，芯材81是除导线80的切断面以外不与该导线80的外部相接(分离)。
所述半导体衬底10上的各构成由绝缘体50密封。
1.4.2半导体装置的制造方法图7是用来说明变化例的半导体装置的导线接合处理的流程图。此外，设定在焊针60且成为导线80的材料的导线在图7中记作包含芯材81'、及被覆该芯材81'的涂覆材82'的导线80'。
如图7所示，步骤ST21中，将导线80'设定在焊针60。
步骤ST22中，接合装置将变量i设定为“4”。此外，该变量i与图6的构成相对应，能够适当设定为任意值。
步骤ST23中，接合装置控制焊针60，将焊针60前端的导线80'的涂覆材82'与焊垫电极21-i(即，焊垫电极21-4)接合。
步骤ST24中，接合装置判定变量i是否为“1”。在变量i不为“1”的情况下(步骤ST24；否)，处理进入步骤ST25，在变量i为“1”的情况下(步骤ST24；是)，处理进入步骤ST27。
步骤ST25中，接合装置一面将导线80'从焊针60的前端卷出一面使焊针60从焊垫电极21-i的上方移动到焊垫电极21-(i-1)的上方。由此，导线80'中，接合到焊垫电极21-i的部分、与焊针60前端之间的部分在焊垫电极21-i与焊垫电极21-(i-1)之间构成环路。
步骤ST26中，接合装置使变量i递减之后，处理返回到步骤ST23。由此，一面使变量i递减一面反复进行导线80'与焊垫电极21-i接合的处理，直到步骤ST24中判定变量i为“1”为止。
步骤ST27中，接合装置一面将导线80'从焊针60的前端卷出一面使焊针60从焊垫电极21-1的上方移动到焊垫电极71的上方。由此，导线80'中，接合到焊垫电极21-1的部分、与焊针60前端之间的部分在焊垫电极21-1与焊垫电极71之间构成环路。
步骤ST28中，接合装置控制焊针60，将焊针60前端的导线80'的涂覆材42'与焊垫电极71接合。
步骤ST29中，接合装置控制焊针60，将导线80'在接合到焊垫电极71的部分与焊针60的前端之间切断。由此，形成对于焊垫电极21-1～21-4及71均通过楔形接合而接合的导线80。
通过以上操作，导线接合处理结束。
1.4.3本变化例的效果 根据本变化例，导线80在第1端接合到焊垫电极21-4上，在第2端接合到焊垫电极71上，并且在第1端与第2端之间，进而接合到焊垫电极21-1～21-3上。而且，与焊垫电极21-1～21-4及71的接合部均通过楔形接合而形成。由此，所有焊垫电极21-1～21-4及71并未与芯材81相接，而是与涂覆材82相接。因此，可发挥与所述实施方式相同的效果，并且可利用1根导线80将3点以上的焊垫电极21-1～21-4及71电连接。
1.4.4应用例 将所述实施方式及变化例的应用例示于图8。
图8是表示应用例的半导体装置的构成的框图。图8中，作为变化例的应用例，示出包含对应于半导体芯片20-1～20-4的多个存储器芯片、及对应于半导体芯片70的控制器芯片的存储器系统。存储器系统对应于图6中的半导体装置1A。
如图8所示，控制器芯片70控制存储器芯片20-1～20-4。具体而言，控制器芯片70将数据写入到存储器芯片20-1～20-4中，且从存储器芯片20-1～20-4中读出数据。控制器芯片70通过NAND(Not AND，与非)总线而连接于存储器芯片20-1～20-4。
存储器芯片20-1～20-4分别具备多个存储单元，将数据非易失地存储。存储器芯片20-1～20-4分别是例如能够根据预先分配的芯片地址而唯一识别的半导体芯片，构成为根据控制器芯片70的指示能够独立地或相互同步地动作。
分别与存储器芯片20-1～20-4连接的NAND总线上，收发同种信号。NAND总线包含多条信号线，进行与NAND接口相符的信号/CE0～/CE3、CLE、ALE、/WE、RE、/RE、/WP、/RB0～/RB3、DQ＜7:0＞、DQS、及/DQS的收发。信号CLE、ALE、/WE、RE、/RE、及/WP由存储器芯片20-1～20-4接收，信号/RB0～/RB3由控制器芯片70接收。另外，信号/CE0～/CE3分别由存储器芯片20-1～20-4接收。
信号/CE0～/CE3分别是用来激活存储器芯片20-1～20-4的信号。信号CLE将信号CLE为“H(高)”电平期间在存储器芯片20-1～20-4中流通的信号DQ＜7:0＞为指令的信息通知给存储器芯片20-1～20-4。信号ALE将信号ALE为“H”电平期间在存储器芯片20-1～20-4中流通的信号DQ＜7:0＞为地址的信息通知给存储器芯片20-1～20-4。信号/WE指示将信号/WE为“L(低)”电平期间在存储器芯片20-1～20-4中流通的信号DQ＜7:0＞取入到存储器芯片20-1～20-4。信号RE及/RE指示将信号DQ＜7:0＞输出到存储器芯片20-1～20-4，例如，用来控制当输出信号DQ＜7:0＞时的存储器芯片20-1～20-4的动作时序。信号/WP对存储器芯片20-1～20-4指示禁止数据写入及删除。信号/RB0～/RB3分别表示存储器芯片20-1～20-4为就绪状态(受理来自外部的命令的状态)还是为忙碌状态(不受理来自外部的命令的状态)。信号DQ＜7:0＞例如为8比特的信号。信号DQ＜7:0＞是在存储器芯片20-1～20-4与控制器芯片70之间收发的数据的实体，包含指令、地址、及数据。信号DQS及/DQS例如可基于信号RE及/RE而产生，用来控制有关信号DQ＜7:0＞的存储器芯片20-1～20-4的动作时序。
所述应用例中，信号CLE、ALE、/WE、RE、/WP、DQ＜7:0＞、DQS、及/DQS将存储器芯片20-1～20-4及控制器芯片70全部共通连接，所以可通过实施方式的导线40实现。另外，其它信号/CE0～/CE3及/RB0～/RB3分别将存储器芯片20-1～20-4与控制器芯片70之间连接，所以可通过变化例的导线80实现。
对本发明的若干实施方式进行了说明，但这些实施方式是作为示例而提出的，并非意图限定发明的范围。这些新颖的实施方式能以其它各种形态实施，且能够在不脱离发明主旨的范围内进行各种省略、替换、变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。

Claims (17)

1.一种半导体装置，具备：
第1电极；
第2电极；以及
导线，在所述第1电极与所述第2电极之间延伸；且
所述导线包含：
第1导电体，与所述第1电极及所述第2电极相接；以及
第2导电体，以不与所述第1电极及所述第2电极相接的方式设置在所述第1导电体内。
2.根据权利要求1所述的半导体装置，其中所述第1导电体包含钯(Pd)。
3.根据权利要求1所述的半导体装置，其中所述第2导电体包含选自铜(Cu)、金(Au)、银(Ag)、及铝(Al)中的至少1种金属。
4.根据权利要求1所述的半导体装置，其具备设置着所述第1电极的配线衬底。
5.根据权利要求1所述的半导体装置，其具备设置着所述第2电极的第1半导体芯片。
6.根据权利要求5所述的半导体装置，其还具备第2半导体芯片，所述第2半导体芯片设置在所述第1半导体芯片上，且形成着第3电极，
所述导线在所述第2电极与所述第3电极之间延伸，
所述第2导电体不与所述第3电极相接。
7.根据权利要求5或6所述的半导体装置，其中所述第1半导体芯片是存储器件、集成电路、分立半导体、或LED(Light emitting diode)。
8.根据权利要求5或6所述的半导体装置，其中所述第1半导体芯片是功率半导体。
9.根据权利要求1至6中任一项所述的半导体装置，其中所述导线具有与所述第1电极相接的第1部分、与所述第2电极相接的第2部分、以及所述第1部分及所述第2部分之间的第3部分，
所述导线的所述第1部分的直径是所述导线的所述第2部分或所述第3部分的直径的1/5以上1/2以下。
10.根据权利要求1至6中任一项所述的半导体装置，其中所述导线具有100微米(μm)以上500微米(μm)以下的直径。
11.根据权利要求1至6中任一项所述的半导体装置，其中所述导线具有15微米(μm)以上80微米(μm)以下的直径。
12.一种半导体装置，具备：
配线衬底，设置着第1电极；
第1半导体芯片，设置着第2电极；
第2半导体芯片，设置在所述第1半导体芯片上，且设置着第3电极；以及
导线，在所述第1电极、所述第2电极及所述第3电极之间延伸；且
所述导线包含：
第1导电体，与所述第1电极、所述第2电极及所述第3电极相接；以及
第2导电体，以不与所述第1电极、所述第2电极及所述第3电极相接的方式设置在所述第1导电体内；且
所述第1导电体包含钯(Pd)，
所述第2导电体包含选自铜(Cu)、金(Au)、银(Ag)、及铝(Al)中的至少1种金属。
13.根据权利要求12所述的半导体装置，其中所述第1半导体芯片是存储器件、集成电路、分立半导体、或LED(Light emitting diode)。
14.根据权利要求12所述的半导体装置，其中所述第1半导体芯片是功率半导体。
15.根据权利要求12所述的半导体装置，其中所述导线具有与所述第1电极相接的第1部分、与所述第2电极相接的第2部分、以及所述第1部分及所述第2部分之间的第3部分，
所述导线的所述第1部分的直径是所述导线的所述第2部分或所述第3部分的直径的1/5以上1/2以下。
16.根据权利要求12所述的半导体装置，其中所述导线具有100微米(μm)以上500微米(μm)以下的直径。
17.根据权利要求12所述的半导体装置，其中所述导线具有15微米(μm)以上80微米(μm)以下的直径。
CN202011409949.9A 2020-01-07 2020-12-04 半导体装置 Pending CN113161316A (zh)

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