CN113140547A - 半导体装置及裂纹检测方法 - Google Patents

半导体装置及裂纹检测方法 Download PDF

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CN113140547A
CN113140547A CN202110053705.XA CN202110053705A CN113140547A CN 113140547 A CN113140547 A CN 113140547A CN 202110053705 A CN202110053705 A CN 202110053705A CN 113140547 A CN113140547 A CN 113140547A
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electrode
semiconductor device
trench
insulating film
semiconductor
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CN113140547B (zh
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高野和豊
中村浩之
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Mitsubishi Electric Corp
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Abstract

本发明涉及半导体装置及裂纹检测方法。提供一种能够高精度地对裂纹的发展状况进行检测的半导体装置。半导体装置(100)是使用半导体基板(1)形成的，具有形成有半导体元件的有源区域(10)以及有源区域(10)的外侧的边缘终止区域(20)。在半导体基板(1)的边缘终止区域(20)形成有裂纹检测构造体(30)。裂纹检测构造体(30)具有：沟槽(31)，其形成于半导体基板(1)，在边缘终止区域(20)的周向延伸；内壁绝缘膜(32)，其形成于沟槽(31)的内壁；埋入电极(33)，其形成于内壁绝缘膜(32)之上，埋入至沟槽(31)；以及监视电极(34)，其形成于半导体基板(1)之上，与埋入电极(33)连接。

Description

半导体装置及裂纹检测方法
技术领域
本发明涉及半导体装置，特别涉及对在半导体装置产生的裂纹进行检测的技术。
背景技术
应功率器件的节能化以及小型化这样的市场要求，正在推进以降低实际使用功率器件时的损耗为目的的晶片的薄化。如果使晶片变薄，则虽然会带来电气特性的改善，但出现晶片的处理变得困难或者半导体装置的制造所涉及的各种处理受到限制等量产性的课题。特别是，在从晶片切出各个芯片的切割工序中，由于通过金刚石切割器等物理地切断晶片，因此由晶片之上的异物、切割器的缺损、晶片的翘曲、晶片的表面状态等各种要因导致在晶片的切割线部产生裂纹、缺损等(下面统称为“裂纹”)。为了防止裂纹的产生，通过小团队活动等改善活动而日复一日地进行进行晶片工艺的改善。
关于防止产生了裂纹的芯片的流出，如果是具有能够通过基于电气特性测定进行的测试、目视检查来判别的程度的大裂纹的芯片，则基本能可靠地剔除。但是，具有不影响电气特性且即使进行目视检查也难以判别的微细裂纹的芯片有可能向后续工序流出。即使具有微细裂纹的芯片流出，在大部分情况下，在后续工序中也不会产生任何影响，但有时偶尔会产生由组装引起的应力、由实际使用时的严酷环境(热、物理力)引起的应力等，使裂纹发展。因此，谋求能够高精度地对在芯片产生的裂纹的发展状况进行监视的技术。
例如，在下述专利文献1中公开了如下技术，即，在芯片的有效区域(半导体元件的形成区域)的周围，使在半导体层形成的扩散层或者直接埋入至半导体层的电极作为裂纹检测用配线而延伸，使用与扩散层或者电极连接的2个焊盘对扩散层或者电极的电阻值进行测定，由此对芯片有无裂纹进行判定。
专利文献1：日本特开2015-167207号公报
在专利文献1的技术中，由于基于裂纹检测用配线(扩散层或者电极)的电阻值对有无裂纹进行判定，因此，如果裂纹没有以裂纹检测用配线的电阻值大幅变化的程度大幅切入至该配线，则无法检测到裂纹。因此，专利文献1的技术难以高精度地对裂纹的发展状况进行检测。
发明内容
本发明是为了解决以上那样的课题而提出的，其目的在于提供一种能够高精度地对裂纹的发展状况进行检测的半导体装置。
本发明所涉及的半导体装置具有：半导体层，其具有形成有半导体元件的有源区域以及所述有源区域的外侧的边缘终止区域；以及裂纹检测构造体，其形成于所述边缘终止区域，所述裂纹检测构造体具有：沟槽，其形成于所述半导体层，在所述边缘终止区域的周向延伸；
内壁绝缘膜，其形成于所述沟槽的内壁；埋入电极，其形成于所述内壁绝缘膜之上，埋入至所述沟槽；以及监视电极，其形成于所述半导体层之上，与所述埋入电极连接。
发明的效果
根据本发明所涉及的半导体装置，能够通过对监视电极与其它电极之间的漏电流或者电位差进行测定，从而对裂纹的发展状况进行监视。只要裂纹到达裂纹检测构造体，漏电流或者电位差就会大幅变化，因此能够高精度地对裂纹的发展状况进行检测。
附图说明
图1是表示实施方式1所涉及的半导体装置的结构的剖面图。
图2是表示实施方式1所涉及的半导体装置的裂纹的监视方法的一个例子的图。
图3是表示实施方式1所涉及的半导体装置的裂纹的监视方法的一个例子的图。
图4是表示实施方式2所涉及的半导体装置的结构的剖面图。
图5是表示实施方式3所涉及的半导体装置的结构的剖面图。
图6是表示实施方式3所涉及的半导体装置的结构的剖面图。
图7是表示实施方式4所涉及的半导体装置的结构的剖面图。
图8是表示实施方式5所涉及的半导体装置的结构的剖面图。
具体实施方式
<实施方式1>
图1是表示实施方式1所涉及的半导体装置100的结构的剖面图。在本实施方式中，半导体装置100所具有的半导体元件是绝缘栅极型、更具体而言是沟槽栅极型的IGBT(Insulated Gate Bipolar Transistor)。但是，半导体元件也可以是例如MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)、二极管等IGBT以外的元件。另外，IGBT、MOSFET也可以是平面栅极型。另外，下面将第1导电型设为N型、将第2导电型设为P型进行说明，但也可以与此相反，将第1导电型设为P型、将第2导电型设为N型。
半导体装置100使用作为半导体层的半导体基板1而形成。这里，将半导体基板1的材料设为硅，但半导体基板1也可以由硅以外的材料，例如SiC、GaN等宽带隙半导体等形成。在使用了宽带隙半导体作为半导体基板1的材料的情况下，与使用了硅的情况相比，能够得到高电压、大电流、高温下的动作优异的半导体装置100。
如图1所示，半导体基板1包含：第1导电型的N型漂移层2，其形成于上表面侧的表层部；第1导电型的N型缓冲层3，其形成于N型漂移层2之下，杂质的峰值浓度高于N型漂移层2；以及第2导电型的P型集电极层4，其形成于下表面侧的表层部。N型缓冲层3介于N型漂移层2与P型集电极层4之间。另外，在半导体基板1的下表面形成有IGBT的集电极电极(collector electrode)5。
半导体装置100具有形成半导体元件(IGBT)的有源区域10、和在有源区域10的外侧设置的边缘终止区域20。边缘终止区域20是包围有源区域10的环状的区域。
首先，说明有源区域10的结构。在有源区域10，在N型漂移层2的表层部形成有第2导电型的P－型基极层11。另外，在半导体基板1的上表面形成有栅极沟槽12，该栅极沟槽12到达P－型基极层11之下的N型漂移层2。在栅极沟槽12的内壁(侧面以及底面)，形成有例如由氧化硅膜构成的IGBT的栅极绝缘膜13。在栅极绝缘膜13之上，以埋入至栅极沟槽12的方式形成有由例如多晶硅、铝等金属构成的IGBT的栅极电极14。另外，在P－型基极层11的表层部，以与栅极沟槽12相邻的方式形成有第1导电型的N+型源极区域15。栅极电极14隔着栅极绝缘膜13与N+型源极区域15、P－型基极层11以及N型漂移层2相对。
在半导体基板1之上以覆盖栅极电极14的方式形成有层间绝缘膜6，在层间绝缘膜6之上形成有发射极电极16。在层间绝缘膜6形成有到达N+型源极区域15以及P－型基极层11的接触孔，发射极电极16穿过接触孔与N+型源极区域15以及P－型基极层11连接。
接着，说明边缘终止区域20的结构。在边缘终止区域20，在N型漂移层2的表层部形成有将P－型基极层11的外侧包围且杂质的峰值浓度高于P－型基极层11的第2导电型(P型)的FLR(Field Limiting Ring)21。FLR 21也被层间绝缘膜6覆盖，在该层间绝缘膜6之上形成有穿过接触孔而与FLR 21连接的FLR电极22。另外，以将FLR 21的外侧包围的方式，在N型漂移层2的表层部形成有第1导电型(N型)的沟道阻止层23，该沟道阻止层23的杂质的峰值浓度高于N型漂移层2。沟道阻止层23也被层间绝缘膜6覆盖，在该层间绝缘膜6之上形成有穿过接触孔而与沟道阻止层23连接的沟道阻止电极24。
就实施方式1的半导体装置100而言，在边缘终止区域20，以将沟道阻止电极24的外侧包围的方式具有用于检测裂纹的配线构造即裂纹检测构造体30。裂纹检测构造体30具有：沟槽31，其形成于半导体基板1的N型漂移层2内，在边缘终止区域20的周向延伸；内壁绝缘膜32，其形成于沟槽31的内壁(侧面以及底面)；埋入电极33，其形成于内壁绝缘膜32之上，埋入至沟槽31；以及监视电极34，其形成于半导体基板1之上，与埋入电极33连接。
此外，在图1的剖面中，层间绝缘膜6介于监视电极34与埋入电极33之间，但是监视电极34与埋入电极33在未图示的区域，穿过在层间绝缘膜6形成的接触孔而连接。使监视电极34与埋入电极33连接的区域的位置没有限制，例如，可以配置于容易产生无效区域的芯片的角部。在该情况下，在芯片的除了角部以外的部分，能够使监视电极34的宽度变窄而减少无效区域。
另外，在半导体装置100的上表面，形成有玻璃涂层7作为保护膜。为了能够将导线等连接于发射极电极16，在玻璃涂层7形成有使发射极电极16的上表面露出的开口。另外，在玻璃涂层7，在未图示的区域(例如芯片的角部)还具有使监视电极34的上表面露出的开口，能够将导线连接于监视电极34或者使测定针抵接于监视电极34。
在实施方式1中，使沟槽31的深度与栅极沟槽12的深度相同，内壁绝缘膜32的厚度以及材料与栅极绝缘膜13的厚度以及材料(例如，氧化硅膜)相同，埋入电极33的材料与栅极电极14的材料(例如，多晶硅、铝等金属)相同。在该情况下，沟槽31、内壁绝缘膜32、埋入电极33能够分别在与栅极沟槽12、栅极绝缘膜13以及栅极电极14相同的工序中形成，因此能够抑制由于在半导体装置100设置裂纹检测构造体30而导致的制造工序数的增加。
半导体装置100的裂纹的发展状况的监视能够通过对监视电极34与其它电极之间的漏电流或者电位差进行监视来进行。这里所说的“其它电极”例如可以是发射极电极16、集电极电极5、FLR电极22、沟道阻止电极24的任意者。另外，在半导体装置100具有多个裂纹检测构造体30的情况下，也可以通过对2个监视电极34之间的漏电流或者电位差进行监视，从而进行裂纹的发展状况的监视。在该情况下，2个监视电极34中的一方是“其它电极”。
在基于监视电极34与其它电极之间的漏电流进行裂纹的监视的情况下，如果裂纹没有到达裂纹检测构造体30，则漏电流仅是内壁绝缘膜32的漏电流，因此是小于或等于pA的数量级，但是如果裂纹到达裂纹检测构造体30，则内壁绝缘膜32的绝缘被破坏，漏电流跨越式地上升至大于或等于nA的数量级。这样，即使裂纹没有大幅切入至裂纹检测构造体30，只要裂纹到达裂纹检测构造体30，漏电流就会大幅变化，因此能够高精度地对裂纹的发展状况进行判定。
在基于监视电极34与其它电极之间的电位差而进行裂纹的监视的情况下，如果裂纹没有到达裂纹检测构造体30，则监视电极34与其它电极之间为开路状态(能够施加几V至几十V的电压的状态)，但如果裂纹到达裂纹检测构造体30，则成为短路状态(仅能施加小于或等于1V的电压的状态)。这样，即使裂纹没有大幅切入至裂纹检测构造体30，只要裂纹到达裂纹检测构造体30，电位差就会发生大幅变化，因此能够高精度地对裂纹的发展状况进行判定。
基本上，只要半导体装置100处于切割后的芯片的状态，就能够进行裂纹的监视。例如，如图2所示，即使在通过切割而从晶片切分出的多个半导体装置100载置于在切割环42安装的切割带43之上的状态下，也能够通过使测定针41分别与各个半导体装置100的监视电极34和其它电极接触，对漏电流或者电位差进行测定，由此对裂纹进行监视。在该情况下，能够确认有无由于切割而产生的裂纹。
另外，例如，如图3所示，即使在半导体装置100被组装至半导体模块50之后，也能够进行裂纹的监视。图3的半导体模块50具有：半导体装置100；裂纹检测用外部电极53，其经由由铝、金等构成的导线52而与半导体装置100的监视电极34连接；发射极外部电极56，其经由导线51而与半导体装置100的发射极电极16连接；以及集电极外部电极54，其与半导体装置100的集电极电极5连接，该半导体模块50具有使用模塑树脂55对包含半导体装置100、发射极外部电极56、集电极外部电极54在内的半导体模块50的结构要素进行了封装的构造。
例如，能够通过对裂纹检测用外部电极53与集电极外部电极54之间的漏电流或电位差、或者裂纹检测用外部电极53与发射极外部电极56之间的漏电流或者电位差进行测定，从而对裂纹进行监视。在该情况下，能够对由于来自半导体模块50的封装体的应力而导致的半导体装置100的裂纹的发展进行检测。
另外，例如，在半导体模块50的实际使用时的定期检查中，通过上述方法对半导体装置100的裂纹进行监视，还能够检测由实际使用时产生的热应力而引起的裂纹的发展。在该情况下，能够在半导体装置100由于裂纹而导致破坏之前，进行更换半导体模块50等维护。
此外，在图3中，作为半导体模块50的外部电极，示出了裂纹检测用外部电极53、集电极外部电极54以及发射极外部电极56这3个，但半导体模块50也可以还具有与半导体装置100的沟道阻止电极24、FLR电极22等连接的外部电极。半导体装置100的裂纹的监视能够通过对裂纹检测用外部电极53与其它任意的外部电极之间的漏电流或者电位差进行测定来进行。
<实施方式2>
图4是表示实施方式2所涉及的半导体装置100的结构的剖面图。图4中放大表示了半导体装置100的剖面的右侧一半。另外，在图4中，对与图1所示的要素相同的要素标注与其相同的标号，因此这里省略它们的说明。
就实施方式2的半导体装置100而言，在裂纹检测构造体30的内壁绝缘膜32之上，层叠了由例如氧化硅膜构成的追加内壁绝缘膜32a。因此，内壁绝缘膜32的实际厚度(包含追加内壁绝缘膜32a的厚度)大于栅极绝缘膜13的厚度。在实施方式2的以下的说明中，“内壁绝缘膜32的厚度”表示包含追加内壁绝缘膜32a的厚度。
追加内壁绝缘膜32a能够通过例如在沟槽31的内壁形成热氧化膜而作为内壁绝缘膜32之后，在该热氧化膜之上沉积氧化膜而形成。此时，如果沟槽31被追加内壁绝缘膜32a填满，则不能在沟槽31内形成埋入电极33，因此为了避免上述情况，沟槽31的尺寸需要大于追加内壁绝缘膜32a的厚度的2倍。
就实施方式2的半导体装置100而言，通过将内壁绝缘膜32的厚度设得厚，能够防止由于除了裂纹以外的原因、例如实际动作时在集电极电极5与发射极电极16之间施加的电压等而导致内壁绝缘膜32被破坏。
<实施方式3>
图5是表示实施方式3所涉及的半导体装置100的结构的剖面图。在图5中，也放大表示了半导体装置100的剖面的右侧一半。另外，在图5中，对与图1所示的要素相同的要素标注与其相同的标号，因此这里省略它们的说明。
就实施方式3的半导体装置100而言，裂纹检测构造体30的沟槽31形成于N型漂移层2内，但在沟槽31的附近形成有将沟槽31的周围覆盖的第2导电型的P型区域36。通过在沟槽31的周围形成由N型漂移层2与P型区域36形成的PN结，从而能够降低在向集电极电极5与发射极电极16之间施加了电压时施加于内壁绝缘膜32的电压，能够降低在内壁绝缘膜32产生的电场强度。由此，能够防止在实际动作时因在集电极电极5与发射极电极16之间施加的电压而导致内壁绝缘膜32被破坏。
此外，特别是在沟槽31的底部附近容易产生电场的集中，因此，只要P型区域36至少形成于沟槽31的底部的周围，就能够得到充分的效果。因此，例如，如图6所示，P型区域36也可以仅形成于沟槽31的底部的周围。
<实施方式4>
图7是表示实施方式4所涉及的半导体装置100的结构的剖面图。在图7中，也放大表示了半导体装置100的剖面的右侧一半。另外，在图7中，对与图1所示的要素相同的要素标注与其相同的标号，因此这里省略它们的说明。
就实施方式4的半导体装置100而言，将裂纹检测构造体30的沟槽31的深度设得比栅极沟槽12的深度深。通过对沟槽31进行加深，能够提高裂纹的检测灵敏度。
<实施方式5>
图8是表示实施方式5所涉及的半导体装置100的结构的剖面图。在图8中，也放大表示了半导体装置100的剖面的右侧一半。另外，在图8中，对与图1所示的要素相同的要素标注与其相同的标号，因此这里省略它们的说明。
就实施方式5的半导体装置100而言，将裂纹检测构造体30的沟槽31的宽度设得比栅极沟槽12的宽度宽。通过对沟槽31的宽度进行加宽，埋入电极33的材料的埋入变得容易。
此外，能够自由地对各实施方式进行组合，或者适当地对各实施方式进行变形、省略。
标号的说明
1半导体基板，2N型漂移层，3N型缓冲层，4P型集电极层，5集电极电极，6层间绝缘膜，7玻璃涂层，10有源区域，11P－型基极层，12栅极沟槽，13栅极绝缘膜，14栅极电极，15N+型源极区域，16发射极电极，20边缘终止区域，21FLR，22FLR电极，23沟道阻止层，24沟道阻止电极，30裂纹检测构造体，31沟槽，32内壁绝缘膜，32a追加内壁绝缘膜，33埋入电极，34监视电极，36P型区域，41测定针，42切割环，43切割带，50半导体模块，51导线，52导线，53裂纹检测用外部电极，54集电极外部电极，55模塑树脂，56发射极外部电极，100半导体装置。

Claims (6)

1.一种半导体装置，其具有：
半导体层，其具有形成有半导体元件的有源区域以及所述有源区域的外侧的边缘终止区域；以及
裂纹检测构造体，其形成于所述边缘终止区域，
所述裂纹检测构造体具有：
沟槽，其形成于所述半导体层，在所述边缘终止区域的周向延伸；
内壁绝缘膜，其形成于所述沟槽的内壁；
埋入电极，其形成于所述内壁绝缘膜之上，埋入至所述沟槽；以及
监视电极，其形成于所述半导体层之上，与所述埋入电极连接。
2.根据权利要求1所述的半导体装置，其中，
所述半导体元件是具有栅极绝缘膜以及栅极电极的绝缘栅极型的半导体元件，
所述裂纹检测构造体的所述内壁绝缘膜的厚度厚于所述半导体元件的所述栅极绝缘膜的厚度。
3.根据权利要求1或2所述的半导体装置，其中，
所述裂纹检测构造体的所述沟槽形成于所述半导体层的第1导电型的漂移层内，
在所述漂移层的所述沟槽的周围形成有至少将所述沟槽的底部的周围覆盖的第2导电型的区域。
4.根据权利要求1至3中任一项所述的半导体装置，其中，
所述半导体元件是具有栅极绝缘膜以及栅极电极的沟槽栅极型的半导体元件，该栅极绝缘膜以及栅极电极埋入至在所述半导体层形成的沟槽，
所述裂纹检测构造体的所述沟槽的深度深于所述半导体元件的所述沟槽的深度。
5.根据权利要求1至4中任一项所述的半导体装置，其中，
所述半导体元件是具有栅极绝缘膜以及栅极电极的沟槽栅极型的半导体元件，该栅极绝缘膜以及栅极电极埋入至在所述半导体层形成的沟槽，
所述裂纹检测构造体的所述沟槽的宽度宽于所述半导体元件的所述沟槽的宽度。
6.一种裂纹检测方法，其是权利要求1至5中任一项所述的半导体装置的裂纹检测方法，其中，
对所述裂纹检测构造体的所述监视电极与所述半导体装置所具有的其它电极之间的漏电流或者电位差进行测定，
基于测定出的所述漏电流或者所述电位差的值对所述半导体装置有无裂纹进行判定。
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