CN113066851A - 一种InAlGaN/GaN异质结结构及其生长方法 - Google Patents

一种InAlGaN/GaN异质结结构及其生长方法 Download PDF

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CN113066851A
CN113066851A CN202110256600.4A CN202110256600A CN113066851A CN 113066851 A CN113066851 A CN 113066851A CN 202110256600 A CN202110256600 A CN 202110256600A CN 113066851 A CN113066851 A CN 113066851A
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张源涛
秦维泉
邓高强
董鑫
张宝林
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Abstract

一种InAlGaN/GaN异质结结构及其生长方法,属于半导体材料外延生长技术领域。采用MOCVD方法在衬底层上依次外延生长GaN沟道层和InAlGaN势垒层,通过控制生长条件生长In:Al组分比约为1:5的InAlGaN势垒层,使InAlGaN势垒层与GaN沟道层实现a轴晶格匹配。本发明方法可以获得a轴晶格匹配的InAlGaN/GaN异质结,消除势垒层与沟道层之间的晶格失配,可以解决目前高Al组分AlGaN/GaN基电子器件中由于晶格失配而导致的结晶质量下降问题,可显著降低强电场下短沟道电子器件的逆压电极化效应,能够实现具有高密度二维电子气和高电导特性的无应变异质结结构。

Description

一种InAlGaN/GaN异质结结构及其生长方法
技术领域
本发明属于半导体材料外延生长技术领域,具体涉及一种InAlGaN/GaN异质结结构及其生长方法。
背景技术
GaN作为一种宽禁带的直接带隙半导体材料,室温下禁带宽度约为3.39eV,具有击穿电压高、电子饱和速度高、热导率高、介电常数低、化学稳定性好等特点。因此GaN有着非常广泛的应用,在大功率电子器件尤其高频微波器件应用方面有着广阔的前景。
GaN基电子器件的研究大多基于AlGaN/GaN异质结,这是由于AlGaN/GaN异质结具有很强的自发极化和压电极化效应,在AlGaN势垒层非故意掺杂的情况下就能形成高迁移率、高密度的二维电子气(2DEG),正是AlGaN/GaN异质结2DEG沟道的高电导能力为GaN电子器件提供了基础。
为了使GaN基电子器件达到更高的工作频率,如毫米波频段甚至太赫兹频段,要求器件的沟道长度必须足够短,这时器件的短沟道效应将成为一个重要的问题。为了克服短沟道效应对器件的影响,需要减薄AlGaN势垒层厚度,但同时还要保持高的异质结沟道电导特性,就必须增大势垒层Al组分,增强自发极化和压电极化效应以维持高2DEG密度。然而,高Al组分AlGaN和GaN的晶格失配增大,AlGaN势垒层受到GaN的张应变增加,会导致异质结界面粗糙度增加以及AlGaN势垒层结晶质量下降,降低2DEG面密度和迁移率,同时高Al组分AlGaN的绝缘性增加,欧姆接触电阻将会增大。另外,器件处于工作状态时,在靠近漏极的栅下方存在大的电场,在AlGaN势垒层的很小区域内产生大的应力,处于晶格失配状态的AlGaN势垒层会发生逆压电效应,导致在其内部形成晶体缺陷,严重影响高频毫米波器件的工作性能和可靠性。
发明内容
本发明提出了一种InAlGaN/GaN异质结结构及其生长方法,该结构采用四元InAlGaN材料作为势垒层,InAlGaN材料在In:Al组分比约为1:5时可实现与GaN材料a轴晶格常数匹配,在晶格匹配的同时还可实现InAlGaN材料禁带宽度的改变,有利于调控InAlGaN/GaN异质结界面处2DEG密度,适用于高频氮化物电子器件的制备。
本发明由如下技术方案实现:
本发明所提出的一种InAlGaN/GaN异质结结构(见附图1),其从下至上依次由衬底层1、GaN沟道层2、InAlGaN势垒层3构成。其特征在于:该异质结结构的势垒层3是由与GaN沟道层2a轴晶格匹配的四元InxAlyGa1-x-yN(0<x<0.2,0<y<0.8)材料构成(见附图2)。
如上所述的一种InAlGaN/GaN异质结结构,其特征在于:GaN沟道层2厚度为1~5μm、InAlGaN势垒层3厚度为1~30nm。
如上所述的一种InAlGaN/GaN异质结结构,其特征在于:GaN沟道层2采用的是两步温度生长法制备,即首先在较低温度(500~900℃)生长一定厚度的的低温GaN层,然后升高温度(1000~1300℃)进行高温GaN层的外延生长,低温GaN层和高温GaN层共同构成GaN沟道层2。
如上所述的一种InAlGaN/GaN异质结结构,其特征在于:衬底层1可以为蓝宝石、SiC、Si、GaN、AlN或金刚石衬底。
一种如上所述的InAlGaN/GaN异质结结构的生长方法,其步骤如下:
采用MOCVD方法在衬底层1上首先外延生长GaN沟道层2,包括先在较低温度(500~900℃)外延生长厚度为10~100nm的低温GaN层,生长压力为200~600mbar,然后升高温度(1000~1300℃)继续外延生长厚度为1~5μm的高温GaN层,生长压力为200~600mbar,低温GaN层和高温GaN层共同构成了GaN沟道层2。之后降温至750~850℃外延生长厚度为1~30nm的InAlGaN势垒层3,生长压力为400~600mbar,生长源为三甲基镓(TMGa)、三甲基铟(TMIn)、三甲基铝(TMAl)及高纯氨气(NH3)。
本发明的效果和益处:本发明方法可以获得a轴晶格匹配的InAlGaN/GaN异质结,消除势垒层与沟道层之间的晶格失配,可以解决目前高Al组分AlGaN/GaN基电子器件中由于晶格失配而导致的结晶质量下降问题,可显著降低强电场下短沟道电子器件的逆压电极化效应,同时在InAlGaN势垒层和GaN沟道层的异质结界面处具有更大的导带带阶,能够实现具有高密度二维电子气和高电导特性的无应变异质结结构。因此,本发明提出的InAlGaN/GaN异质结结构,可用于高频GaN基电子器件的制备。
附图说明
图1:本发明所述InAlGaN/GaN异质结的外延结构示意图。
图2:本发明所述InAlGaN材料的a轴晶格常数与组分对应关系示意图。
图1中标识:1为衬底层、2为GaN沟道层、3为InAlGaN势垒层。
图2中颜色表示InAlGaN材料的a轴晶格常数数值,虚线表示In:Al组分比约为1:5时可与GaN晶格匹配的InAlGaN的a轴晶格常数。
具体实施方式
实施例1:
采用MOCVD方法,在(0001)面的蓝宝石衬底层1上首先外延生长厚度为20nm的低温GaN层,生长温度为550℃,生长压力为600mbar,生长源为三甲基镓(TMGa)和高纯氨气(NH3)。然后升温至1100℃,继续外延生长厚度为2μm的高温GaN层,生长压力为300mbar,使用在线原位反射率监测系统实时监控高温GaN层的厚度,低温GaN层和高温GaN层共同构成GaN沟道层2。之后降温至810℃,继续外延生长厚度为30nm的InAlGaN势垒层3,生长压力为600mbar,生长源为三甲基镓(TMGa)、三甲基铟(TMIn)、三甲基铝(TMAl)及高纯氨气(NH3)。各层具体生长参数见表1。
表1:InAlGaN/GaN异质结的外延结构各层生长参数
Figure BDA0002967633720000031
表1附注:TMGa代表三甲基镓;TMIn代表三甲基铟;TMAl代表三甲基铝;NH3代表高纯氨气。

Claims (5)

1.一种InAlGaN/GaN异质结结构,其特征在于:从下至上依次由衬底层(1)、GaN沟道层(2)、InAlGaN势垒层(3)构成,该异质结结构的势垒层(3)是由与GaN沟道层(2)a轴晶格匹配的四元InxAlyGa1-x-yN材料构成,0<x<0.2,0<y<0.8。
2.如权利要求1所述的一种InAlGaN/GaN异质结结构,其特征在于:该结构外延生长的GaN沟道层(2)的厚度为1~5μm,InAlGaN势垒层(3)的厚度为1~30nm。
3.如权利要求1所述的一种InAlGaN/GaN异质结结构,其特征在于:衬底层(1)为蓝宝石、SiC、Si、GaN、AlN或金刚石衬底。
4.权利要求1所述的一种InAlGaN/GaN异质结结构的生长方法,其特征在于:采用MOCVD方法在所述衬底层(1)上首先外延生长厚度为1~5μm的GaN沟道层(2),之后在GaN沟道层(2)上继续外延生长厚度为1~30nm的InAlGaN势垒层(3),生长源为三甲基镓(TMGa)、三甲基铟(TMIn)、三甲基铝(TMAl)及高纯氨气(NH3),生长温度为500~1300℃,生长压强为50~600mbar。
5.如权利要求4所述的一种InAlGaN/GaN异质结结构的生长方法,其特征在于:GaN沟道层(2)采用两步温度生长法制备,即首先在较低温度(500~900℃)外延生长厚度为10~100nm的低温GaN层,生长压力为600mbar,之后升高温度(1000~1300℃)继续外延生长厚度为1~5μm的高温GaN层,生长压力为300mbar,低温GaN层和高温GaN层共同构成GaN沟道层(2)。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009049288A (ja) * 2007-08-22 2009-03-05 Nec Corp 半導体装置
US20130168734A1 (en) * 2010-08-25 2013-07-04 Ngk Insulators, Ltd. Epitaxial substrate for semiconductor device, semiconductor device, method of manufacturing epitaxial substrate for semiconductor device, and method of manufacturing semiconductor device
CN104600108A (zh) * 2014-12-31 2015-05-06 中国电子科技集团公司第五十五研究所 一种氮化物高电子迁移率晶体管外延结构及其制备方法
US20180158926A1 (en) * 2016-12-05 2018-06-07 Sumitomo Electric Industries, Ltd. Process of forming semiconductor device
CN109962100A (zh) * 2019-04-03 2019-07-02 中国科学院微电子研究所 P型沟道GaN基结构及电子器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009049288A (ja) * 2007-08-22 2009-03-05 Nec Corp 半導体装置
US20130168734A1 (en) * 2010-08-25 2013-07-04 Ngk Insulators, Ltd. Epitaxial substrate for semiconductor device, semiconductor device, method of manufacturing epitaxial substrate for semiconductor device, and method of manufacturing semiconductor device
CN104600108A (zh) * 2014-12-31 2015-05-06 中国电子科技集团公司第五十五研究所 一种氮化物高电子迁移率晶体管外延结构及其制备方法
US20180158926A1 (en) * 2016-12-05 2018-06-07 Sumitomo Electric Industries, Ltd. Process of forming semiconductor device
CN109962100A (zh) * 2019-04-03 2019-07-02 中国科学院微电子研究所 P型沟道GaN基结构及电子器件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
邓高强: "SiC衬底上氮极性GaN薄膜的MOCVD生长及发光器件制备研究", 《中国优秀博硕士学位论文全文数据库(博士)信息科技辑》 *

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