CN113035932A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN113035932A
CN113035932A CN202010817443.5A CN202010817443A CN113035932A CN 113035932 A CN113035932 A CN 113035932A CN 202010817443 A CN202010817443 A CN 202010817443A CN 113035932 A CN113035932 A CN 113035932A
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semiconductor device
insulating member
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CN113035932B (zh
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篠原大辅
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Toshiba Electronic Devices and Storage Corp
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Abstract

实施方式提供能够兼顾高耐压与低接通电阻的半导体装置。实施方式的半导体装置具备在上表面形成有凹部的半导体部分、设于所述凹部内的一部分的绝缘部件、第一电极、以及比所述绝缘部件薄的栅极绝缘膜。所述第一电极具有设于所述凹部内的其他一部分的第一部分、以及设于比所述绝缘部件靠上方的位置的第二部分。所述栅极绝缘膜设于所述半导体部分与所述第一部分之间。所述半导体部分具有与所述栅极绝缘膜相接的第一导电型的第一层、以及与所述第一层相接并与源极触点及漏极触点连接的第二导电型的第二层和第三层。在从上方观察时，所述凹部位于所述源极触点与所述漏极触点之间。所述绝缘部件配置于所述第一部分与所述第三层之间。

Description

半导体装置
相关申请
本申请享受以日本专利申请2019－232931号(申请日：2019年12月24日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
实施方式涉及半导体装置。
背景技术
以往，作为电力控制用的开关元件，使用了DMOS(Diffused Metal-Oxide-Semiconductor Field-Effect Transistor，扩散金属氧化物半导体场效应晶体管)。在DMOS中，期望兼顾高耐压与低接通电阻。
发明内容
实施方式提供一种能够兼顾高耐压与低接通电阻的半导体装置。
实施方式的半导体装置具备：半导体部分，在上表面形成有凹部；绝缘部件，设于所述凹部内的一部分；第一电极；栅极绝缘膜，比所述绝缘部件薄；源极触点，设于所述半导体部分上；以及漏极触点，设于所述半导体部分上。所述第一电极具有：第一部分，设于所述凹部内的其他一部分；以及第二部分，设于比所述绝缘部件靠上方的位置。所述栅极绝缘膜设于所述半导体部分与所述第一部分之间。所述半导体部分具有：第一导电型的第一层，与所述栅极绝缘膜相接；第二导电型的第二层，与所述第一层相接并与所述源极触点连接；以及第二导电型的第三层，与所述第一层相接并与所述漏极触点连接。在从上方观察时，所述凹部位于所述源极触点与所述漏极触点之间。所述绝缘部件配置于所述第一部分与所述第三层之间。
附图说明
图1是表示第一实施方式的半导体装置的剖面图。
图2是表示第二实施方式的半导体装置的剖面图。
图3的(a)是表示第三实施方式的半导体装置的俯视图，(b)是其剖面图。
具体实施方式
＜第一实施方式＞
首先，对第一实施方式进行说明。
图1是表示本实施方式的半导体装置的剖面图。
另外，图1是示意性的，适当省略或者夸张了构成要素。对于后述的图2、图3的(a)以及(b)也是同样的。
如图1所示，在本实施方式的半导体装置1中设有硅基板10，在硅基板10上设有外延层11。外延层11是从硅基板10的上表面外延生长硅而形成的层，导电型例如为p型。
在外延层11上的一部分设有导电型为p型的p型阱12。p型阱12的杂质浓度比外延层11的杂质浓度高。在p型阱12上的一部分设有导电型为n型的源极层13。在源极层13上的一部分设有导电型为n+型的源极触点层14。源极触点层14的杂质浓度比源极层13的杂质浓度高。
在p型阱12上的其他一部分设有导电型为p型的主体层15。主体层15的杂质浓度比p型阱12的杂质浓度高。在主体层15上的一部分设有导电型为p+形的主体触点层16。主体触点层16的杂质浓度比主体层15的杂质浓度高。例如，主体层15与源极层13相接。
在外延层11上的其他一部分设有导电型为n型的漂移层17以及导电型为n型的n型阱18。n型阱18的杂质浓度比漂移层17的杂质浓度高。漂移层17与n型阱18彼此相接。在漂移层17上的一部分以及n型阱18上设有导电型为n型的漏极层19。漏极层19的杂质浓度比n型阱18的杂质浓度高。在漏极层19上的一部分设有导电型为n+型的漏极触点层20。漏极触点层20的杂质浓度比漏极层19的杂质浓度高。
通过硅基板10、外延层11、p型阱12、源极层13、源极触点层14、主体层15、主体触点层16、漂移层17、n型阱18、漏极层19、漏极触点层20，形成有半导体部分30。半导体部分30例如由单晶硅构成，在各部分导入有杂质。
通过半导体部分30中的外延层11、p型阱12、主体层15、主体触点层16，形成有导电型为p型的第一层31。通过半导体部分30中的源极层13以及源极触点层14，形成有导电型为n型的第二层32。通过半导体部分30中的漂移层17、n型阱18、漏极层19、漏极触点层20，形成有导电型为n型的第三层33。第二层32以及第三层33与第一层31相接，例如设于第一层31上。即，半导体部分30具有第一层31、第二层32、第三层33。
另外，外延层11的导电型也可以为n型。在该情况下，p型的第一层31包括p型阱12、主体层15、主体触点层16，n型的第二层32包括源极层13以及源极触点层14，n型的第三层33包括外延层11、漂移层17、n型阱18、漏极层19、漏极触点层20。在该情况下，第二层32以及第三层33也与第一层31相接。
在半导体部分30的上表面35形成有凹部36。在包含源极层13以及漏极层19的截面中，凹部36的形状为倒梯形形状，且为锥状。凹部36具有源极层13侧的侧面36s、漏极层19侧的侧面36d、底面36b。侧面36s以及侧面36d为锥状。另外，在与包含源极层13以及漏极层19的截面正交的截面、即沿着图1的纸面进深方向的截面中，凹部36的侧面并不限于锥状。底面36b位于侧面36s与侧面36d之间，并与侧面36s以及侧面36d相接。另外，将由侧面36s的上端与侧面36d的上端夹着的虚拟的平面设为凹部36的上表面36u。
源极层13在侧面36s的上部露出。p型阱12在从侧面36s的下部到底面36b的侧面36s侧的部分露出。漏极层19在侧面36d的上部露出。漂移层17在从侧面36d的下部到底面36b的侧面36d侧的部分露出。外延层11在底面36b中的p型阱12露出的部分与漂移层17露出部分之间露出。
在凹部36内的漏极层19侧的部分设有绝缘部件41。绝缘部件41例如由硅氧化物构成，例如通过以TEOS(Tetraethyl orthosilicate：Si(OC2H5)4)为原料的CVD(ChemicalVapor Deposition：化学气相沉积)法形成。
绝缘部件41的侧面41d与凹部36的侧面36d相同。绝缘部件41的底面41b与底面36b中的侧面36d侧的部分相同。绝缘部件41的侧面41d以及底面41b与第三层33相接。更详细地说，侧面41d的上部与漏极层19相接，侧面41d的下部以及底面41b与漂移层17相接。绝缘部件41的上表面41u与凹部36的上表面36u相同。绝缘部件41的侧面41d与上表面41u所成的角度θ1为锐角，例如为10度以上且85度以下。
从凹部36内的源极层13侧的部分到绝缘部件41上设有电极42。即，电极42具有配置于凹部36内的第一部分42a、以及配置于比绝缘部件41靠上方的位置的第二部分42b。第一部分42a配置于绝缘部件41与栅极绝缘膜43之间。第二部分42b配置于比第一部分42a靠上方的位置，具有设于凹部36的正上方区域的部分、以及朝向漏极层19延伸突出的部分。由此，第二部分42b的一部分与绝缘部件41的上表面41u相接。第一部分42a以及第二部分42b与绝缘部件41相接。另外，电极42也可以具有第一部分42a以及第二部分42b以外的部分。绝缘部件41配置于电极42的第一部分42a与第三层33之间。
在凹部36内的电极42的第一部分42a与半导体部分30之间设有栅极绝缘膜43。栅极绝缘膜43设于凹部36的源极层13侧的侧面36s的整体以及底面36b中的源极层13侧的部分。栅极绝缘膜43比绝缘部件41薄。在后述的源极－栅极间的电位差为5V的情况下，栅极绝缘膜43的厚度例如为10～15nm。栅极绝缘膜43例如由硅氧化物构成，例如对半导体部分30进行热氧化而形成。栅极绝缘膜43的表面与凹部36的上表面36u所成的角度θ2为锐角，例如为10度以上且85度以下。栅极绝缘膜43可以与绝缘部件41一体地设置，也可以作为分体而设置。
在半导体部分30上、绝缘部件41上以及电极42上设有层间绝缘膜45。在层间绝缘膜45内设有源极触点46以及漏极触点47。源极触点46的下端与源极触点层14连接。漏极触点47的下端与漏极触点层20连接。在从上方观察时，凹部36位于源极触点46与漏极触点47之间。另外，在从上方观察时，电极42的第二部分42b的一部分配置于第一部分42a与漏极触点47之间。
通过以上的构成，在半导体装置1形成n沟道型的DMOS。另外，上述的各层的导电型也可以相反。在这种情况下，形成p沟道型的DMOS。另外，在半导体装置1中，也可以形成有用于将DMOS与其他元件分离的杂质含有层以及STI(Shallow Trench Isolation：元件分离绝缘膜)等。而且，也可以不形成外延层11，而在导电型为p型的硅基板10的上层部分形成上述的n沟道型的DMOS。构成半导体部分30的各层并不限于可清楚地观察到边界。
半导体装置1例如能够通过以下的方法来制造。
首先，在硅基板10的上表面使硅外延生长，形成外延层11。接下来，例如通过干式蚀刻法，在外延层11的上表面形成锥状的凹部36。接下来，实施热氧化处理，对外延层11的表面进行氧化。接下来，通过选择性地离子注入杂质，形成p型阱12、漂移层17、n型阱18。
接下来，通过以TEOS为原料的CVD法，在凹部36内埋入硅氧化物，通过CMP(Chemical Mechanical Polishing：化学机械研磨)法等将上表面平坦化。接下来，选择性地去除埋入凹部36内的硅氧化物的一部分。由此，硅氧化物的残留部分成为绝缘部件41。接下来，实施热氧化处理，在凹部36中的半导体部分30的露出面形成栅极绝缘膜43。接下来，使多晶硅堆积，并进行图案化，由此形成电极42。接下来，选择性地离子注入杂质，形成源极层13、漏极层19、主体层15、源极触点层14、漏极触点层20、主体触点层16。
接下来，通过以TEOS为原料的CVD法，在半导体部分30上形成层间绝缘膜45。接下来，在层间绝缘膜45内形成源极触点46以及漏极触点47。源极触点46与源极触点层14连接，漏极触点47与漏极触点层20连接。如此，制造了半导体装置1。
接下来，对本实施方式的半导体装置1的动作进行说明。
在使半导体装置1驱动时对源极触点46与漏极触点47之间施加直流电压。例如，对源极触点46施加接地电位(0V)作为源极电位，对漏极触点47施加正的漏极电位、例如40V。另外，对主体触点层16例如施加源极电位。
在该状态下，若对电极42施加接通电位、例如5V，则在第一层31中的接近栅极绝缘膜43的部分形成反转层，电流在源极触点46与漏极触点47之间流动。即，DMOS成为接通状态。另一方面，若对电极42施加断开电位、例如0V，则反转层消失而耗尽层扩展，电流被切断。即，DMOS成为断开状态。此时，在被施加0V的电极42与被施加40V的第三层33之间形成电场。
接下来，对本实施方式的效果进行说明。
在半导体装置1中，电极42中的配置于凹部36内的第一部分42a作为栅极电极而发挥功能，切换DMOS的接通状态与断开状态。另一方面，电极42中的搭在绝缘部件41上的第二部分42b作为场板电极而发挥功能，缓和断开状态下的电场的集中。
此时，由于角度θ1为锐角，因此在绝缘部件41的与漏极层19对置的侧面41d以越向下方越接近第二部分42b的正下方的方式倾斜。由此，电极42的第二部分42b与第三层33的距离被均匀化，能够抑制电场的集中。其结果，DMOS的耐压提高。另外，通过调整电极42的第二部分42b的漏极侧的端部与绝缘部件41的侧面41d的位置关系，能够控制源极－漏极间耐压。半导体装置1中的DMOS的源极－漏极间耐压例如为10V以上。
另外，接通状态时从源极层13流向漏极层19的电子电流在第一层31中的沿着栅极绝缘膜43的部分、以及第三层33中的沿着栅极绝缘膜43、绝缘部件41的底面41b及侧面41d的部分中流动。而且，由于角度θ2以及角度θ1为锐角，因此电子电流容易在第一层31中的沿着栅极绝缘膜43的部分、第三层33中的沿着绝缘部件41的侧面41d的部分中流动。其结果，DOMOS的接通电阻较低。
而且，电极42的第一部分42a经由栅极绝缘膜43与半导体部分30的第一层31对置。由此，第一层31中的沿着栅极绝缘膜43的部分成为沟道层。由于沟道层的一部分沿凹部36的侧面36s而形成，因此除了横向、即从源极层13朝向漏极层19的方向之外，也沿纵向、即从源极层13朝向硅基板10的方向延伸。因此，能够抑制横向上的沟道层的尺寸，并且能够实现作为整体所需的沟道长。由此，能够实现半导体装置1的小型化。
另外，在半导体装置1中，源极触点46与源极触点层14连接，漏极触点47与漏极触点层20连接。由此，能够从半导体部分30的上表面侧向源极以及漏极供给电位。因而，在半导体装置1中，无需为了向源极以及漏极供给电位而形成较深的沟槽、或者从硅基板10的背面侧形成电极构造，通用性较高。
＜第二实施方式＞
接下来，对第二实施方式进行说明。
图2是表示本实施方式的半导体装置的剖面图。
如图2所示，在本实施方式的半导体装置2中，在第一实施方式的半导体装置1的构成的基础上，设有电极52。电极52配置于绝缘部件41上的电极42的第二部分42b与漏极触点47之间。电极52与电极42分离，并与绝缘部件41以及层间绝缘膜45相接。能够与电极42独立地对电极52施加电位。
在半导体装置2中，在DMOS的断开状态时，对电极52施加施加于电极42的断开电位与施加于漏极触点47的漏极电位之间的中间电位。中间电位例如能够设为与接通状态时施加于电极42的接通电位相同的电位。例如，在断开电位为0V、漏极电位为40V时，也可以对电极52施加5V的中间电位。
由此，能够控制在电极42与第三层33之间产生的电场的分布，能够缓和电场的集中。其结果，DMOS的耐压进一步提高。另一方面，在接通状态时，能够对电极52施加接通电位(例如，5V)、或者设为浮置状态。本实施方式中的上述以外的构成、动作以及效果与第一实施方式相同。
＜第三实施方式＞
接下来，对第三实施方式进行说明。
图3的(a)是表示本实施方式的半导体装置的俯视图，(b)是其剖面图。
如图3的(a)以及(b)所示，在本实施方式的半导体装置3中，形成有多个第一实施方式中所说明的DMOS。具体而言，在共用的硅基板10以及外延层11上交替地排列有源极层13与漏极层19，在每个源极层13与漏极层19之间形成有凹部36。在各凹部36内及其上方设有绝缘部件41、电极42以及栅极绝缘膜43。在各凹部36内，绝缘部件41配置于漏极层19侧，电极42以及栅极绝缘膜43配置于源极层13侧。
另外，源极层13与主体层15沿着相对于源极层13以及漏极层19的排列方向(栅极长度方向)正交的方向(栅极宽度方向)交替地排列。由此，在相邻的两个DMOS间共用源极层13以及主体层15、或者共用漏极层19。半导体部分30的各层、绝缘部件41、电极42、栅极绝缘膜43沿着栅极宽度方向而延伸。而且，以包围设有多个DMOS的区域的方式，在半导体部分30上设有STI60。在从上方观察时，STI60的形状例如为框状。
根据本实施方式，在相邻的两个DMOS间共用源极层13以及主体层15、或者共用漏极层19，由此能够以较高的集成度排列多个DMOS。由此，能够提高半导体装置3所控制的电流的密度，实现半导体装置3的小型化。
本实施方式中的上述以外的构成、动作以及效果与第一实施方式相同。另外，如第二实施方式中所说明的那样，也可以在半导体装置3设置电极52。
根据以上说明的实施方式，可以实现能够兼顾高耐压与低接通电阻的半导体装置。
以上，虽然对本发明的几个实施方式进行了说明，但这些实施方式是作为例子而提出的，并不意图限定发明的范围。这些新的实施方式能够以其他各种方式实施，在不脱离发明的主旨的范围内，能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其等效的范围中。

Claims (10)

1.一种半导体装置，具备：
半导体部分，在上表面形成有凹部；
绝缘部件，设于所述凹部内的一部分；
第一电极，具有第一部分和第二部分，该第一部分设于所述凹部内的其他一部分，该第二部分设于比所述绝缘部件靠上方的位置；
栅极绝缘膜，设于所述半导体部分与所述第一部分之间，比所述绝缘部件薄；
源极触点，设于所述半导体部分上；以及
漏极触点，设于所述半导体部分上，
所述半导体部分具有：
第一导电型的第一层，与所述栅极绝缘膜相接；
第二导电型的第二层，与所述第一层相接，并与所述源极触点连接；以及
第二导电型的第三层，与所述第一层相接，并与所述漏极触点连接，
在从上方观察时，所述凹部位于所述源极触点与所述漏极触点之间，
所述绝缘部件配置于所述第一部分与所述第三层之间。
2.如权利要求1所述的半导体装置，
在从上方观察时，所述第二部分的一部分配置于所述第一部分与所述漏极触点之间。
3.如权利要求1或2所述的半导体装置，
所述第三层与所述绝缘部件相接。
4.如权利要求1或2所述的半导体装置，
所述凹部的侧面为锥状。
5.如权利要求1或2所述的半导体装置，
所述绝缘部件的所述第三层侧的侧面与所述绝缘部件的上表面所成的第一角度为锐角。
6.如权利要求5所述的半导体装置，
所述第一角度为10度以上且85度以下。
7.如权利要求1或2所述的半导体装置，
所述栅极绝缘膜的表面与所述凹部的上表面所成的第二角度为锐角。
8.如权利要求1或2所述的半导体装置，
所述第一部分配置于所述绝缘部件与所述栅极绝缘膜之间。
9.如权利要求1或2所述的半导体装置，
所述半导体装置还具备第二电极，该第二电极设于所述绝缘部件上、且所述第一电极与所述漏极触点之间。
10.如权利要求1或2所述的半导体装置，
所述半导体部分含有硅，
所述栅极绝缘膜是硅的氧化膜。
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