CN112889354A - 电路组件 - Google Patents
电路组件 Download PDFInfo
- Publication number
- CN112889354A CN112889354A CN201980068443.5A CN201980068443A CN112889354A CN 112889354 A CN112889354 A CN 112889354A CN 201980068443 A CN201980068443 A CN 201980068443A CN 112889354 A CN112889354 A CN 112889354A
- Authority
- CN
- China
- Prior art keywords
- metal core
- circuit assembly
- blind hole
- solder
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 82
- 239000002184 metal Substances 0.000 claims abstract description 82
- 229910000679 solder Inorganic materials 0.000 claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 11
- 239000000919 ceramic Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000005553 drilling Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 230000035882 stress Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000001351 cycling effect Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000005382 thermal cycling Methods 0.000 description 3
- IYZWUWBAFUBNCH-UHFFFAOYSA-N 2,6-dichlorobiphenyl Chemical compound ClC1=CC=CC(Cl)=C1C1=CC=CC=C1 IYZWUWBAFUBNCH-UHFFFAOYSA-N 0.000 description 2
- 101100129500 Caenorhabditis elegans max-2 gene Proteins 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004519 grease Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09072—Hole or recess under component or special relationship between hole and component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
本发明描述了一种电路组件(1),其包括:电路板(10),其具有金属芯(11)、导电迹线(13)的图案、以及在金属芯(11)和导电迹线(13)之间的电介质层(12);至少一个电路部件(20),其借助于焊料互连件(33)安装到电路板(10),其中,焊料互连件(33)形成在电路部件(20)的接触垫(23)和导电迹线(13)之间;其特征在于,金属芯(11)包括至少一个腔(110),其中腔(110)布置在焊料互连件(33)的附近。本发明还描述了用于这种电路组件(1)的电路板(10)以及制造这种电路组件(1)的方法。
Description
技术领域
本发明描述了一种电路组件,以及制造这种电路组件的方法。
背景技术
通常将电路部件焊接到诸如印刷电路板(PCB)的载体。焊料提供了良好的电气连接,并且继续还用于将非常小的部件(诸如表面安装器件(SMD))安装到PCB。从封装部件或集成电路延伸的引线或支脚可以通过非常小的焊料珠连接到PCB,例如在回流焊接过程中。
但是,在设计的各个部分中使用的不同材料的热性能差异可能促进电路过早发生故障。例如,在PCB的金属芯、多芯片LED阵列的陶瓷载体、LED的蓝宝石衬底等之间可能存在非常高的热膨胀失配。这可能是个问题,尤其是当部件在操作期间反复加热(并膨胀),并且然后冷却(并收缩)。在热循环期间不同的膨胀率和收缩率导致很大的力作用在板和部件之间的焊料接合件或互连件上,从而使互连层处于高应力状态。这可能导致互连层中的塑性应变,即某种程度的变形,这可能导致焊料材料中微观裂纹的形成。这种“微故障”可能在进一步的热循环期间加剧,并且可能最终导致一个或多个焊料接合件的疲劳故障,这实际上意味着电路的整体故障或灾难性故障。
通常,包括焊接到PCB上的电气和电子部件的系统经受彻底的温度循环测试,以便确定其抵抗温度极限的能力。这种温度循环测试可以遵循行业标准,例如JEDEC JESD22-A104。客户可以指定系统在故障之前必须承受的最小热循环次数,并且制造商必须遵守规格。
因此,为确保系统将通过温度循环测试,有必要采取一些措施以避免焊料互连件中故障的发生。例如,可以采取措施以减少在系统的各个部分中使用的金属之间的热失配。在单层绝缘金属衬底(IMS)或单层金属芯PCB(MCPCB)的情况下,这意味着选择金属(诸如铜)作为衬底或芯。可替代地,当在陶瓷载体上设置部件时,可以使用陶瓷镶嵌板。但是,这些设计选择导致大量附加成本。
因此,本发明的目的是提供一种降低这种系统的焊料互连件中的应力的更经济的方式。
发明内容
本发明的目的通过权利要求1的电路组件以及通过权利要求11的制造电路组件的方法来实现。
根据本发明,电路组件包括:电路板,其具有金属芯、导电迹线的图案、以及在金属芯和导电迹线之间的电介质层;以及至少一个电路部件,其借助于焊料互连件安装到电路板,其中,焊料互连件形成在电路部件的接触垫和导电迹线之间。本发明的电路组件的特征在于金属芯包括至少一个腔,其中腔形成在焊料互连件的下方,作为具有正圆柱体的形状的盲孔。
该电路组件可以称为金属芯PCB(MCPCB)系统,因为它包括一个或多个安装在金属芯PCB上的电路部件。如上所述,由于MCPCB系统中的热膨胀系数的失配而引起的塑性应变可能导致电路故障。本发明的电路组件的优点在于,可以显著降低焊料互连件中的这种塑性应变。术语“焊料互连件”和“焊料接合件”是同义的,并且可以在本文中互换使用。发明人已经看到,通过在金属芯中在焊料接合件下方的位置处形成一个或多个腔,焊料接合件经受较小的塑性应变。这是因为腔导致应力重新分布,从而减小了在应力最大值否则可能导致裂纹萌生和/或裂纹增长的关键位置处由各种材料的不同热膨胀引起的应力。由于腔导致焊料接合件处的应力的这种显著降低,因此可以考虑对现有技术MCPCB系统所需的昂贵金属芯的替代方案。本发明的MCPCB可以以非常成本有效的方式实现,因为它允许将廉价且容易获得的金属(诸如铝)用于金属芯。
如上所解释的,在未来的焊料接合件的下方形成了正圆柱体或“盲孔”形状的腔。这可以理解为意味着腔可以形成为位于电路组件的焊料接合件的下方,例如腔可以形成在焊料接合件的(未来)位置的正下方;但是,取决于各种参数(诸如腔深度、腔直径、各腔之间的距离等),另一个腔的位置可能同样很好地从焊料接合件偏移。
根据本发明,制造这种电路组件的方法包括以下步骤:提供用于电路板的金属芯;在金属芯中形成多个盲孔,其中,盲孔的位置基于未来或计划的焊料互连件的位置来选择;将电介质层施加到金属芯上;在电介质层上形成导电迹线的图案;以及在电路部件的接触垫和对应的导电迹线之间形成焊料互连件。
本发明的方法为上述问题提供了一种有利的廉价解决方案,因为在金属芯中形成腔的步骤是简单的,并且可以使用容易获得的铣削或钻孔工具来完成。该步骤可以在施加电介质层的步骤之前的任何节点进行,并且不需要洁净室条件。腔可以以随机的方式形成在金属芯中,或者可以以预定义的图案布置。该方法可以足以导致一个或多个腔的位置在焊料互连件的附近。然而,优选地,选择腔的位置,使得腔肯定将在焊料互连件的附近。为了实现这一点,所需要做的就是对未来的焊料互连件的位置的一些了解,该焊料互连件将用于将一个或多个电路部件接合到在板上形成的导电迹线上。一旦形成腔,就可以以通常的方式制备金属芯,以用于随后的电介质的层压。随后是铜层的层压,并且然后进行光刻蚀刻以形成导电迹线图案。
从属权利要求和以下描述公开了本发明的特别有利的实施例和特征。实施例的特征可以适当地组合。在一个权利要求类别的上下文中描述的特征可以同样适用于另一权利要求类别。
在金属芯PCB中,术语“芯”或“基底”是指为MCPCB提供结构稳定性以及提供高效散热的金属板。金属芯实质上是平坦矩形金属板。如上所解释的,由于与热膨胀系数之间的失配相关联的问题,因此通常必须使用铜芯。对于本发明的MCPCB,可以使用具有高热膨胀系数的金属,例如铝,其还具有相对廉价且易于加工的优点。因此,在不以任何方式限制本发明的情况下,以下可以假定芯由铝制成。金属芯的厚度例如可以在1.5 mm的量级。当然,取决于各种因素,诸如所用金属的类型、所需的散热率等,金属芯可以具有任何合适的厚度。
从现有技术已知在多层级PCB中使用盲孔,但是本发明的MCPCB的腔或盲孔用作完全不同的目的。在多层级PCB中,穿过PCB的电介质层形成盲孔以电连接不同层级处的金属迹线。在本发明的MCPCB中,腔或盲孔不是电路的一部分。相反,它用于吸收由相对厚的金属芯的膨胀或收缩引起的热应力。在沉积将形成导电迹线的铜层之前,通过施加在芯上的不间断的电介质层,在本发明的MCPCB的金属芯中形成的任何盲孔对系统的其余部分隐藏。
腔可以以多种方式形成并且可以具有任何合适的形状。例如,可以通过在金属芯的表面中铣削凹陷或凹坑来形成腔。优选地,通过在金属芯中钻出圆柱形孔来形成腔。在本发明的特别优选的实施例中,腔形成为正圆柱形孔,该圆柱形孔延伸穿过金属芯的主体,即,从“顶”表面(将在其上施加电介质)穿到底表面。在这样的实施例中,盲孔的纵轴基本上垂直于基本矩形的平坦金属芯的主表面。
腔可以保持“空”而没有任何负面影响。然而,在施加电介质层之前,可以优选地利用合适的导热材料填充一些腔或全部腔。因此,在本发明的优选实施例中,腔至少部分地填充有具有有利地高热导率并且还具有有利地低热膨胀系数的材料。例如,腔可以填充有一种类型的导热油脂,该导热油脂用于克服表面粗糙度,例如石墨基导热油脂。利用这种材料填充腔的任何步骤优选地在电路部件已经被焊接到电路板之后执行。
优选地,金属芯被制备为在每个焊料互连件下方包括至少一个腔或盲孔。焊料接合件的接触面积通常可以在0.1–3.0 mm2的量级。在本发明的特别优选的实施例中,在这种焊料接合件下方的腔的截面面积最大为2.5mm2。在本发明的另一优选实施例中,腔的截面面积至少为0.05 mm2。在本发明的优选实施例中,在每个焊料接合件下方提供单个盲孔,并且优选地形成一个盲孔,使得其将位于将在焊料接合件下方的区域的中心。
在一些实施例中,单个盲孔可以足以确保有利地减轻热膨胀效应,即减小焊料互连处的应变。同样,如果尺寸非常小,则在焊料接合件下方形成多于一个盲孔可能不可行。但是,在具有合适尺寸的MCPCB系统中,优选在焊料接合件下方提供多于一个盲孔。例如,在焊料接合件下方提供非常小的盲孔的2x2或3x3阵列可能是有益的。
当电路部件需要高效散热时,通常MCPCB系统是优选的。在本发明的优选实施例中,电路部件包括半导体封装,该半导体封装具有安装在陶瓷载体或瓦片上的多个LED管芯。在这样的实施例中,焊料互连件形成在陶瓷载体的接触垫与电路板的导电迹线之间。
根据结合附图考虑的以下详细描述,本发明的其他目的和特征将变得清楚。但是,应当理解,附图仅是出于说明的目的而设计的,而不是对本发明的限制的定义。
附图说明
图1示出了穿过现有技术MCPCB系统的截面;
图2示出了用于本发明电路组件的实施例的金属芯PCB的透视图;
图3示出了图2的金属芯PCB的另一透视图;
图4示出了穿过本发明的电路组件的实施例的截面;
图5-6示出了本发明的电路组件的实施例中的焊料互连件和盲孔布置;
图7示出了穿过本发明的电路组件的替代实施例的局部截面;
图8示出了现有技术电路组件和根据本发明的电路组件的TCT测试的模拟结果。
在附图中,相同的附图标记始终指代相同的对象。图中的对象不一定按比例绘制。
具体实施方式
图1示出了穿过现有技术MCPCB系统4的截面。这里,电路部件20借助于焊料接合件33被焊接到MCPCB 40。MCPCB 40包括金属芯41或基底层41,电绝缘电介质层12被施加到该金属芯41或基底层41。在光刻过程中,从沉积在电介质12上的铜层中蚀刻出铜迹线13。焊料接合件33形成在部件20的接触垫23与MCPCB 40的对应迹线13之间。当系统4的金属芯41与其他相关部件的热膨胀系数之间存在明显的不匹配时,可以形成微故障F,如在图的放大区域中所示。最终,这种微故障F可能导致焊料接合件33从接触表面13、23完全脱离,从而导致电路故障。出于该原因,这种现有技术MCPCB系统4或电路组件通常设置有金属芯41,该金属芯41具有相对低的热膨胀系数,例如铜芯。但是,这种芯41所需的金属体积是相当大的,因此铜芯的成本可能很高。
图2示出了金属芯PCB 10,即使基底层11或芯11由具有大的热膨胀系数的相对金属(例如铝)制成,该金属芯PCB 10也可以抵消不期望的热失配效应。该图示出了从下方看的透视图,其指示金属芯11的底表面11B、电介质层12以及铜层120(将从该铜层120蚀刻出导电迹线)。为了补偿电路的铝芯11和其他相关部分的热膨胀系数之间的失配,芯11设置有多个腔110。在该示例性实施例中,腔110从下面钻到基底层11中,处于后续将位于焊料接合件下方的位置。
图3示出了从上方看的透视图,其指示图2的金属芯11、电介质层12以及从铜层130蚀刻的导电迹线13。还示出了未来焊料接合件的位置。这些将形成在迹线13的专用互连区域330或接合区域330上。在该示例性实施例中,每个焊料接合件将位于在金属芯11中形成的盲孔110的上方。
图4示出了根据本发明的MCPCB系统1的实施例的截面,类似于图1的系统4,但是使用了图2和3中描述的类型的MCPCB 10,即,具有由铝制成的金属芯11的PCB,铝是相当廉价的金属,但是其特征在于相对高的热膨胀系数。同样在这里,电路部件20借助于焊料接合件33焊接到MCPCB 10。本发明的目的是增加这种MCPCB系统或电路组件可以承受的热循环的次数而不发生故障,即,本发明的目的是避免焊料接合件33故障的发生。该图示出了焊料接合件33和在铝芯11中形成的盲孔110。左手的盲孔110被布置为位于对应的焊料接合件33的正下方,而右手的盲孔110从对应的焊料接合件33偏移。当部件20运行且非常热时,铝芯11的所产生的热膨胀效应由于盲孔110的存在而减轻。结果是减小了焊料接合件33上的应力,使得可以推迟或甚至完全避免对焊料接合件33疲劳相关的损坏。
图5示出了穿过焊料接合件33和盲孔110的视图,示出了示例性尺寸。这里,在芯中在焊料接合件33下方的位置处已经形成了单个盲孔110。焊料接合件33覆盖的面积可以例如大约为1.5mm2,并且盲孔110可以被钻为约0.4mm的直径D110,从而给出了约0.12 mm2的圆形截面面积。
图6示出了可以在芯中钻出的四个盲孔110的阵列。如图5所示,盲孔110可以位于焊料接合件33的下方。同样,盲孔110中的一个或多个可以从焊料接合件的位置偏移。盲孔110的直径可以相应地选择。
图7示出了穿过本发明的电路组件的另一替代实施例的局部截面。这里,在金属芯11的下表面11B中形成若干腔110。这里,每个腔110在金属芯11的下面11B中形成为凹坑或凹陷。
图8示出了现有技术MCPCB系统(在图的左侧)和根据本发明的MCPCB系统(在图的右侧)的TCT测试的模拟结果。在每种情况下,都对具有铝芯的MCPCB进行了建模,并具有相同的相关尺寸(诸如厚度),以模拟热循环对焊料接合件的影响。该图示出了铝芯模型M11和焊料接合件模型M33。可以假设该模拟考虑了与芯M11和焊料接合件M33之间的电介质层和导电迹线有关的参数。在左侧,将金属芯M11建模为实心板,即,在焊料接合件下方没有任何盲孔。在右侧,在金属芯中(在焊料接合件附近)建模盲孔M110。
该图示出了在模拟一系列热循环之后,在焊料接合件中塑性应变分布的区域。在图的左手侧,在焊料接合件M33的下部外部区域91处预测到最大等效塑性应变Max_1处于15%的量级。如此大的塑性应变将导致在相对少的热循环次数内发生微故障。这与实际测试系统进行的观察结果保持一致,在该系统中,在500次热循环之后已经观察到这种MCPCB焊料接合件的微故障。
在该图的右手侧,在焊料接合件M33的上部区域92处预测到最大等效塑性应变Max_2仅处于4%的量级。当与图的左手侧的配置相比时,这显著更低,并且示出了在焊料接合件M33附近设置盲孔M110的有益效果。通过减小焊料接合件M33中的塑性应变,可以增加在发生故障之前可以承受的热循环的次数,即,可以获得具有有利的长寿命的MCPCB系统。
尽管已经以优选实施例及其变型形式公开了本发明,但是将理解,在不脱离本发明范围的情况下,可以对其做出许多附加的修改和变型。例如,代替具有圆形截面的圆柱形孔,腔可以具有其中截面形状为正方形、矩形、星形等的任何合适的形式。可以使用任何合适的制造方法(诸如冲压、钻孔蚀刻等)来形成腔。
为了清楚起见,应当理解,遍及本申请使用“一”或“一个”不排除多个,并且“包括”不排除其他步骤或元件。
附图标记:
电路组件 1
电路板 10
金属芯 11
底表面 11B
盲孔 110
纵轴 110X
电介质层 12
导电迹线 13
电路部件 20
接触垫 23
焊接互连件 33
现有技术MCPCB系统 4
MCPCB 40
金属芯 41
最大应变 Max_1,Max_2。
Claims (15)
1.一种电路组件(1),包括:
-电路板(10),其具有金属芯(11)、导电迹线(13)的图案、以及在所述金属芯(11)和所述导电迹线(13)之间的电介质层(12),其中所述金属芯(11)是平坦矩形金属板;
-至少一个电路部件(20),其借助于焊料互连件(33)安装到所述电路板(10),其中,焊料互连件(33)形成在所述电路部件(20)的接触垫(23)和导电迹线(13)之间;
其特征在于
所述金属芯(11)包括形成在焊料互连件(33)下方的至少一个盲孔(110),并且其中盲孔(110)形成为具有正圆柱体的形状。
2.根据权利要求1所述的电路组件,其中,盲孔(110)的纵轴(110X)沿与所述金属芯(11)和所述电介质层(12)之间的界面基本上垂直的方向延伸。
3.根据权利要求1或权利要求2所述的电路组件,其中,针对每个焊料互连件(33),所述金属芯(11)包括至少一个盲孔(110)。
4.根据前述权利要求中任一项所述的电路组件,其中,所述金属芯(11)由铝制成。
5.根据前述权利要求中任一项所述的电路组件,其中,盲孔(110)的截面面积最大为2.5 mm2。
6.根据前述权利要求中任一项所述的电路组件,其中,盲孔(110)的截面面积至少为0.05 mm2。
7.根据前述权利要求中任一项所述的电路组件,在每个焊料互连件(33)下方设置有单个盲孔(110)。
8.根据前述权利要求中任一项所述的电路组件,其中,盲孔(110)从所述金属芯(11)的下表面(11B)朝向所述电介质层(12)延伸。
9.根据前述权利要求中任一项所述的电路组件,其中,电路部件(20)包括半导体封装(20),所述半导体封装(20)具有安装在陶瓷载体上的多个LED管芯,并且其中焊料互连件(33)形成在所述陶瓷载体的接触垫(23)和所述电路板(10)的导电迹线(13)之间。
10.一种用于根据权利要求1至8中任一项所述的电路组件(1)中的电路板(10),所述电路板(10)包括金属芯(11)、施加到所述金属芯(11)的表面的电介质层(12)、以及形成在所述电介质层(12)上的导电迹线(13)的图案,其中所述金属芯(11)是平坦矩形金属板;
其特征在于
至少一个盲孔(110)形成在所述金属芯(11)中,其中,盲孔(110)具有正圆柱体的形状,并且布置在导电迹线(13)的互连件区域(330)的下方。
11.一种制造根据权利要求1至9中任一项所述的电路组件(1)的方法,该方法包括以下步骤:
-提供平坦矩形金属板作为电路板(10)的金属芯(11);
-在所述金属芯(11)中形成多个盲孔(110),其中,盲孔(110)的位置被选择为位于未来的焊料互连件(33)的下方,并且其中,盲孔(110)被形成为具有正圆柱体的形状;
-将电介质层(12)施加到所述金属芯(10)上;
-在所述电介质层(12)上形成导电迹线(13)的图案;以及
-在多个电路部件(20)的接触垫(23)和对应导电迹线(13)之间形成焊料互连件(33)。
12.根据权利要求11所述的方法,其中,在所述金属芯(11)中形成盲孔(110)的步骤包括钻圆柱形孔(110)以从所述金属芯(11)的下表面(11B)朝向所述电介质层(12)延伸到所述金属芯(11)中的步骤。
13.根据权利要求11或权利要求12所述的方法,其中,盲孔(110)位于将位于所述焊料互连件(33)下方的区域的中心处。
14.根据权利要求11至13中任一项所述的方法,其中,针对所述电路组件(1)的每个焊料互连件(33)形成至少一个盲孔(110)。
15.根据权利要求11至14中任一项所述的方法,其中,在所述电路组件(1)的单个焊料互连件(33)的下方形成多个盲孔(110)。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP18200984 | 2018-10-17 | ||
EP18200984.5 | 2018-10-17 | ||
PCT/EP2019/077070 WO2020078752A1 (en) | 2018-10-17 | 2019-10-07 | Circuit assembly |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112889354A true CN112889354A (zh) | 2021-06-01 |
CN112889354B CN112889354B (zh) | 2024-09-10 |
Family
ID=63921520
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201980068443.5A Active CN112889354B (zh) | 2018-10-17 | 2019-10-07 | 电路组件 |
Country Status (4)
Country | Link |
---|---|
US (1) | US11430931B2 (zh) |
EP (1) | EP3868183A1 (zh) |
CN (1) | CN112889354B (zh) |
WO (1) | WO2020078752A1 (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117501814A (zh) | 2021-04-16 | 2024-02-02 | 亮锐有限责任公司 | 具有缺口的发光二极管(led)器件 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0471938A1 (en) * | 1990-07-23 | 1992-02-26 | International Business Machines Corporation | High circuit density thermal carrier |
US5786986A (en) * | 1989-04-17 | 1998-07-28 | International Business Machines Corporation | Multi-level circuit card structure |
JP2007273835A (ja) * | 2006-03-31 | 2007-10-18 | Toyota Industries Corp | 金属ベース基板、及びそれを備える電子部品実装構造 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04152590A (ja) * | 1990-10-16 | 1992-05-26 | Tamura Seisakusho Co Ltd | 金属コア基板 |
JP2004253738A (ja) * | 2003-02-21 | 2004-09-09 | Toshiba Corp | パッケージ基板及びフリップチップ型半導体装置 |
JP4360240B2 (ja) * | 2004-03-22 | 2009-11-11 | 日立化成工業株式会社 | 半導体装置と半導体装置用多層基板 |
DE102006049562A1 (de) * | 2006-10-20 | 2008-04-24 | Qimonda Ag | Substrat mit Durchführung und Verfahren zur Herstellung desselben |
JP5068060B2 (ja) * | 2006-10-30 | 2012-11-07 | 新光電気工業株式会社 | 半導体パッケージおよびその製造方法 |
US9029991B2 (en) * | 2010-11-16 | 2015-05-12 | Conexant Systems, Inc. | Semiconductor packages with reduced solder voiding |
JP6282425B2 (ja) * | 2012-10-29 | 2018-02-21 | 新光電気工業株式会社 | 配線基板の製造方法 |
TWM555065U (zh) * | 2017-09-05 | 2018-02-01 | 恆勁科技股份有限公司 | 電子封裝件及其封裝基板 |
-
2019
- 2019-10-07 EP EP19779925.7A patent/EP3868183A1/en active Pending
- 2019-10-07 WO PCT/EP2019/077070 patent/WO2020078752A1/en unknown
- 2019-10-07 CN CN201980068443.5A patent/CN112889354B/zh active Active
- 2019-10-17 US US16/656,265 patent/US11430931B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5786986A (en) * | 1989-04-17 | 1998-07-28 | International Business Machines Corporation | Multi-level circuit card structure |
EP0471938A1 (en) * | 1990-07-23 | 1992-02-26 | International Business Machines Corporation | High circuit density thermal carrier |
JP2007273835A (ja) * | 2006-03-31 | 2007-10-18 | Toyota Industries Corp | 金属ベース基板、及びそれを備える電子部品実装構造 |
Also Published As
Publication number | Publication date |
---|---|
EP3868183A1 (en) | 2021-08-25 |
CN112889354B (zh) | 2024-09-10 |
US20200127182A1 (en) | 2020-04-23 |
US11430931B2 (en) | 2022-08-30 |
WO2020078752A1 (en) | 2020-04-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2146374B1 (en) | Printed circuit boards assembly comprising a heat sink | |
EP3310140B1 (en) | Mounting assembly with a heatsink | |
KR20190028760A (ko) | 하부 리세스형 부품 배치 | |
US7987587B2 (en) | Method of forming solid vias in a printed circuit board | |
JP2007535156A (ja) | 埋込み構成要素からの熱伝導 | |
KR101719822B1 (ko) | 솔더링 연결핀, 상기 솔더링 연결핀을 이용한 반도체 패키지 기판 및 반도체칩의 실장방법 | |
KR20090042777A (ko) | 반도체 플립칩 패키지를 위한 기판 및 공정 | |
US9326372B2 (en) | Semiconductor device manufacturing method and semiconductor mounting substrate | |
TW201507556A (zh) | 具有散熱墊及電性突柱之散熱增益型線路板 | |
US20170347455A1 (en) | Circuit board and electronic component device | |
CN112889354B (zh) | 电路组件 | |
JP6894816B2 (ja) | 放熱金属片素材を用いたプリント配線板の製造方法 | |
CN111642059A (zh) | 一种散热pcb板及其制作方法 | |
CN1560911B (zh) | 电路载板的制造方法 | |
US20110031004A1 (en) | Board, mounting structure of surface mounting component, and electronic device | |
JP4457905B2 (ja) | パワーモジュール用の絶縁回路基板およびパワーモジュール | |
US20240244761A1 (en) | Packages with a shortest distance between package connectors and a seating plane of at least 6 mils | |
KR20200144286A (ko) | 고방열 pcb 제조 방법 및 이에 의해 제조된 고방열 pcb | |
JP7041535B2 (ja) | プリント配線板とその製造方法 | |
WO2024155292A1 (en) | Integrated circuit package, system comprising printed circuit board and integrated circuit package, method of soldering integrated circuit package to printed circuit board | |
EP4095898A1 (en) | Thermally improved pcb for semiconductor power die connected by via technique and assembly using such pcb | |
KR20110026165A (ko) | 비아홀동메움피씨비 및 피씨비 비아홀 동메움방법 | |
US9107296B2 (en) | Thermo/electrical conductor arrangement for multilayer printed circuit boards | |
CN111480395A (zh) | 用于在功率构件和电路载体的金属层之间建立导热连接部的方法 | |
US7827679B1 (en) | Thermal management circuit board and methods of producing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |