CN1126168C - 具有封装材料的电子元件组件及其形成方法 - Google Patents

具有封装材料的电子元件组件及其形成方法 Download PDF

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Publication number
CN1126168C
CN1126168C CN98102142A CN98102142A CN1126168C CN 1126168 C CN1126168 C CN 1126168C CN 98102142 A CN98102142 A CN 98102142A CN 98102142 A CN98102142 A CN 98102142A CN 1126168 C CN1126168 C CN 1126168C
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CN
China
Prior art keywords
electronic component
trench
substrate
mask layer
component assembly
Prior art date
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Expired - Fee Related
Application number
CN98102142A
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English (en)
Chinese (zh)
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CN1201255A (zh
Inventor
菲利普C·塞拉亚
约翰R·克尔
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NXP USA Inc
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Motorola Inc
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Application filed by Motorola Inc filed Critical Motorola Inc
Publication of CN1201255A publication Critical patent/CN1201255A/zh
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Publication of CN1126168C publication Critical patent/CN1126168C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05599Material
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    • H01L2224/45001Core members of the connector
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/481Disposition
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    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
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    • H01ELECTRIC ELEMENTS
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2924/01075Rhenium [Re]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
CN98102142A 1997-05-30 1998-05-14 具有封装材料的电子元件组件及其形成方法 Expired - Fee Related CN1126168C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/865652 1997-05-30
US08/865,652 US5808873A (en) 1997-05-30 1997-05-30 Electronic component assembly having an encapsulation material and method of forming the same
US08/865,652 1997-05-30

Publications (2)

Publication Number Publication Date
CN1201255A CN1201255A (zh) 1998-12-09
CN1126168C true CN1126168C (zh) 2003-10-29

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN98102142A Expired - Fee Related CN1126168C (zh) 1997-05-30 1998-05-14 具有封装材料的电子元件组件及其形成方法

Country Status (5)

Country Link
US (1) US5808873A (enExample)
JP (1) JPH10335542A (enExample)
KR (1) KR19980086512A (enExample)
CN (1) CN1126168C (enExample)
MY (1) MY117410A (enExample)

Families Citing this family (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5759047A (en) * 1996-05-24 1998-06-02 International Business Machines Corporation Flexible circuitized interposer with apertured member and method for making same
JP2959480B2 (ja) * 1996-08-12 1999-10-06 日本電気株式会社 半導体装置及びその製造方法
US6650525B2 (en) 1997-04-08 2003-11-18 X2Y Attenuators, Llc Component carrier
US6509807B1 (en) 1997-04-08 2003-01-21 X2Y Attenuators, Llc Energy conditioning circuit assembly
US20030161086A1 (en) 2000-07-18 2003-08-28 X2Y Attenuators, Llc Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package
US7336468B2 (en) 1997-04-08 2008-02-26 X2Y Attenuators, Llc Arrangement for energy conditioning
US7110235B2 (en) 1997-04-08 2006-09-19 Xzy Altenuators, Llc Arrangement for energy conditioning
US7106570B2 (en) 1997-04-08 2006-09-12 Xzy Altenuators, Llc Pathway arrangement
US7336467B2 (en) 2000-10-17 2008-02-26 X2Y Attenuators, Llc Energy pathway arrangement
US6894884B2 (en) 1997-04-08 2005-05-17 Xzy Attenuators, Llc Offset pathway arrangements for energy conditioning
US7274549B2 (en) 2000-12-15 2007-09-25 X2Y Attenuators, Llc Energy pathway arrangements for energy conditioning
US7321485B2 (en) 1997-04-08 2008-01-22 X2Y Attenuators, Llc Arrangement for energy conditioning
US6995983B1 (en) 1997-04-08 2006-02-07 X2Y Attenuators, Llc Component carrier
US6606011B2 (en) 1998-04-07 2003-08-12 X2Y Attenuators, Llc Energy conditioning circuit assembly
US7301748B2 (en) 1997-04-08 2007-11-27 Anthony Anthony A Universal energy conditioning interposer with circuit architecture
US7042703B2 (en) 2000-03-22 2006-05-09 X2Y Attenuators, Llc Energy conditioning structure
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
US6603646B2 (en) 1997-04-08 2003-08-05 X2Y Attenuators, Llc Multi-functional energy conditioner
US7110227B2 (en) 1997-04-08 2006-09-19 X2Y Attenuators, Llc Universial energy conditioning interposer with circuit architecture
US6018448A (en) 1997-04-08 2000-01-25 X2Y Attenuators, L.L.C. Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package
US6215184B1 (en) * 1998-02-19 2001-04-10 Texas Instruments Incorporated Optimized circuit design layout for high performance ball grid array packages
US5888850A (en) * 1997-09-29 1999-03-30 International Business Machines Corporation Method for providing a protective coating and electronic package utilizing same
JPH11186294A (ja) * 1997-10-14 1999-07-09 Sumitomo Metal Smi Electron Devices Inc 半導体パッケージ及びその製造方法
KR100294910B1 (ko) 1997-12-30 2001-07-12 이중구 범프그리드어레이패키지및그제조방법
JPH11307689A (ja) 1998-02-17 1999-11-05 Seiko Epson Corp 半導体装置、半導体装置用基板及びこれらの製造方法並びに電子機器
US6365979B1 (en) * 1998-03-06 2002-04-02 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
EP1070389B1 (en) 1998-04-07 2007-12-05 X2Y Attenuators, L.L.C. Component carrier
US7427816B2 (en) 1998-04-07 2008-09-23 X2Y Attenuators, Llc Component carrier
US6362436B1 (en) * 1999-02-15 2002-03-26 Mitsubishi Gas Chemical Company, Inc. Printed wiring board for semiconductor plastic package
US6191477B1 (en) * 1999-02-17 2001-02-20 Conexant Systems, Inc. Leadless chip carrier design and structure
JP2000243876A (ja) * 1999-02-23 2000-09-08 Fujitsu Ltd 半導体装置とその製造方法
US6127728A (en) * 1999-06-24 2000-10-03 Lsi Logic Corporation Single reference plane plastic ball grid array package
KR20010009350A (ko) * 1999-07-09 2001-02-05 윤종용 기판이 없는 칩 스케일 패키지 및 그 제조방법
US6277672B1 (en) * 1999-09-03 2001-08-21 Thin Film Module, Inc. BGA package for high density cavity-up wire bond device connections using a metal panel, thin film and build up multilayer technology
US6483101B1 (en) 1999-12-08 2002-11-19 Amkor Technology, Inc. Molded image sensor package having lens holder
US6538213B1 (en) * 2000-02-18 2003-03-25 International Business Machines Corporation High density design for organic chip carriers
US6426565B1 (en) 2000-03-22 2002-07-30 International Business Machines Corporation Electronic package and method of making same
US7113383B2 (en) 2000-04-28 2006-09-26 X2Y Attenuators, Llc Predetermined symmetrically balanced amalgam with complementary paired portions comprising shielding electrodes and shielded electrodes and other predetermined element portions for symmetrically balanced and complementary energy portion conditioning
US6448507B1 (en) * 2000-06-28 2002-09-10 Advanced Micro Devices, Inc. Solder mask for controlling resin bleed
JP2002094082A (ja) * 2000-07-11 2002-03-29 Seiko Epson Corp 光素子及びその製造方法並びに電子機器
JP2004507198A (ja) 2000-08-15 2004-03-04 エクストゥーワイ、アテニュエイタズ、エル、エル、シー 回路のエネルギーを調整するための電極装置
US6395998B1 (en) 2000-09-13 2002-05-28 International Business Machines Corporation Electronic package having an adhesive retaining cavity
WO2002033798A1 (en) 2000-10-17 2002-04-25 X2Y Attenuators, Llc Amalgam of shielding and shielded energy pathways and other elements for single or multiple circuitries with common reference node
US7193831B2 (en) 2000-10-17 2007-03-20 X2Y Attenuators, Llc Energy pathway arrangement
US6582979B2 (en) 2000-11-15 2003-06-24 Skyworks Solutions, Inc. Structure and method for fabrication of a leadless chip carrier with embedded antenna
US6960824B1 (en) 2000-11-15 2005-11-01 Skyworks Solutions, Inc. Structure and method for fabrication of a leadless chip carrier
US6710433B2 (en) 2000-11-15 2004-03-23 Skyworks Solutions, Inc. Leadless chip carrier with embedded inductor
US6867493B2 (en) * 2000-11-15 2005-03-15 Skyworks Solutions, Inc. Structure and method for fabrication of a leadless multi-die carrier
US6611055B1 (en) 2000-11-15 2003-08-26 Skyworks Solutions, Inc. Leadless flip chip carrier design and structure
US6889429B2 (en) * 2001-03-26 2005-05-10 Semiconductor Components Industries, L.L.C. Method of making a lead-free integrated circuit package
US6657133B1 (en) * 2001-05-15 2003-12-02 Xilinx, Inc. Ball grid array chip capacitor structure
CN101370361B (zh) * 2001-06-13 2010-09-08 株式会社电装 埋有电子器件的印刷线路板的制造方法
MXPA02005829A (es) * 2001-06-13 2004-12-13 Denso Corp Tablero de cableados impresos con dispositivo electrico incrustado y metodo para la manufactura de tablero de cableados impresos con dispositivo electrico incrustado.
MY131114A (en) * 2001-06-27 2007-07-31 Shinko Electric Ind Co Wiring substrate having position information
JP4000507B2 (ja) * 2001-10-04 2007-10-31 ソニー株式会社 固体撮像装置の製造方法
US6762509B2 (en) * 2001-12-11 2004-07-13 Celerity Research Pte. Ltd. Flip-chip packaging method that treats an interconnect substrate to control stress created at edges of fill material
ATE477590T1 (de) * 2002-03-21 2010-08-15 Nxp Bv Halbleiterbauelement mit einer schutzenden sicherheitsbeschichtung und verfahren zu seiner herstellung
US6855573B2 (en) * 2002-09-19 2005-02-15 St Assembly Test Services Ltd. Integrated circuit package and manufacturing method therefor with unique interconnector
TWI285421B (en) * 2002-11-05 2007-08-11 Advanced Semiconductor Eng Packaging structure having connector
US7180718B2 (en) 2003-01-31 2007-02-20 X2Y Attenuators, Llc Shielded energy conditioner
US7440252B2 (en) 2003-05-29 2008-10-21 X2Y Attenuators, Llc Connector related structures including an energy conditioner
EP1649572A4 (en) 2003-07-21 2012-06-27 X2Y Attenuators Llc FILTER ASSEMBLY
CN1890854A (zh) 2003-12-22 2007-01-03 X2Y艾泰钮埃特有限责任公司 内屏蔽式能量调节装置
DE102004056449A1 (de) * 2004-01-16 2005-08-25 Continental Teves Ag & Co. Ohg Integriertes Bauelement
WO2005093827A1 (ja) * 2004-03-26 2005-10-06 Fujikura Ltd. 貫通配線基板及びその製造方法
GB2439861A (en) 2005-03-01 2008-01-09 X2Y Attenuators Llc Internally overlapped conditioners
US7817397B2 (en) 2005-03-01 2010-10-19 X2Y Attenuators, Llc Energy conditioner with tied through electrodes
US7586728B2 (en) 2005-03-14 2009-09-08 X2Y Attenuators, Llc Conditioner with coplanar conductors
US20060226202A1 (en) * 2005-04-11 2006-10-12 Ho-Ching Yang PCB solder masking process
US7429799B1 (en) 2005-07-27 2008-09-30 Amkor Technology, Inc. Land patterns for a semiconductor stacking structure and method therefor
US8026777B2 (en) 2006-03-07 2011-09-27 X2Y Attenuators, Llc Energy conditioner structures
DE102006059127A1 (de) * 2006-09-25 2008-03-27 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Anordnung optoelektronischer Bauelemente und Anordnung optoelektronischer Bauelemente
US20080258285A1 (en) * 2007-04-23 2008-10-23 Texas Instruments Incorporated Simplified Substrates for Semiconductor Devices in Package-on-Package Products
KR100860308B1 (ko) * 2007-06-05 2008-09-25 삼성전기주식회사 카메라 모듈 패키지 및 그 제조방법
KR20090041756A (ko) * 2007-10-24 2009-04-29 삼성전자주식회사 접착층을 갖는 프린트 배선 기판 및 이를 이용한 반도체패키지
JP4833307B2 (ja) * 2009-02-24 2011-12-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体モジュール、端子板、端子板の製造方法および半導体モジュールの製造方法
KR20110059054A (ko) * 2009-11-27 2011-06-02 삼성전기주식회사 집적 수동 소자 어셈블리
US8415785B1 (en) 2010-01-27 2013-04-09 Marvell International Ltd. Metal ring techniques and configurations
JP2011199261A (ja) * 2010-02-24 2011-10-06 Panasonic Corp 電子部品
US20120193802A1 (en) * 2011-02-01 2012-08-02 Chin-Tien Chiu Glob top semiconductor package
JP6111832B2 (ja) * 2013-05-06 2017-04-12 株式会社デンソー 多層基板およびこれを用いた電子装置、電子装置の製造方法
KR102430750B1 (ko) * 2019-08-22 2022-08-08 스템코 주식회사 회로 기판 및 그 제조 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5455456A (en) * 1993-09-15 1995-10-03 Lsi Logic Corporation Integrated circuit package lid
US5468784A (en) * 1994-02-23 1995-11-21 Tamura Kaken Corporation Photopolymerizable resin composition
US5468999A (en) * 1994-05-26 1995-11-21 Motorola, Inc. Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
US5652463A (en) * 1995-05-26 1997-07-29 Hestia Technologies, Inc. Transfer modlded electronic package having a passage means

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KR19980086512A (ko) 1998-12-05
MY117410A (en) 2004-06-30

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