CN112599515A - 半导体装置以及制造半导体装置的方法 - Google Patents
半导体装置以及制造半导体装置的方法 Download PDFInfo
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- CN112599515A CN112599515A CN202011070747.6A CN202011070747A CN112599515A CN 112599515 A CN112599515 A CN 112599515A CN 202011070747 A CN202011070747 A CN 202011070747A CN 112599515 A CN112599515 A CN 112599515A
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Abstract
半导体装置以及制造半导体装置的方法。一种半导体装置可包含基板介电结构和基板传导结构,基板传导结构穿越基板介电结构并且包含第一基板端子和第二基板端子;电子构件,具有耦接到第一基板端子的构件端子;以及第一天线组件,具有耦接到第二基板端子的第一组件端子、相邻于第一天线图案的第一组件头侧、相对于第一组件侧的第一组件基底侧以及第一组件侧壁。第一组件端子可以在第一组件基底侧处或在第一组件侧壁处从第一组件介电结构暴露。第一天线图案可以经由第一组件端子而耦接到基板。基板传导结构可耦接第一天线组件到电子构件。
Description
技术领域
本揭示内容总体而言涉及电子构件,更具体地,涉及半导体装置以及用于制造半导体装置的方法。
背景技术
现有半导体封装件和用于形成半导体封装件的方法是不足的,其例如是导致过多的成本、降低的可靠度、相对低的效能或是太大的封装尺寸。通过习知及传统的方式与本揭示内容及图式的比较,习知及传统的方式的进一步限制及缺点对于该领域中习知此技术人士而言将会变得明显。
发明内容
本发明的一态样为一种半导体装置,所述半导体装置包括:基板,包括:基板顶部侧;基板底部侧;基板介电结构,所述基板介电结构在所述基板顶部侧和所述基板底部侧之间;以及基板传导结构,所述基板传导结构穿越所述基板介电结构并且包括:第一基板端子;以及第二基板端子,所述第二基板端子在所述基板顶部侧处;电子构件,所述电子构件耦接到所述基板并且包括:耦接到所述第一基板端子的构件端子;以及第一天线组件,所述第一天线组件耦接到所述基板并且包括:第一组件介电结构;第一天线图案,所述第一天线图案耦接到所述第一组件介电结构;第一组件端子,所述第一组件端子耦接到所述第二基板端子;第一组件头侧,所述第一组件头侧相邻于所述第一天线图案;第一组件基底侧,所述第一组件基底侧相对于所述第一组件侧;以及第一组件侧壁,所述第一组件侧壁在所述第一组件头侧和所述第一组件基底侧之间;其中:所述第一组件端子在所述第一组件基底侧或所述第一组件侧壁中的至少一处从所述第一组件介电结构暴露;所述第一天线图案经由所述第一组件端子而被耦接到所述基板;所述第一天线组件耦接到在所述电子构件的覆盖区之外的所述基板;并且所述基板传导结构耦接所述第一天线组件到所述电子构件。
如本发明的一态样所述的半导体装置,所述第一天线组件包括:第一天线路径,所述第一天线路径穿越所述第一组件介电结构并且耦接到所述第一天线图案和所述第一组件端子。
如本发明的一态样所述的半导体装置,所述第一天线图案被定向成沿着实质上正交于所述第一天线头侧的方向通讯。
如本发明的一态样所述的半导体装置,所述第一天线组件包括:面向垂直方向的所述第一组件头侧,及被定向成沿着所述垂直方向通讯的所述第一天线图案;以及耦接到所述基板的所述第一组件基底侧。
如本发明的一态样所述的半导体装置,所述第一天线组件包括:面向第一水平方向的所述第一组件头侧,及被定向成沿着所述第一水平方向通讯的所述第一天线图案;以及耦接到所述基板的所述第一组件侧壁。
如本发明的一态样所述的半导体装置,所述半导体装置包括:耦接到所述基板的第二天线组件;其中:围绕所述电子构件的覆盖区的所述基板包括:基板向左部分、基板向右部分、基板向上部分以及基板向下部分;所述第一天线组件在所述基板向左部分处被耦接到所述基板顶部侧;并且所述第二天线组件在所述基板向右部分处被耦接到所述基板顶部侧。
如本发明的一态样所述的半导体装置,所述半导体装置包括:在所述基板顶部侧上的囊封物;其中:所述第二天线组件包括相邻于第二组件头侧的第二天线图案;所述第二天线组件包括第二组件侧壁;所述囊封物覆盖所述第一组件侧壁以及所述第二组件侧壁;并且所述囊封物暴露所述第一组件头侧以及所述第二组件头侧。
如本发明的一态样所述的半导体装置,所述电子构件包括:构件第一侧,所述构件第一侧耦接到所述基板顶部侧;构件第二侧,所述构件第二侧相对于所述构件第一侧;构件侧壁,所述构件侧壁在所述构件第一侧和所述构件第二侧之间;以及屏蔽结构,所述屏蔽结构覆盖所述构件第二侧和所述构件侧壁;并且所述囊封物覆盖相邻于所述构件侧壁的所述屏蔽结构。
如本发明的一态样所述的半导体装置,所述第一天线组件包括:面向垂直方向的所述第一组件头侧,及被定向成沿着所述垂直方向通讯的所述第一天线图案;以及耦接到所述基板的所述第一组件基底侧;并且所述第二天线组件包括:面向所述垂直方向的第二组件头侧,及被定向成沿着所述垂直方向通讯的第二天线图案;以及耦接到所述基板的第二组件基底侧。
如本发明的一态样所述的半导体装置,所述第一天线图案被定向成沿着所述垂直方向朝顶部通讯;所述第二天线图案被定向成沿着所述垂直方向朝底部通讯。
如本发明的一态样所述的半导体装置,所述第一天线组件包括:面向朝右方向的所述第一组件头侧,及被定向成沿着所述朝右方向通讯的所述第一天线图案;以及耦接到所述基板的所述第一组件侧壁;并且所述第二天线组件包括:面向与所述朝右方向相反的朝左方向的第二组件头侧,及被定向成沿着所述朝左方向通讯的第二天线图案;以及耦接到所述基板的第二组件侧壁。
如本发明的一态样所述的半导体装置,所述第一天线组件包括:面向垂直方向的所述第一组件头侧,及被定向成沿着所述垂直方向通讯的所述第一天线图案;以及耦接到所述基板的所述第一组件基底侧;并且所述第二天线组件包括:面向朝右方向的第二组件头侧,及被定向成沿着所述朝右方向通讯的第二天线图案;以及耦接到所述基板的第二组件侧壁。
如本发明的一态样所述的半导体装置,所述半导体装置包括:第三天线组件,所述第三天线组件在所述基板向上部分处耦接到所述基板并且包括:面向朝上方向的第三组件头侧,及被定向成沿着所述向上方向通讯的第三天线图案;以及耦接到所述基板的第三组件侧壁。
如本发明的一态样所述的半导体装置,所述半导体装置包括:第四天线组件,所述第四天线组件在所述基板向下部分处耦接到所述基板并且包括:面向朝下方向的第四组件头侧,及被定向成沿着所述朝下方向通讯的第四天线图案;以及耦接到所述基板的第四组件侧壁。
如本发明的一态样所述的半导体装置,所述半导体装置包括:第五天线组件,所述第五天线组件在所述基板向左部分处耦接到所述基板并且包括:面向朝左方向的第五组件头侧,及被定向成沿着所述朝左方向通讯的第五天线图案;以及耦接到所述基板的第五组件侧壁。
如本发明的一态样所述的半导体装置,所述半导体装置包括:第六天线组件,所述第六天线组件在所述基板向右部分处耦接到所述基板并且包括:第六组件头侧,及被定向成沿着所述垂直方向通讯的第六天线图案;以及耦接到所述基板的第六组件侧壁。
如本发明的一态样所述的半导体装置,所述电子构件耦接到所述基板底部侧。
如本发明的一态样所述的半导体装置,所述半导体装置包括:被动构件,所述被动构件耦接到所述基板且于所述电子构件上方。
如本发明的一态样所述的半导体装置,所述半导体装置包括:被动构件,所述被动构件耦接到在所述第一天线组件以及所述第二天线组件之间的所述基板顶部侧。
本发明的另一态样为一种方法,所述方法包括:提供基板,所述基板包括:基板顶部侧;基板底部侧;基板介电结构,所述基板介电结构在所述基板顶部侧以及所述基板底部侧之间;以及基板传导结构,所述基板传导结构穿越所述基板介电结构并且包括:第一基板端子;以及在所述基板顶部侧处的第二基板端子;将电子构件耦接到所述基板,所述电子构件包括:耦接到所述第一基板端子的构件端子;以及将第一天线组件耦接到所述基板,所述第一天线组件包括:第一组件介电结构;第一天线图案,所述第一天线图案耦接到所述第一组件介电结构;第一组件端子,所述第一组件端子耦接到所述第二基板端子;第一组件头侧,所述第一组件头侧相邻于所述第一天线图案;第一组件基底侧,所述第一组件基底侧相对于所述第一组件侧;以及第一组件侧壁,所述第一组件侧壁在所述第一组件头侧和所述第一组件基底侧之间;其中:所述第一组件端子在所述第一组件基底侧或所述第一组件侧壁中的至少一处从所述第一组件介电结构暴露;所述第一天线图案经由所述第一组件端子耦接到所述基板;所述第一天线组件被耦接到在所述电子构件的覆盖区之外的所述基板;并且所述基板传导结构耦接所述第一天线组件到所述电子构件。
附图说明
图1示出了范例性半导体装置的剖面图。
图2A至图2I示出了用于制造范例性半导体装置的范例性方法的剖面图。
图3示出了如图2C中所示的用于制造范例性半导体装置的范例性方法的平面图。
图4A和图4B示出了范例性天线组件的平面图和剖面图以及天线组件的范例性布局,其可被应用至用于制造范例性半导体装置的范例性方法。
图5A至图5C示出了范例性天线组件的平面图和剖面图以及天线组件的范例性布局,其可被应用至用于制造范例性半导体装置的范例性方法。
图6A至图6F示出了范例性天线组件的平面图和剖面图以及天线组件的范例性布局,其可被应用至用于制造范例性半导体装置的范例性方法。
图7A至图7D示出了范例性半导体装置的平面图和剖面图。
图8A至图8F示出了用于制造范例性半导体装置的范例性方法的剖面图。
图9A至图9F示出了如图8A至图8F中所示的用于制造范例性半导体装置的范例性方法的剖面图。
图10A和图10B示出了如图8A和图8B中所示的用于制造范例性半导体装置的范例性方法的平面图。
图11示出了范例性半导体装置的剖面图。
图12A至图12F示出了用于制造范例性半导体装置的范例性方法的剖面图。
图13示出了如图12A中所示的用于制造范例性半导体装置的范例性方法的平面图。
图14示出了范例性半导体装置的剖面图。
图15A至图15G示出了用于制造范例性半导体装置的范例性方法的剖面图。
图16A和图16B示出了如图15A和图15B中所示的用于制造范例性半导体装置的范例性方法的平面图。
具体实施方式
以下的讨论提供了半导体装置以及制造半导体装置的方法的各种范例。这些范例是非限制性的,并且所附申请专利范围的范畴不应该受限于在此所揭示的特定范例。在下面的讨论中,术语“范例”和“例如”是非限制性的。
这些图示出了一般的构造方式,并且可以省略公知特征和技术的描述和细节,以避免不必要地使本揭示内容模糊。另外,附图中的组件不一定按比例绘制。例如,图中的一些组件的尺寸可能相对于其他组件被放大,以帮助提高对本揭示内容中讨论的范例的理解。在不同附图中,相同的附图标记表示相同的组件。
术语“或”是指列表中由“或”所链接的项目中的任一个或多个。举例而言,"x或y"是表示三个组件的集合{(x)、(y)、(x,y)}中的任一组件。作为另一例子的是,"x、y或z"是表示七个组件的集合{(x)、(y)、(z)、(x,y)、(x,z)、(y,z)、(x,y,z)}中的任一组件。
术语“包括”或“包含”是“开放式”的术语,并且指定所陈述的特征的存在,但不排除存在或添加一个或多个其他特征。
这里可以使用术语“第一”、“第二”等来描述各种组件,并且这些组件不应受这些术语的限制。这些术语仅用于区分一个组件与另一个组件。因此,例如,在不脱离本揭示内容的教导的情况下,本揭示内容中讨论的第一组件可以被称为第二组件。
除非另有说明,否则术语“耦接”可用于描述彼此直接接触的两个组件或描述由一个或多个其他组件间接连接的两个组件。例如,如果组件A耦接至组件B,则组件A可以直接接触组件B或通过中间组件C间接连接至组件B。类似地,术语“上”或“上方”可以用于描述两个组件直接相互接触或描述由一个或多个其他组件间接连接的两个组件。
在一范例中,一种半导体装置可以包括:(a)基板,包括:基板顶部侧;基板底部侧;在基板顶部侧和基板底部侧之间的基板介电结构;以及基板传导结构,基板传导结构穿越基板介电结构并且包括:第一基板端子;以及在基板顶部侧处的第二基板端子;(b)电子构件,电子构件耦接到基板并且包括耦接到第一基板端子的构件端子;以及(c)第一天线组件,第一天线组件耦接到基板并且包括:第一组件介电结构;耦接到第一组件介电结构的第一天线图案;耦接到第二基板端子的第一组件端子;相邻于第一天线图案的第一组件头侧;相对于第一组件侧的第一组件基底侧;以及在第一组件头侧和第一组件基底侧之间的第一组件侧壁。第一组件端子可以在第一组件基底侧或第一组件侧壁中的至少一处从第一组件介电结构暴露。第一天线图案可以经由第一组件端子而耦接到基板。第一天线组件可以被耦接到在电子构件的覆盖区之外的基板。基板传导结构可以耦接第一天线组件到电子构件。
其他范例包括在本揭示内容中。此些范例可以在图式中、在申请专利范围中、或在本揭示内容的详述说明中发现。
图1示出了范例性半导体装置100的剖面图。在图1所示的范例中,半导体装置100可以包括电子构件110、天线组件130、囊封物140、基板150和外部互连件160。
电子构件110包括可以内部互连件111和电磁干扰(EMI)屏蔽件112。天线组件130可以包括介电结构131、传导结构132和133以及天线图案134。基板150可以包括介电结构151和153和传导结构152。
天线组件130、囊封物140、基板150和外部互连件160可以包括或被称为半导体封装件101或封装件101,并且可以保护电子构件110不受外部组件或环境的暴露所影响。半导体封装件101可提供外部组件和电子构件110之间的电性耦接。
图2A至图2I示出了用于制造范例性半导体装置100的范例性方法的剖面图。图3示出了用于制造范例性半导体装置100的范例性方法的平面图。
图2A示出了在制造的前段的半导体装置100的剖面图。在图2A所示的范例中,电子构件110的底部表面110b可以附接至形成在载体10上的暂时接合层11。在一些范例中,多个电子构件110可以被设置成具有行或列的矩阵配置且彼此间隔开,并且可以被附接至载体10。
在一些范例中,取放设备可以将电子构件110拾取且放置在载体10的暂时接合层11上,并且可以黏接至暂时接合层11。电子构件110可以具有实质平坦的顶部表面(或非主动区域)、与顶部表面相对的实质底部表面(或主动区域)以及将顶部表面和底部表面彼此连接的侧表面。电子构件110的底部表面可以黏接至载体10的暂时接合层11。电子构件110可以在其底部表面上包括至少一个内部互连件111。内部互连件111可以黏接至载体10的暂时接合层11。内部互连件111可以是电子构件110的外部输入/输出端子,并且可以包括或被称为晶粒垫或接合垫。内部互连件111可以具有范围从约2μm(微米)至约500μm的宽度。内部互连件111可以具有范围从约3μm至约50μm的厚度。内部互连件111可以包括导电材料,例如金属材料、铝、铜、铝合金或铜合金。
电子构件110可以包括或称为半导体晶粒、半导体芯片或半导体封装件或子封装件。在一些范例中,电子构件110可以包括特定应用集成电路、逻辑晶粒、微控制单元、内存、数字信号处理器、网络处理器、电源管理单元、音频处理器、射频电路和无线基带系统单芯片处理器中的至少一个。电子构件110可以具有范围从约0.01mm(毫米)至约1mm的厚度。
载体10可以是实质上平坦的平板。例如,载体10可以包括或称为板、晶圆、面板、半导体或条带。在一些范例中,载体10可以包括例如钢、不锈钢、铝、铜、陶瓷、玻璃或晶圆。载体10可以具有范围从约0.5mm至约1.5mm的厚度且可以具有范围从约200mm至约320mm的宽度。
载体10可以起到以整合方式处理多个组件的作用,以附接电子构件110和天线组件130、形成EMI屏蔽件112和形成囊封物140。载体10可以被经常地应用于本揭示内容的一些范例。
暂时接合层11可以设置在载体10的表面上。暂时接合层11可以使用以下的方式设置在载体10的表面上:涂覆制程,例如旋涂、刮刀片(doctor blade)、浇铸、喷涂、狭缝式涂覆(slot die coating)、帘式涂覆(curtain coating)、斜板式涂覆(slide coating)或边缘上刮刀涂覆(knife over edge coating);印刷制程,例如网版印刷、移印(padprinting)、凹版印刷、柔版涂覆或胶版印刷;喷墨印刷制程,其具有涂覆和印刷的中间特征;或黏合膜或黏合带的直接附接。暂时接合层11可以包括或被称为暂时黏合膜或暂时黏合带。暂时接合层11可以例如是热可剥离带(膜)或UV可剥离带(膜),并且其接合强度通过加热或UV照射被减弱或去除。在一些范例中,暂时接合层11可以具有减弱的接合强度或者可以通过物理或化学的外力去除。暂时接合层11可以具有范围从约20μm至约500μm的厚度。暂时接合层11可以允许载体10在稍后描述的囊封物140形成之后分离。暂时接合层11可以被经常地应用于本揭示内容的一些范例。
图2B示出了在制造的后段的半导体装置100。在如图2B所示的范例中,EMI屏蔽件112可以覆盖电子构件110。EMI屏蔽件112可以接触电子构件110的顶部表面和侧表面。EMI屏蔽件112可以完全覆盖电子构件110的顶部表面和侧表面以达到均匀的厚度。
EMI屏蔽罩112可以由传导材料制成,以执行屏蔽来自天线组件130所感应的EMI或屏蔽对电子构件110的外部感应的EMI的功能。在一些范例中,EMI屏蔽件112可以包括银(Ag)、铜(Cu)、铝(Al)、镍(Ni)、钯(Pd)或铬(Cr)。在一些范例中,可以通过溅射、喷涂、涂覆或镀覆来形成EMI屏蔽件112。在一些范例中,帽状金属盖可以用作EMI屏蔽件112。EMI屏蔽件112可以具有范围从约0.1μm至约10μm的厚度。
图2C和图3示出了在制造的后段的半导体装置100。在如图2C所示的范例中,天线组件130中的底部表面130b可以被黏接至设置在载体10上的暂时接合层11。
在一些范例中,取放设备可以拾取天线组件130以放置在载体10的暂时接合层11的表面上并且可以被黏接。在一些范例中,天线组件130可以被配置以使得两个天线被黏接至载体10以被定位在电子构件110的相对侧。天线组件130的内部表面130c可以与具有EMI屏蔽件112的电子构件110的侧表面110c间隔开。在此处,天线组件130的内部表面130c可以面对电子构件110的侧表面110c,并且天线组件130的外部表面130d可以面向外以与天线组件130的内部表面130c相对。天线组件130可以延伸而平行于电子构件110的侧表面110c。天线组件130可以包括范围从约0.01mm至约20mm的长度。天线组件130可以包括范围从约0.01mm至约20mm的宽度。天线组件130中的每一个可以具有范围从约0.01mm至约1mm的厚度或高度。在一些范例中,天线组件130可包括或被称为天线基板、天线模组或天线块。
天线组件130可包括:介电结构131,其具有实质平坦的顶部表面和底部表面;传导结构132和133,其暴露至介电结构131的内部和底部表面;及天线图案134,其暴露至介电结构131的顶部表面。传导结构132和133可以包括:传导图案或端子132,其暴露至介电结构131的底部表面;及传导路径133,其形成在介电结构131的内部。在一些范例中,天线组件130可以被配置以使得介电结构131和传导路径133中的一或多个依序垂直地堆栈。
在一些范例中,介电结构131可以具有实质平坦的顶部表面和底部表面。在一些范例中,介电结构131可以包括或被称为一或多个介电层、介电质、介电材料、绝缘层或绝缘材料。在一些范例中,介电结构131可以包括环氧树脂、酚醛树脂、玻璃环氧树脂、聚酰亚胺、聚酯纤维、环氧模制化合物、玻璃或陶瓷。介电结构131可以被配置以使得一或多个介电层被向上堆栈。介电结构131可以使天线组件130保持在实质平坦的状态。
可以通过介电结构131的底部表面暴露传导端子132。传导端子132可具有一或多个图案。传导端子132可以电连接至至少一个传导路径133。传导端子132中的每一个可以包括或被称为导体、传导材料、天线连接盘(land)、传导连接盘、天线垫、布线垫、连接垫、微垫、迹线或凸块下金属(UBM)。在一些范例中,传导端子132可以包括铜、铁、镍、金、银、钯或锡。
传导路径133可以穿过介电结构131,以接着电连接传导端子132与天线图案134。在一些范例中,传导路径133可以包括或被称为导体、传导材料、传导通孔、传导路径、传导迹线、传导图案、传导层、重新分布层或电路图案。传导路径133可以被配置以使得一或多个传导层使用各种图案向上堆栈。在一些范例中,传导路径133可以包括铜、铁、镍、金、银、钯或锡。
天线图案134可通过介电结构131的顶部表面130a暴露,以便能够进行通讯。天线图案134可以具有一或多个图案。天线图案134可以电连接至至少一个传导路径132。在一些范例中,天线图案134中的每一个可以包括或被称为偶极天线、单极天线、贴片天线、环形天线、波束天线、双极天线、折迭天线、菱形天线或半波天线。在一些范例中,天线图案134可以包括铜、金或银。
天线组件130可以使用定位于天线组件130的上方部分上的天线图案134垂直地发送/接收讯号。此天线组件130可以是垂直的天线。天线组件130可以考虑到结构和布局而以各种方式变化。在以下的讨论中,将会描述可以用各种方式变化的范例性天线组件和天线组件的范例性布局。
图4A和图4B出示了范例性天线组件的布局的视图,其具有沿着图4A中的线4B-4B截取的剖面图,其可以应用于用以制造例如半导体装置100或半导体装置1004的范例性半导体装置的范例性方法。在一些范例中,天线组件230可以类似于天线组件130,但是可以用不同的方式定向。在图4A和图4B所示的范例中,两个天线组件230可以与载体10或基板150耦接,以便被定位在电子构件110的相对侧处,如同图2C和图3中所示的天线组件130。在一些范例中,天线组件230可以类似于图2C中所示的天线组件130被设置。在一些范例中,天线组件230可以被配置以使得介电结构231和传导结构232的每一者中的一或多个被依序地堆栈,无论是以向内、向外或向上的方式。
天线组件230中的每一个可以包括:介电结构231,其具有实质平坦的顶部表面和底部表面;传导结构232,其形成在介电结构231内部且暴露于介电结构231的底部表面230b的部分;及天线图案234,其暴露至介电结构231的外部表面230d。
在一些范例中,介电结构231可以类似于图2和图3所示的介电结构131。介电结构231可以被配置以使得一或多个介电层的沿y轴堆栈。
传导结构232可以形成在介电结构131内部并且可以暴露至介电结构231的底部表面230b。传导结构232可以电连接至天线图案134,并且可以暴露至介电结构231的底部表面230b。在一些范例中,传导结构232可以包括或被称为导体、传导材料、传导通孔、传导路径、传导迹线、传导图案、传导层、重新分布层(RDL)或电路图案。传导结构232可以被配置以使得一或多个传导层使用各种图案从内部表面230c堆栈至外部表面230d。在一些范例中,传导路径232可以包括铜、铁、镍、金、银、钯或锡。
天线图案234可通过介电结构231的外部表面230a暴露,以便能够进行通讯。天线图案234可以形成在介电结构231的外部表面230a上以便具有一或多个图案。天线图案234可以电连接至至少一个传导结构232。在一些范例中,天线图案134中的每一个可以包括或被称为偶极天线、单极天线、贴片天线、环形天线、波束天线、双极天线、折叠天线、菱形天线或半波天线。在一些范例中,天线图案234可以包括铜、金或银。
天线组件230可以使用定位于天线组件230的外部表面230d上的天线图案234向外发送/接收讯号。此天线组件230可以是水平的天线。
图5A、图5B和图5C出示了范例性天线组件的布局的视图,其具有沿着图5A中的线5B-5B和5C-5C截取的剖面图,其可以应用于用以制造例如半导体装置100或半导体装置1005的范例性半导体装置的范例性方法。在图5A至图5C所示的范例中,四个天线组件330可以与载体10或基板150耦接,以使得两个天线被定位在电子构件110的相对侧处。天线组件330可以包括类似于图2C和图3所示的天线组件130的具有天线图案334x的两个垂直天线330x,以及类似于图4A和图4B所示的天线组件230的具有天线图案334y的两个水平天线330y。垂直天线330x可以类似于图2C和图3所示的天线组件130,并且水平天线330y可以类似于图4A和图4B所示的天线组件230。
天线组件330可以使用具有位于天线组件330的上方部分上的天线图案334x的垂直天线330X来垂直地发送/接收讯号,并且可以使用具有位于水平天线330y的外部表面上的天线图案334y的水平天线330y来横向地发送/接收讯号。
天线组件330可以被配置以使得具有不同定向的两个天线330x和330y被纵向(lengthwise)设置在电子构件110的一侧,并且具有不同定向的两个天线330x和330y被纵向设置在电子构件110的另一侧。
天线330x和330y中的每一个可以延伸范围从约0.01mm至约20mm的长度。天线330x和330y中的每一个可以延伸范围从约0.01mm至约20mm的宽度。天线组件330x和330y中的每一个可以具有范围从约0.01mm至约1mm的厚度或高度。在一些范例中,天线组件330中的每一个可包括或被称为天线基板、天线模组或天线块。
图6A、图6B、图6C和图6D出示了范例性天线组件的布局的视图,其具有沿着图6A中的线6B-6B、6C-6C和6D-6D截取的剖面图,其可以应用于用以制造例如半导体装置100或半导体装置1006的范例性半导体装置的范例性方法。在图6A至图6D所示的范例中,六个天线组件可以与载体10或基板150耦接,以使得天线330x和330y被纵向设置在电子构件110的第一相对侧,如同图5A、图5B和图5C所示的天线组件330的布局,并且天线430z被纵向设置在电子构件110的第二相对侧。
天线组件330可以包括:垂直天线组件330x,其在组件头侧135处具有面向一或多个垂直方向的天线图案334;以及两个水平天线330y,其在组件头侧135处具有类似于图5A至图5C所示的天线组件330而分别面向朝右和朝左的水平方向的天线图案334。天线组件430可以包括水平天线组件430z,其在组件头侧135处具有分别面向朝上和朝下的水平方向的天线图案134。
垂直天线330x可以与图2C和图3中所示的天线组件130类似的方式被配置,并且水平天线330y和430z可以与图4A和图4B中所示的天线组件230类似的方式被配置。
半导体装置1006的天线组件可以使用垂直天线组件330x垂直地发送/接收讯号,并且可以使用水平天线组件330y和430z水平地发送/接收讯号。在一些范例中,个别天线组件330x、330y和430z可以全部类似于天线组件130或者彼此相似。在一些范例中,天线组件330x、330y和430z之间的主要区别可以是在当与载体10或基板150耦接时以不同方向定向。
除了图2C、图3、图4A、图4B、图5A至图5C和图6A至图6D中所示的天线组件130、230、330和430的配置和布局之外,可以通过以类似于以各种方式描述的垂直天线或水平天线来设置垂直天线或水平天线而改变天线组件的构造和布局。
图2D示出了在制造的后段的半导体装置100。在图2D所示的范例中,囊封物140可以覆盖载体10、电子构件110和天线组件130。在一些范例中,可以使囊封物140与载体10的暂时接合层11的顶部表面、电子构件110的EMI屏蔽件112的外部表面和天线组件130的侧表面接触。在此处,天线组件130的天线图案134可以被暴露。
在一些范例中,囊封物140可包括或称为环氧模制化合物、环氧模制树脂或密封剂。在一些范例中,囊封物140可包括或被称为模制部分、密封部分、囊封物部分、保护部分、封装件或主体。在一些范例中,囊封物140可以包括有机树脂、无机填料、固化剂、催化剂、耦合剂、着色剂和阻燃剂。可以通过多种制程中的任何一种来形成囊封物140。在一些范例中,可以使用压缩模制、转移模制、液相囊封物模制、真空层压、膏印刷或薄膜辅助模制来形成囊封物140。囊封物140可以具有范围从约0.1mm至约2mm的厚度。囊封物140可以覆盖电子构件110和天线组件130,以保护电子构件110和天线组件130免受外部组件或环境的暴露所影响。
图2E示出了在制造的后段的半导体装置100。在图2E所示的范例中,半导体装置100可以被翻转以在载体10被定位在电子构件110、天线组件130和囊封物140上的状态下去除载体110。如果以这种方式翻转半导体装置100,则天线组件130的天线图案134可以定位在半导体装置100的底部表面上。
载体10可以从电子构件110的顶部表面110b、天线组件130的顶部表面130b以及囊封物140的顶表面140b被移除。暂时接合层11可以在暂时接合层11被黏接至载体10的状态下从电子构件110、天线组件130和囊封物140移除。在一些范例中,热、光、化学溶液或物理力可以被形成于暂时接合层11,从而移除或降低暂时接合层11的接合强度。因此,电子构件110的顶部表面110b、天线组件130的顶部表面130b和囊封物110的顶部表面140b可以被暴露。电子构件110的内部互连件111和天线组件130的传导端子130也可以被暴露。
图2F示出了在制造的后段的半导体装置100。在图2F所示的范例中,介电结构151可以被形成在电子构件110的顶部表面110b、天线组件130的顶部表面130b和囊封物140的顶部表面140b,并且可以被图案化,从而暴露内部互连件111和传导端子132。
介电结构151可以具有均匀的厚度,以覆盖电子构件110的顶部表面110b、天线组件130的顶部表面130b和囊封物140的顶部表面140b。可以在介电结构151中形成暴露电子构件110的内部互连件111和天线组件130的传导端子132的孔洞151x和151y。
介电结构151可以包括或称为介电质、介电材料、介电层、钝化层、绝缘层或保护层。在一些范例中,介电结构151可以包括电绝缘材料,例如聚合物、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺三嗪(BT)、模制材料、酚醛树脂、环氧树脂、硅氧树脂或丙烯酸酯聚合物。在一些范例中,可以通过各种制程中的任何一种来形成介电结构151。介电结构151可以通过例如旋涂、喷涂、印刷、PVD、CVD、MOCVD、ALD、LPCVD或PECVD来形成。介电结构151可以具有范围从约5μm到约50μm的厚度。
例如,屏蔽图案可以形成在介电结构151的顶部表面上,并且经暴露的介电结构151可以通过蚀刻去除,从而形成孔洞151x和151y。孔洞151x和151y可包括或称为开口或孔。介电结构151可以通过孔洞151x暴露电子构件110的内部互连件111的顶部表面,并且通过孔洞151y暴露天线组件130的传导端子132的顶部表面。例如,光阻可以作为屏蔽图案使用。
图2G示出了在制造的后段的半导体装置100。在图2G所示的范例中,传导结构152可以覆盖经由孔洞151x和151y所暴露的介电结构151的顶部表面、电子构件110的内部互连件111和天线组件130的传导端子132。
传导结构152可以具有多种图案,并且可以分别与通过孔洞151x和151y暴露的电子构件110的内部互连件111和天线组件130的传导端子132接触,并且可以被电连接。导电结构152可以包括导体152x,其将电子构件110的内部互连件111和天线组件130的传导端子132彼此电连接。导体152x可以从电子构件110上方的一点延伸到天线组件130中的每一个天线组件上方的一点,以将电子构件110与天线组件130电连接。
在一些范例中,传导结构152可以包括或被称为导体、传导材料、传导层、重新分布层(RDL)、布线图案、迹线图案或电路图案。在一些范例中,传导端子132可以包括铜、铁、镍、金、银、钯或锡。在一些范例中,一或多个导体152x可以包括或称为迹线、端子、垫、通孔、传导图案、传导层或传导路径,并且可以在电子构件110的覆盖区内和之外延伸。在一些范例中,可以使用例如各种传导材料(例如,铜、金、银或等效物)中的任何一种来形成传导结构152。可以通过多种制程(例如,溅射、无电解镀覆、电解镀覆、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或等效方法)中的任何一种来形成传导结构152。传导结构152可以形成为具有均匀的厚度,以覆盖通过孔洞151x和151y暴露的介电结构151的顶部表面、电子构件110的内部互连件111和天线组件130的传导端子132,并且可以使用屏蔽图案将其图案化以具有多个图案。传导结构152可以具有范围从约3μm至约50μm的厚度。
图2H示出了在制造的后段的半导体装置100。在图2H所示的范例中,介电结构153可以覆盖介电结构151和传导结构152以达到均匀的厚度。暴露传导结构152的顶部表面152b的孔洞153x可以形成在介电结构153中。介电结构153也可以通过孔洞153x暴露导体152x的顶部表面。介电结构153可以类似于介电结构151,并且可以类似于介电结构151来形成。
尽管仅示出了在基板150中的两个介电结构151和153及一个传导结构152,但这不是对本揭示内容的限制。在一些范例中,构成基板150的结构的数量可以小于或大于本揭示内容中示出的结构的数量。
在本范例中,基板150被呈现为重新分布层(RDL)基板。RDL基板可以包括一或多个传导性重新分布层以及一或多个介电层,其(a)可以在RDL基板所电耦接的电子构件上方逐层地形成,或者(b)可以逐层地形成在载体上方,该载体可以在电子构件和RDL基板耦接在一起之后完全去除或至少部分去除。RDL基板可以逐层制造以作为在晶圆级制程中的圆形晶圆上的晶圆级基板,或作为在面板级制程中的矩形或方形面板载体上的面板级基板。RDL基板可以在加成增建制程中形成,其可以包括与界定各别传导性重新分布图案或迹线的一或多个传导层交替堆栈的一或多个介电层,传导性重新分布图案或迹线被配置以集体地(a)将电性迹线扇出到电子构件的覆盖区之外,或(b)将电性迹线扇入到电子构件的覆盖区之内。可以使用例如电解镀覆制程或无电解镀覆制程的镀覆制程来形成传导图案。传导图案可以包括导电材料,例如铜或其他可镀覆的金属。可以使用例如光微影制程和形成光微影屏蔽的光阻材料的光图案化制程来形成传导图案的位置。RDL基板的介电层可以用光图案化制程来图案化,该光图案化制程可以包括光微影屏蔽,光经由该光微影屏蔽进行曝光以具有所期望的光图案特征(例如介电层中的通孔)。介电层可由光可界定的有机介电材料制成,例如聚酰亚胺(PI)、苯并环丁烯(BCB)或聚苯并恶唑(PBO)。此介电材料可以以液体形式旋涂或其他方式涂覆,而不是以预先形成的膜被附着。为了允许适当地形成期望的光界定特征,此可光界定的介电材料可以省略结构增强剂或可以是不含填料的,而没有可能会干扰来自光图案化制程的股线(strand)、编织物(weave)或其他颗粒。在一些范例中,具有无填料介电材料的此种无填料特性可减小所得介电层的厚度。尽管上述光可界定的介电材料可以是有机材料,但在一些范例中,RDL基板的介电材料可以包含一或多个无机介电层。无机介电层的一些范例可以包括硅氮化物(Si3N4)、硅氧化物(SiO2)或SiON。可以通过使用氧化或氮化制程而不是光界定的有机介电材料来生长无机介电层而形成无机介电层。此无机介电层可以是没有填料的,而没有股线、编织物或其他不同的无机颗粒。在一些范例中,RDL基板可以省略永久性芯结构或载体,例如包括双马来酰亚胺三嗪(BT)或FR4的介电材料,并且这些类型的RDL基板可以包括或称为无芯基板。本揭示内容中的其他基板也可以包括RDL基板。
在一些范例中,基板150可以是预先形成的基板。预先形成的基板可以在附接至电子构件之前被制造,并且可以包括在各别传导层之间的介电层。传导层可以包括铜并且可以使用电解镀覆制程来形成。介电层可以是相对较厚的光不可界定层,其可以作为预先形成的膜而非作为液体被附接,并且可以包括具有填料的树脂,例如股线、编织物或其他无机颗粒,以提高刚性或结构支撑。由于介电层是光不可界定的,因此可以使用钻孔或镭射来形成例如通孔或开口的特征。在一些范例中,介电层可以包括预浸材料或味之素构成膜(ABF)。预先形成的基板可以包括永久性芯结构或载体,例如包括双马来酰亚胺三嗪(BT)或FR4的介电材料,并且介电层和传导层可以形成在永久性芯结构上。在一些范例中,预先形成的基板可以是省略永久性芯结构的无芯基板,并且介电层和传导层可以形成在牺牲性载体上,该牺牲性载体在形成介电层和传导层之后并且在附接到电子构件之前被去除。预先形成的基板可以被称为印刷电路板(PCB)或层压基板。可以通过半加成或经修改的半加成制程来形成此预先形成的基板。在本揭示内容中的其他基板也可以包括预先形成的基板。
图2I示出了在制造的后段的半导体装置100。在图2I所示的范例中,外部互连件160可以被形成在传导结构152的顶部表面152b上。
外部互连件160可以电连接至传导结构152的顶部表面152b。外部互连件160可以通过基板150电连接至电子构件110或电连接至天线组件130。外部互连件160可以通过基板150的导体152x电连接至电子构件110和天线组件130。
在一些范例中,外部互连件160可以包括锡(Sn)、银(Ag)、铅(Pb)、铜(Cu)、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。外部互连件160可以使用例如球落制程、网版印刷制程或电解镀覆制程来形成。例如,可以通过使用球落制程然后进行回焊制程在基板150的传导结构152的顶部表面152b上预先制备包含焊料的传导材料来形成外部互连件160。外部互连件160可以包括或被称为传导球(例如焊料球)、传导柱(例如铜柱)或具有在铜柱上的焊料帽的传导杆。外部互连件160可以具有范围从约0.01mm至约1mm的尺寸。完成的半导体装置100可以被翻转,以便将外部互连件160定位在半导体装置100的底部表面100y上。
整个图2A至2I所提出的方法可以用于完成不同的半导体装置,例如与图4A至图6F的配置相对应的半导体装置。例如,图6A示出了半导体装1006的俯视图。图6B至图6F示出了沿着不同天线组件330x、330y、430z的半导体装置1006的剖面图。
图6A示出了几个天线组件,其示出为在电子构件110的覆盖区119周围或在天线组件的布置的中心周围所界定的基板部分处与基板150耦接,此基板部分由虚线所划分。天线组件330x1被示为耦接到基板向左部分156、天线组件330x2被示为耦接到基板向右部分157、天线组件330y1被示为耦接到基板向右部分157、天线组件330y2被示为耦接到基板向左部分156、天线组件430z1被示为耦接到基板向上部分158,并且天线组件430z2被示为耦接到基板向下部分159。
基板150包括基板介电结构,其具有在基板顶部侧154和基板底部侧155之间的一或多个介电层,例如介电层151、153。基板150还包括基板传导结构152,其包括一或多个导体、传导层、垫、通孔或迹线,其水平或垂直地穿越基板介电结构。基板传导结构152可以包括基板端子1521,并且可以包括在基板顶部侧154处暴露的基板端子1522。在一些范例中,基板端子1521、1522可以包括或者被称为垫、通孔或迹线。
电子构件110可以耦接至基板150,并且可以包括耦接至基板端子1521的构件端子115。在一些范例中,构件端子115可以包括或者被称为垫、凸块或柱。在一些范例中,电子构件110的构件侧面117可以直接接触基板顶部侧154。在一些范例中,例如当构件端子115包括凸块或柱时,电子构件110的构件侧面117可以与基板顶部侧相隔由构件端子115的高度所限定的间隙距离。
在一些范例中,图6A中所示的覆盖区119可以表示被电子构件110覆盖的基板150的区域,其中电子构件110可以例如相关于图1至图2I所示且描述的方式而耦接至基板顶部侧154,或者电子构件110可以例如下面相关于图11至图16B中的对应组件所示且描述的方式耦接至基板底部侧155。
半导体装置1006可以包括耦接至基板150的一或多个被动构件。在一些范例中,被动构件在特征或位置方面可类似于下面相对于图7A至图10B或图14至图16B所进一步描述的被动构件520或720。在一些范例中,被动构件中的一或多个可至少部分地在电子构件110的覆盖区119内耦接至基板150,无论此被动构件是在基板底部侧155上且电子构件110是在基板顶部侧154上,或者此被动构件是在基板顶部侧154上且电子构件110是在基板底部侧155上。在一些范例中,被动构件中的一或多个可以耦接至基板向上部分158,无论是在基板顶部侧154处或基板底部侧155处、在天线组件330x1与天线组件330y1之间、邻近天线组件430z1或者邻近电子构件110。在一些范例中,被动构件中的一或多个可以耦接至基板向下部分159,无论是在基板顶部侧154处或基板底部侧155处、在天线组件330y2与天线组件330x2之间、邻近天线组件430z2或者邻近电子构件110。在一些范例中,被动构件中的一或多个可以耦接至基板向左部分156,无论是在基板顶部侧154处或基板底部侧155处、在天线组件430z1与天线组件430z2之间、邻近天线组件330x1或天线组件330y2或者邻近电子构件110。在一些范例中,被动构件中的一或多个可以耦接至基板向右部分157,无论是在基板顶部侧154处或基板底部侧155处、在天线组件430z1与天线组件430z2之间、邻近天线组件330y1或天线组件330x2或者邻近电子构件110。
天线组件330x、330y、430z可以包括面向半导体装置1006水平地向外的向外垂直表面,以及与向外垂直表面相对的向内垂直表面。取决于天线组件而定,此向外垂直表面可以对应于组件头侧135或组件侧壁136,并且此向内垂直表面可以对应于组件基底侧137或组件侧壁136。半导体装置1006可以包括在基板顶部侧154上的囊封物140。在一些范例中,囊封物140可以覆盖天线组件330x、330y或430z的向内垂直表面。在一些范例中,囊封物140可以覆盖天线组件330x、330y或430z的向外垂直表面。在一些范例中,囊封物140使天线组件330x、330y或430z的向外垂直表面暴露。囊封物140还可以覆盖电子构件110的构件侧壁116或构件侧面115。在一些范例中,屏蔽结构112可以覆盖构件侧壁116和构件侧面115,并且囊封物140可以接着覆盖邻近构件侧壁116或邻近构件侧面115的屏蔽结构112。在一些范例中,囊封物140可以使与构件侧面115相邻的屏蔽结构112暴露。
图6B所示的剖面图对应于图6A的线6B-6B,并且示出了在电子构件110的覆盖区119之外耦接至基板150的天线组件330x1和天线组件330x2。天线组件330x1或天线组件330x2可以类似于先前描述的天线组件130。天线组件330x1可以类似于天线组件330x2,但是可以彼此相对地耦接。天线组件330y1和330y2的配置、定向或特征可以类似于前面关于图1至图3中的天线组件130所描述的配置、定向或特征。
作为范例,天线组件330x2包括:组件介电结构131,其包括一或多个介电层;天线图案134,其耦接至组件介电结构131;以及组件端子132,其耦接至基板端子1522。组件端子132可以是传导结构133的部分,其提供包括一或多个迹线或通孔的传导路径或天线路径,该迹线或通孔穿越组件介电结构131以将天线图案134耦接至组件端子132。天线组件330x1还包括:组件头侧135,其邻近天线图案134;组件基底侧137,其相对于组件头侧135;以及组件侧壁136,其在组件头侧135和组件基底侧137之间。在一些范例中,天线图案134可以在组件头侧134处或通过组件头侧134暴露以用于出站(outbound)或入站(inbound)无线通信。在本范例中,组件端子132在组件基底侧137处暴露,并且天线图案134通过组件端子132和基板端子1522耦接至基板150。基板传导结构152将天线组件330x2耦接至电子构件110,从而在组件端子132和构件端子115之间提供传导路径。
天线图案134可以被配置或定向成沿着实质正交于天线头侧135或天线图案134的方向发送或接收无线通信。对于天线组件330x2而言,组件头侧135面向朝顶部垂直方向,天线图案134定向成沿着此垂直方向进行通讯,且组件基底侧137耦接至基板150。类似而言,在本范例中,天线组件330x1包括面向朝顶部垂直方向的组件头侧135,天线图案134定向成沿着此垂直方向进行通讯,且组件基底侧137耦接至基板150。在一些范例中,囊封物140可以覆盖组件头侧135或天线图案134。在一些范例中,囊封物140可以被施加,或者天线组件330x1或天线组件330x2可以被定位,使得组件头侧面135或天线图案134保持从囊封物140暴露。
然而,可以存在多个范例,其中天线组件330x1或天线组件330x2中的一或两者可以被定向成使得天线头侧135面向水平方向以沿着此水平方向进行通讯。在此些范例中,组件侧壁136可以被耦接至基板150,或者组件端子132可以在组件侧壁137处暴露且耦接至基板端子1522。可以存在多个范例,其中天线组件330x1或天线组件330x2中的一者可以如上面所述的定向以进行朝顶部垂直通讯,并且天线组件330x1或天线组件330x2中的另一者可以被定向以使得天线头侧135面向朝底部垂直方向以沿着此垂直方向进行通讯。
图6C中所显示的剖面图对应于图6A的线6C-6C并且显示耦接到在电子构件110的构件覆盖区119之外的基板150的天线组件330y1以及天线组件330y2。天线组件330y1或天线组件330y2可相似于先前所描述的天线组件130。天线组件330y1可相似于天线组件330y2,但是可彼此相对的耦接。天线组件330y1及330y2的配置、定向或是特征可相似于上文中所描述的关于图4A至4B中的天线组件230。
在图6C中,天线组件330y1包含面向朝右水平方向的组件头侧135、具有定向成沿着该朝右水平方向通讯的天线图案134以及具有耦接到基板150的组件侧壁136。天线组件330y2包含面向朝左水平方向的组件头侧135、具有面向朝左水平方向的天线图案134以及具有耦接到基板150的组件侧壁136。在某些范例中,囊封物140可覆盖组件头侧135或天线图案134。在某些范例中,囊封物140可被施加或者是天线组件330y1或天线组件330y2可被定位,使得组件头侧135或天线图案134保持从囊封物140暴露。
图6D中所显示的剖面图对应于图6A的线6D-6D并且显示耦接到在电子构件110的构件覆盖区119之外的基板150的天线组件330x1以及天线组件330y1。天线组件330x1或天线组件330y1可相似于先前所描述的天线组件130。天线组件330x1可相似于天线组件330y1,但是可彼此相对的耦接或以不同定向耦接。
在图6D中,天线组件330x1包含面向垂直朝上方向的组件头侧135、具有定向成沿着该朝顶部垂直方向通讯的天线图案134以及具有耦接到基板150的组件基底侧137。天线组件330y1面向朝右水平方向的组件头侧135、具有定向用于沿着该朝右水平方向通讯的天线图案134以及具有耦接到基板150的组件侧壁136。在某些范例中,囊封物140可覆盖组件头侧135或天线图案134。在某些范例中,囊封物140可被施加或者是天线组件330x1或天线组件330y1可被定位,使得组件头侧135或天线图案134保持从囊封物140暴露。
图6E中所显示的剖面图对应于图6A的线6E-6E并且显示耦接到在电子构件110的构件覆盖区119之外的基板150的天线组件330y2以及天线组件330x2。天线组件330y2或天线组件330x2可相似于先前所描述的天线组件130。天线组件330x2可相似于天线组件330y2,但是可彼此相对的耦接或以不同定向耦接。
在图6E中,天线组件330y2包含面向朝左水平方向的组件头侧135、具有面向该朝左水平方向的天线图案134以及具有耦接到基板150的组件侧壁136。天线组件330x2包含面向朝顶部垂直方向的组件头侧135、具有定向成沿着该朝顶部垂直方向通讯的天线图案134以及具有耦接到基板150的组件基底侧137。在某些范例中,囊封物140可覆盖组件头侧135或天线图案134。在某些范例中,囊封物140可被施加或者是天线组件330y2或天线组件330x2可被定位,使得组件头侧135或天线图案134保持从囊封物140暴露。
图6F中所显示的剖面图对应于图6A的线6F-6F并且显示耦接到在电子构件110的构件覆盖区119之外的基板150的天线组件430z1以及天线组件430z2。天线组件430z1或天线组件430z2可相似于先前所描述的天线组件130。天线组件430z1可相似于天线组件430z2,但是可彼此相对的耦接或以不同定向耦接。
在图6F中,天线组件430z1包含面向朝上垂直方向的组件头侧135、具有定向成沿着该朝上垂直方向通讯的天线图案134以及具有耦接到基板150的组件侧壁136。天线组件430z2包含面向朝下垂直方向的组件头侧135、具有沿着该朝下垂直方向通讯的天线图案134以及具有耦接到基板150的组件基底侧137。在某些范例中,囊封物140可覆盖组件头侧135或天线图案134。在某些范例中,囊封物140可被施加或者是天线组件430z1或天线组件430z2可被定位,使得组件头侧135或天线图案134保持从囊封物140暴露。
图7A到7D显示范例性半导体装置的透视平面图、沿着图7A的线7B-7B的剖面图、沿着图7A的线7C-7C的剖面图以及沿着图7A的线7D-7D的剖面图。
在如图7A到7D显示的范例中,半导体装置500可包含电子构件110、被动构件520、天线组件130、囊封物540、基板550以及外部互连160。
电子构件110、天线组件130以及外部互连件160可相似于如图1中所示的半导体装置100的组件。被动构件520可包含端子521。基板550可包含介电结构551和553以及传导结构552。
天线组件130、囊封物540、基板550以及外部互连件160可包含或是被称为半导体封装件501或封装件501,并且可保护电子构件110和被动构件520免于受到外部组件或环境暴露的影响。半导体封装件501可提供外部组件和电子构件之间以及所述外部组件和被动构件520之间的电性耦接
图8A到图8F显示用于制造范例性半导体装置500的范例性方法的剖面图。图9A到图9F显示用于制造图8A到图8F所示的范例性半导体装置500的范例性方法的剖面图。特别是,在制造范例性半导体装置500的范例性方法的剖面图中,图8A到图8F显示沿着图7A中的线7C-7C的剖面图,并且图9A到图9F显示沿着图7A中的线7D-7D的剖面图。特别是,沿着图7A中的线7B-7B的剖面图可相似于图2C到图2I所示的剖面图。
图8A、图9A及图10A显示在前段的制造阶段的半导体装置500。
如在图8A、图9A及图10A中所示的范例中,可制备半导体装置500。如图8A、图9A及图10A中所示的半导体装置500可相似于如图2A到图2C及图3中所示的制造半导体装置100的范例性方法所制造的半导体装置100。
图8B、9B及10B显示在后段的制造阶段的半导体装置500。在图8B、图9B及图10B所示的范例中,被动构件520的底表面520b可被黏接到载体10的暂时接合层11的表面。被动构件520可被黏接到载体10,如此以定位在沿着第一方向x的电子构件110的相对侧处。被动构件520可以以具有行或列的矩阵配置的方式设置在载体10的暂时接合层11上并且黏接在载体10的暂时接合层11,如此被动构件520可在第二方向y上被定位在彼此分隔开的天线组件130之间。被动构件520的端子521可黏接至暂时接合层11。
在某些范例中,取放设备可以拾取和放置被动构件520于载体10的暂时接合层11上并且可黏接到暂时接合层11。被动构件520的底表面可黏接到暂时接合层11。被动构件520可包含暴露于其底表面的端子521。端子521可黏接到载体10的暂时接合层11。端子521可以是被动构件520输入端子/输出端子。
在某些范例中,被动构件520可包含电阻器、电容器、电感器、连接器以及等同物中的至少一个。被动构件520可以具有范围从大约0.01mm到大约2mm的整体厚度。
天线组件130可以借由图2C、图3、图4A、图4B、图5A到图5C以及图6A到图6D中所示的天线组件130、230、330以及430所使用的布局来改变。或者是,天线组件130可以借由以各种方式任意地配置垂直天线或水平天线来改变。在此,被动构件520可以根据布局而改变,如此以根据天线组件130、230、330以及430所使用的布局而以各种方式配置在载体10的暂时接合层11的表面内。
图8C及图9C显示在制造后段时的半导体装置500。在如图8C及图9C所示的范例中,囊封物540可覆盖载体10、电子构件110、被动构件520以及天线组件130。在某些范例中,囊封物540可以接触载体10的暂时接合层11的顶部表面、EMI屏蔽件112的外部表面、被动构件520的顶部表面和侧表面以及天线组件130的侧表面。此处,天线组件130的天线图案134可被暴露。囊封物540可相似于囊封物140并且可类似于囊封物140来形成。
图8D及图9D显示在制造后段时的半导体装置500。在如图8D及图9D所示的范例中,半导体装置500可被翻转以在载体10位在电子构件110、被动构件520、天线组件130以及囊封物540上的状态时移除载体10。
载体10可以从电子构件110的顶部表面110b、被动构件520的顶部表面520b、天线组件130的顶部表面以及囊封物540的顶部表面540b被移除。因此,电子构件110的顶部表面110b、被动构件520的顶部表面520b、天线组件130的顶部表面以及囊封物540的顶部表面540b可被暴露。电子构件110的内部互连件111、被动构件520的端子521以及天线组件130的传导端子132也可被暴露。载体10的移除可相似于图2E中所示的载体10的移除。
图8E及图9E显示在制造后段时的半导体装置500。在如图8E及图9E所示的范例中,基板550可被形成在电子构件110的顶部表面110b、被动构件520的顶部表面520b、天线组件130的顶部表面以及囊封物540的顶部表面540b上。在某些范例中,基板550可相似于基板150或者是可包含或可被称为基板。基板550可包含介电结构551、传导结构552以及介电结构553并且为依序地形成。
介电结构551可被首先形成在基板550上以覆盖电子构件110的顶部表面110b、被动构件520的顶部表面520b、天线组件130的顶部表面以及囊封物540的顶部表面540b而成均匀的厚度。分别暴露电子构件110的内部互连件111、天线组件130的传导端子132以及被动构件520的端子521的孔洞551x、551y及551z可被形成在介电结构551中。介电结构551可分别通过孔洞551x而暴露电子构件110的内部互连件111的顶部表面、通过孔洞551y而暴露天线组件130的传导端子132的顶部表面以及通过孔洞551z而暴露被动构件520的端子521的顶部表面。介电结构551可相似于介电结构151并且可类似于介电结构151来形成。
传导结构552可覆盖电子构件110的内部互连件111、天线组件130的传导端子132以及被动构件520的端子521并且通过介电结构551的顶部表面以及孔洞551x、551y和551z而被暴露。
传导结构552可被形成以具有多个图案,并且被连接到电子构件110的互连件111、天线组件130的传导端子132以及被动构件520的端子521,并且可分别通过孔洞551x、551y及551z而被暴露,并且可被电性连接。传导结构552可包含将电子构件110的内部互连件111以及被动构件520的端子521彼此电性连接的迹线552x。迹线552x可从电子构件110上的一点延伸到被动构件520上的一点以将电子构件110的内部互连件111以及天线组件130的传导端子132彼此电性连接,就像被动构件520一样。迹线552x也可电性连接电子构件110的内部互连件111及天线组件130的传导端子132,就像图2G中所示的传导结构152一样。传导结构552可相似于传导结构152并且可类似于传导结构152来形成。
介电结构553可覆盖介电结构551和传导结构552而成均匀的厚度。暴露传导结构552的顶部表面552b的孔洞553x可被形成在介电结构553中。介电结构553也可经由孔洞553x而暴露迹线552y的顶部表面。介电结构553可相似于介电结构151并且可类似于介电结构151来形成。
虽然只有两个介电结构551和553以及一个传导结构552被显示于基板550中,然而此非本发明的限制。在某些范例中,建造基板550的结构的数量可小于或大于本发明范例所显示的数量。
图8F及图9F显示在制造后段时的半导体装置500。在图8F和图9F所示的范例中,外部互连件160可被形成在传导结构552的顶部表面552b上。
外部互连件160可被电性连接到传导结构552的顶表面552b。外部互连件160可经由基板150而被电性连接到电子构件110、被动构件520或天线组件130。外部互连件160可经由导体152x而被电性连接到电子构件110及天线组件130,或者是外部互连件160可被同时电性连接到电子构件110及被动构件520。外部互连件160可相似于半导体装置100的外部互连件160并且可类似于半导体装置100的外部互连件160来形成。
图11显示范例性半导体装置600的剖面图。如图11中所示的范例,半导体装置600可包括电子构件610、天线组件630、囊封物640、基板650以及外部互连件660。
电子构件610可包含内部互连件611。天线组件630可包含介电结构631、传导结构632及633以及天线图案634。基板650可包含介电结构651及653以及传导结构652。
天线组件630、囊封物640、基板650以及外部互连件660可包含或被称为半导体封装件601或封装件601,并且可保护电子构件610免于受到外部组件或环境暴露的影响。
图12A到图12F显示用于制造范例性半导体装置600的范例性方法的剖面图。图13显示用于制造如图12A中所示的范例性半导体装置600的范例性方法的剖面图。
图12A和图13显示在前段的制造阶段的半导体装置600。在如图12A和图13中所显示的范例中,天线组件630的底部表面630b可被黏接到提供在载体10上的暂时接合层11。
在某些范例中,取放设备可以拾取和放置天线组件630于载体10的暂时接合层11的表面上并且可被黏接到暂时接合层11。在某些范例中,两个天线组件630可被黏接到载体10上,如此以被定位在沿着第二方向y的相对侧处。两个天线组件630可被设置,使得两个天线组件630的内侧表面630c面向彼此并且可彼此分隔开。天线组件630中的每一个可沿着第一方向x纵向延伸。天线组件630可相似于天线组件130并且可类似于天线组件130来形成。天线组件630可以借由图3、图4A、图4B、图5A到图5C以及图6A到图6D中所示的天线组件230、330以及430所使用的布局来改变。或者是,天线组件630可以借由以各种方式任意地配置垂直天线或水平天线来改变。
图12B显示在制造后段时的半导体装置600。在图12B所示的范例中,囊封物640可覆盖载体10和天线组件630。在某些范例中,囊封物640可接触载体10的暂时接合层11的顶部表面以及天线组件630的侧表面。在此处,天线组件630的天线图案634可被暴露。囊封物640可相似于囊封物140并且可类似于囊封物140来形成。
图12C显示在制造后段时的半导体装置600。在图12C所示的范例中,半导体装置600可被翻转以在载体10是位在天线组件630和囊封物640上的情况下移除载体10。
载体10可以从天线组件630的顶部表面630b以及囊封物640的顶部表面640b被移除。因此,天线组件630的顶部表面630b以及囊封物640的顶部表面640b可被暴露。天线组件630的传导图案632也可被暴露。载体10的移除相似于图2E所示的载体10的移除。
图12D显示在制造后段时的半导体装置600。在图12D所示的范例中,基板650可被形成在天线组件630的顶表面630b以及囊封物640的顶表面640b上。在某些范例中,基板650可相似于基板150,或是可包含或被称为基板。基板650可包含介电结构651、传导结构652以及介电结构653并且依序地形成。
介电结构651可覆盖天线组件630的顶部表面630b以及囊封物640的顶部表面640b而成均匀的厚度。暴露天线组件630的传导图案632的孔洞651x可被形成在介电结构651中。介电结构651可经由孔洞651x而暴露天线组件630的传导图案632的顶部表面。介电结构651可相似于介电结构151并且可类似于介电结构151来形成。
传导结构652可以覆盖介电结构651的顶部表面以及经由孔洞651x所暴露的天线组件630的传导图案632。传导结构652可具有多个图案,所述多个图案分别与经由孔洞651x而被暴露的天线组件630的传导图案632接触并且可被电性连接。传导结构652可被电性连接到天线组件630的传导图案632并且可包括沿着囊封物640的顶表面640b延伸的迹线652x。传导结构652可相似于传导结构152并且可类似于传导结构152来形成。
介电结构653可覆盖介电结构651及传导结构652而成均匀的厚度。暴露传导结构652的顶部表面652b的孔洞653x可被形成在介电结构653中。介电结构653也可以经由孔洞653x来暴露迹线652x的顶部表面。介电结构653可相似于介电结构651并且可类似于介电结构651来形成。
虽然只有两个介电结构651和653以及一个传导结构652被显示于基板650中,然而此非本发明的限制。在某些范例中,建造基板650的结构的数量可小于或大于本发明范例所显示的数量。
图12E显示在制造后段时的半导体装置600。在图12E所示的范例中,电子构件610的内部互连件611可电性连接传导结构652的顶部表面652b。电子构件610可被定位在基板650的中央。
在某些范例中,取放设备可以拾取和放置电子构件610到基板650的传导结构652的迹线652x上。之后,电子构件610可利用大批量回焊制程(mass reflow process)、热压制程或薄膜辅助接合制程(film assist bonding process)而被电性连接到基板650的传导结构652。电子构件610可通过基板650的传导结构652而被电性连接到天线组件630。
在某些范例中,电子构件610可包含主动区和非主动区。在某些范例中,主动区可被形成以面向基板650。在某些范例中,主动区可包含内部互连件611。在某些范例中,内部互连件611可包含或是可被称为晶粒垫、接合垫、铝垫、传导柱或是传导杆。
内部互连件611可利用低熔点材料612而被连接到基板650的传导结构652。在某些范例中,低熔点材料612可包含从下面所组成的群组中选出的一个:Sn、Ag、Pb、Cu、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi、Sn-Ag-Cu以及等同物。电子构件610的内部互连件611和基板650的传导结构652可借由所述低熔点材料612而彼此电性连结。电子构件610可具有整体厚度,所述整体厚度在大约0.1mm到大约1mm的范围内。
图12F显示在制造后段时的半导体装置600。在图12F所示的范例中,外部互连件660被形成在传导结构652的顶部表面652b上。外部互连件660可被电性连接到传导结构652的顶部表面652b。
外部互连件660可被设置在电子构件610的外侧处而以具有行或列的矩阵配置的方式彼此分隔开。外部互连件660可经由基板650而被电性连接到电子构件610或天线组件630。外部互连件660可经由迹线652x而被电性连接到电子构件610以及天线组件630。外部互连件660可相似于外部互连件160并且可类似于外部互连件160来形成。
图14显示范例性半导体装置700的剖面图。在图14所示的范例中,半导体装置700可包含电子构件710、被动构件720、天线组件630、囊封物740、基板750以及外部互连件760。
电子构件710可包含内部互连件711。被动构件720可包含端子721。天线组件630可包含介电结构631、传导结构632和133以及天线图案634。基板750可包含介电结构751和653以及传导结构752。
天线组件630、囊封物740、基板750以及外部互连件760可包含或被称为半导体封装件701或封装件701,并且可保护电子构件710免于受到外部组件或环境暴露的影响。半导体封装件701可提供外部组件与电子构件710之间的电性耦接。
图15A到图15G显示用于制造范例性半导体装置700的范例性方法的剖面图。图16A到图16B显示用于制造图15A到图15B所示的范例性半导体装置700的范例性方法的平面图。
图15A和图16A显示在前段的制造阶段的半导体装置700。在图15A和图16A所示的范例中,可备制半导体装置700。如图15A和图16A中所示的半导体装置700可相似于如图12A及图13中所示的由范例性方法所制造的半导体装置600。
图15B显示在制造后段时的半导体装置700。如在图15B所显示的范例中,被动构件720的底部表面720b可被黏接到载体10的暂时接合层11的表面。被动构件720可被定位在两个分隔开的天线组件630的内侧表面630c之间。被动构件720可被设置在载体10的暂时接合层11上而以具有行或列的矩阵配置的方式彼此分隔开,如此以被定位在在第二方向y上为彼此分隔开的两个天线组件630之间并且可被黏接到载体10的暂时接合层11。被动构件720的端子721也可被黏接到暂时接合层11。被动构件720可相似于被动构件520并且可类似于被动构件520来形成。
图15C显示在制造后段时的半导体装置700。如图15C所示的范例中,囊封物740可覆盖载体10、被动构件720以及天线组件630。在某些范例中,囊封物740可接触载体10的暂时接合层11的顶部表面、被动构件720的侧表面以及天线组件630的侧表面。在此处,天线组件630的天线图案634可被暴露。囊封物740可相似于囊封物140并且可类似于囊封物140来形成。
图15D显示在制造后段时的半导体装置700。如图15D所示的范例中,半导体装置700可被翻转,而在当载体10位在天线组件630和囊封物740上的状态之下,移除载体10。
载体10可从天线组件630的顶部表面630b、被动构件720的顶部表面720b以及囊封物740的顶部表面740b而被移除。因此,天线组件630的顶部表面630b、被动构件720的顶部表面720b以及囊封物740的顶部表面740b也可被暴露。被动构件720的端子721以及天线组件630的传导图案632也可被暴露。载体10的移除可相似于如图2E中所示的载体10的移除。
图15E显示在制造后段时的半导体装置700。如图15E所示的范例中,基板750可被形成在天线组件630的顶部表面630b以及囊封物740的顶部表面740b上。在某些范例中,基板650可相似于基板150,或是可包含或被称为基板。基板750可包含介电结构751、传导结构752以及介电结构753并且依序地形成。
介电结构751可覆盖天线组件630的顶部表面630b、被动构件720的顶部表面720b以及囊封物740的顶部表面740b而成均匀的厚度。暴露天线组件630的传导图案632以及被动构件720的端子721的孔洞751x和751y可被形成在介电结构751中。介电结构751也可经由孔洞751x和751y暴露天线组件630的传导图案632以及被动构件720的端子721。介电结构751可相似于介电结构151并且可类似于介电结构151来形成。
传导结构752可覆盖经由孔洞751x和751y所暴露的介电结构751的顶部表面、天线组件630的传导图案632以及被动构件720的端子721。传导结构752可具有多个图案,并且所述多个图案分别与经由孔洞751x和751y所暴露的天线组件630的传导图案632以及被动构件720的端子721接触,并且可以是电性连接。传导结构752可电性连接到被动构件720的端子721并且可包括沿着囊封物740的顶部表面740b延伸的迹线752y。迹线752y可被电性连接到天线组件630的传导图案632(像是如图12D所示的传导结构652)并且可以沿着囊封物740的顶部表面740b延伸。传导结构752可相似于传导结构152并且可类似于传导结构152来形成。
介电结构753可覆盖介电结构751和传导结构752以成为均匀的厚度。暴露传导结构752的顶表面752b的孔洞753x可被形成在介电结构753中。介电结构753也可通过孔洞753x来暴露迹线752y的顶部表面。介电结构753可相似于介电结构751并且可类似于介电结构751来形成。
虽然只有两个介电结构751和753以及一个传导结构752被显示于基板750中,然而此非本发明的限制。在某些范例中,建造基板750的结构的数量可小于或大于本发明范例所显示的数量。
图15F显示在制造后段时的半导体装置700。如图15F所示的范例中,电子构件710的内部互连件711可被电性连接到传导结构752的顶部表面752b。电子构件710可被定位在基板750的中央。电子构件710可被定位在迹线752y上以被电性连接到传导结构752。电子构件710可经由基板750而被电性连接到被动构件720或天线组件730。电子构件710可相似于电子构件610并且可类似于电子构件610而被形成。
图15G显示在制造后段时的半导体装置700。如图15G所示的范例中,外部互连件760可被形成在传导结构752的顶部表面752b上。外部互连件760可被电性连接到传导结构752的顶部表面752b。
外部互连件760可被形成在电子构件710的外侧处而以具有行或列的矩阵配置的方式彼此分隔开。外部互连件760可经由基板750而被电性连接到电子构件710、被动构件720或天线组件730。外部互连件760可经由迹线752y而同时被电性连接到电子构件710以及被动构件720,或者是被电性连接到电子构件710以及天线组件630。外部互连件760可相似于外部互连件160并且可类似于外部互连件160来形成。
本揭示内容包含对某些范例的引用。然而,所属技术领域中具有通常知识者应当理解,在不脱离本揭示内容的范围的情况下,可以作出各种改变并且可以取代等效物。另外,在不脱离本揭示内容的范围的情况下,可以对所揭示的范例进行修改。因此,预期本揭示内容不受限于所公开的范例,而是本揭示内容将包含落入所附申请专利范围的范畴内的所有范例。
Claims (20)
1.一种半导体装置,包括:
基板,包括:
基板顶部侧;
基板底部侧;
基板介电结构,所述基板介电结构在所述基板顶部侧和所述基板底部侧之间;以及
基板传导结构,所述基板传导结构穿越所述基板介电结构并且包括:
第一基板端子;以及
第二基板端子,所述第二基板端子在所述基板顶部侧处;
电子构件,所述电子构件耦接到所述基板并且包括:
耦接到所述第一基板端子的构件端子;
以及
第一天线组件,所述第一天线组件耦接到所述基板并且包括:
第一组件介电结构;
第一天线图案,所述第一天线图案耦接到所述第一组件介电结构;
第一组件端子,所述第一组件端子耦接到所述第二基板端子;
第一组件头侧,所述第一组件头侧相邻于所述第一天线图案;
第一组件基底侧,所述第一组件基底侧相对于所述第一组件侧;以及
第一组件侧壁,所述第一组件侧壁在所述第一组件头侧和所述第一组件基底侧之间;
其中:
所述第一组件端子在所述第一组件基底侧或所述第一组件侧壁中的至少一处从所述第一组件介电结构暴露;
所述第一天线图案经由所述第一组件端子而被耦接到所述基板;
所述第一天线组件耦接到在所述电子构件的覆盖区之外的所述基板;并且
所述基板传导结构耦接所述第一天线组件到所述电子构件。
2.如权利要求1所述的半导体装置,其中:
所述第一天线组件包括:
第一天线路径,所述第一天线路径穿越所述第一组件介电结构并且耦接到所述第一天线图案和所述第一组件端子。
3.如权利要求1所述的半导体装置,其中:
所述第一天线图案被定向成沿着实质上正交于所述第一天线头侧的方向通讯。
4.如权利要求1所述的半导体装置,其中:
所述第一天线组件包括:
面向垂直方向的所述第一组件头侧,及被定向成沿着所述垂直方向通讯的所述第一天线图案;以及
耦接到所述基板的所述第一组件基底侧。
5.如权利要求1所述的半导体装置,其中:
所述第一天线组件包括:
面向第一水平方向的所述第一组件头侧,及被定向成沿着所述第一水平方向通讯的所述第一天线图案;以及
耦接到所述基板的所述第一组件侧壁。
6.如权利要求1所述的半导体装置,包括:
耦接到所述基板的第二天线组件;
其中:
围绕所述电子构件的覆盖区的所述基板包括:
基板向左部分、基板向右部分、基板向上部分以及基板向下部分;
所述第一天线组件在所述基板向左部分处被耦接到所述基板顶部侧;并且
所述第二天线组件在所述基板向右部分处被耦接到所述基板顶部侧。
7.如权利要求6所述的半导体装置,包括:
在所述基板顶部侧上的囊封物;
其中:
所述第二天线组件包括相邻于第二组件头侧的第二天线图案;
所述第二天线组件包括第二组件侧壁;
所述囊封物覆盖所述第一组件侧壁以及所述第二组件侧壁;并且
所述囊封物暴露所述第一组件头侧以及所述第二组件头侧。
8.如权利要求7所述的半导体装置,其中:
所述电子构件包括:
构件第一侧,所述构件第一侧耦接到所述基板顶部侧;
构件第二侧,所述构件第二侧相对于所述构件第一侧;
构件侧壁,所述构件侧壁在所述构件第一侧和所述构件第二侧之间;以及
屏蔽结构,所述屏蔽结构覆盖所述构件第二侧和所述构件侧壁;
并且
所述囊封物覆盖相邻于所述构件侧壁的所述屏蔽结构。
9.如权利要求6所述的半导体装置,其中:
所述第一天线组件包括:
面向垂直方向的所述第一组件头侧,及被定向成沿着所述垂直方向通讯的所述第一天线图案;以及
耦接到所述基板的所述第一组件基底侧;
并且
所述第二天线组件包括:
面向所述垂直方向的第二组件头侧,及被定向成沿着所述垂直方向通讯的第二天线图案;以及
耦接到所述基板的第二组件基底侧。
10.如权利要求6所述的半导体装置,其中:
所述第一天线图案被定向成沿着所述垂直方向朝顶部通讯;
所述第二天线图案被定向成沿着所述垂直方向朝底部通讯。
11.如权利要求6所述的半导体装置,其中:
所述第一天线组件包括:
面向朝右方向的所述第一组件头侧,及被定向成沿着所述朝右方向通讯的所述第一天线图案;以及
耦接到所述基板的所述第一组件侧壁;
并且
所述第二天线组件包括:
面向与所述朝右方向相反的朝左方向的第二组件头侧,及被定向成沿着所述朝左方向通讯的第二天线图案;以及
耦接到所述基板的第二组件侧壁。
12.如权利要求6所述的半导体装置,其中:
所述第一天线组件包括:
面向垂直方向的所述第一组件头侧,及被定向成沿着所述垂直方向通讯的所述第一天线图案;以及
耦接到所述基板的所述第一组件基底侧;
并且
所述第二天线组件包括:
面向朝右方向的第二组件头侧,及被定向成沿着所述朝右方向通讯的第二天线图案;以及
耦接到所述基板的第二组件侧壁。
13.如权利要求12所述的半导体装置,包括:
第三天线组件,所述第三天线组件在所述基板向上部分处耦接到所述基板并且包括:
面向朝上方向的第三组件头侧,及被定向成沿着所述朝上方向通讯的第三天线图案;以及
耦接到所述基板的第三组件侧壁。
14.如权利要求13所述的半导体装置,包括:
第四天线组件,所述第四天线组件在所述基板向下部分处耦接到所述基板并且包括:
面向朝下方向的第四组件头侧,及被定向成沿着所述朝下方向通讯的第四天线图案;以及
耦接到所述基板的第四组件侧壁。
15.如权利要求14所述的半导体装置,包括:
第五天线组件,所述第五天线组件在所述基板向左部分处耦接到所述基板并且包括:
面向朝左方向的第五组件头侧,及被定向成沿着所述朝左方向通讯的第五天线图案;以及
耦接到所述基板的第五组件侧壁。
16.如权利要求15所述的半导体装置,包括:
第六天线组件,所述第六天线组件在所述基板向右部分处耦接到所述基板并且包括:
第六组件头侧,及被定向成沿着所述垂直方向通讯的第六天线图案;以及
耦接到所述基板的第六组件侧壁。
17.如权利要求6所述的半导体装置,其中:
所述电子构件耦接到所述基板底部侧。
18.如权利要求17所述的半导体装置,包括:
被动构件,所述被动构件耦接到所述基板且于所述电子构件上方。
19.如权利要求6所述的半导体装置,包括:
被动构件,所述被动构件耦接到在所述第一天线组件以及所述第二天线组件之间的所述基板顶部侧。
20.一种方法,包括:
提供基板,所述基板包括:
基板顶部侧;
基板底部侧;
基板介电结构,所述基板介电结构在所述基板顶部侧以及所述基板底部侧之间;以及
基板传导结构,所述基板传导结构穿越所述基板介电结构并且包括:
第一基板端子;以及
在所述基板顶部侧处的第二基板端子;
将电子构件耦接到所述基板,所述电子构件包括:
耦接到所述第一基板端子的构件端子;
以及
将第一天线组件耦接到所述基板,所述第一天线组件包括:
第一组件介电结构;
第一天线图案,所述第一天线图案耦接到所述第一组件介电结构;
第一组件端子,所述第一组件端子耦接到所述第二基板端子;
第一组件头侧,所述第一组件头侧相邻于所述第一天线图案;
第一组件基底侧,所述第一组件基底侧相对于所述第一组件侧;以及
第一组件侧壁,所述第一组件侧壁在所述第一组件头侧和所述第一组件基底侧之间;
其中:
所述第一组件端子在所述第一组件基底侧或所述第一组件侧壁中的至少一处从所述第一组件介电结构暴露;
所述第一天线图案经由所述第一组件端子耦接到所述基板;
所述第一天线组件被耦接到在所述电子构件的覆盖区之外的所述基板;并且
所述基板传导结构耦接所述第一天线组件到所述电子构件。
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