CN112599484A - 半导体器件结构及其形成方法 - Google Patents

半导体器件结构及其形成方法 Download PDF

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Publication number
CN112599484A
CN112599484A CN202010511577.4A CN202010511577A CN112599484A CN 112599484 A CN112599484 A CN 112599484A CN 202010511577 A CN202010511577 A CN 202010511577A CN 112599484 A CN112599484 A CN 112599484A
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China
Prior art keywords
buffer layer
bond pad
layer
bump
etch stop
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CN202010511577.4A
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English (en)
Inventor
朱景升
徐晨祐
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112599484A publication Critical patent/CN112599484A/zh
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Abstract

本揭露的各种实施例涉及一种半导体器件结构，所述半导体器件结构包括上覆在结合垫上的凸块结构。结合垫设置在半导体衬底之上。刻蚀停止层上覆在结合垫上。缓冲层设置在结合垫之上且将刻蚀停止层与结合垫隔开。凸块结构包括基部部分及上部部分，基部部分接触结合垫的上表面，上部部分延伸穿过刻蚀停止层及缓冲层。凸块结构的基部部分具有第一宽度或直径且凸块结构的上部部分具有第二宽度或直径。第一宽度或直径大于第二宽度或直径。

Description

半导体器件结构及其形成方法
技术领域
本揭露实施例涉及半导体器件结构及其形成方法。
背景技术
半导体芯片用于各种各样的电子器件及其他器件中且是众所周知的。如今这种芯片的广泛使用以及消费者对更强大及更紧密(compact)的器件的需求要求芯片制造商持续减小这些芯片的实体大小及持续增加这些芯片的功能。这种按比例缩小工艺(scaling-down process)通常通过提高生产效率及降低相关成本来提供有益效果。然而，由于特征大小持续减小，因此制作工艺持续变得更加难以执行。因此，形成大小越来越小的可靠的半导体器件是一项挑战。
发明内容
在本揭露实施例提供一种半导体器件结构。所述半导体器件结构包括：结合垫，设置在半导体衬底之上；刻蚀停止层，上覆在所述结合垫上；缓冲层，设置在所述结合垫之上且将所述刻蚀停止层与所述结合垫隔开；以及凸块结构，包括基部部分及上部部分，所述基部部分接触所述结合垫的上表面，所述上部部分延伸穿过所述刻蚀停止层及所述缓冲层，其中所述凸块结构的所述基部部分具有第一宽度或直径且所述凸块结构的所述上部部分具有第二宽度或直径，所述第一宽度或直径大于所述第二宽度或直径。
在本揭露实施例另提供一种半导体器件结构。所述半导体器件结构包括：内连结构，上覆在衬底上，所述内连结构包括最顶部导电配线；钝化结构，上覆在所述内连结构上；结合垫，上覆在所述最顶部导电配线上，其中所述结合垫延伸穿过所述钝化结构且直接接触所述最顶部导电配线的顶表面，其中所述结合垫具有在垂直方向上位于所述结合垫的顶表面下方的上表面，且其中所述结合垫的所述上表面在垂直方向上位于所述钝化结构的顶表面下方；刻蚀停止层，上覆在所述结合垫及所述钝化结构上；缓冲层，设置在所述刻蚀停止层与所述结合垫之间，其中所述结合垫沿着所述缓冲层的下侧连续地延伸并以杯状包围所述缓冲层的所述下侧；以及凸块结构，包括基部部分及上部部分，所述基部部分接触所述结合垫的所述上表面且设置在所述缓冲层内，所述上部部分从所述基部部分向上延伸且延伸穿过所述刻蚀停止层及所述缓冲层，其中所述基部部分具有在所述缓冲层内界定的第一宽度，且所述上部部分具有在所述缓冲层的顶表面上方界定的第二宽度，且其中所述第一宽度大于所述第二宽度。
在本揭露实施例提供一种形成半导体器件结构的方法。所述形成半导体器件结构的方法包括：在导电配线之上形成钝化结构；在所述导电配线之上形成结合垫，其中所述结合垫悬在所述钝化结构上；在所述结合垫之上沉积缓冲层；在所述缓冲层及所述钝化结构之上沉积刻蚀停止层；在所述刻蚀停止层之上沉积上部介电结构；对所述缓冲层、所述刻蚀停止层及所述上部介电结构执行干式刻蚀工艺，所述干式刻蚀工艺界定上覆在所述结合垫的上表面上的凸块结构开口，其中在所述干式刻蚀工艺之后，所述缓冲层的一部分上覆在所述结合垫的所述上表面上；对所述缓冲层执行湿式刻蚀工艺，所述湿式刻蚀工艺移除所述缓冲层的上覆在所述结合垫的所述上表面上的所述一部分，其中所述湿式刻蚀工艺使所述凸块结构开口扩大且暴露出所述结合垫的所述上表面；以及在所述凸块结构开口中形成凸块结构。
附图说明
结合附图阅读以下详细说明，会最好地理解本揭露的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为使论述清晰起见，可任意增大或减小各种特征的尺寸。
图1示出具有上覆在结合垫(bond pad)上的凸块结构的互补金属氧化物半导体(complementary metal-oxide semiconductor，CMOS)芯片的一些实施例的剖视图，其中结合垫上覆在与半导体器件电耦合的内连结构上。
图2示出上覆在结合垫上的凸块结构的一些实施例的立体图。
图3示出图1的凸块结构的一些替代实施例的剖视图。
图4示出图3的凸块结构的一段的放大视图(close-up view)的一些实施例的剖视图。
图5A及图5B示出图1的凸块结构的一些替代实施例的剖视图。
图6示出具有设置在衬底之上的多个半导体器件、上覆在衬底上的内连结构以及上覆在内连结构上的凸块结构的互补金属氧化物半导体(CMOS)芯片的一些实施例的剖视图。
图7到图18示出形成上覆在结合垫上的凸块结构的方法的一些实施例的剖视图。
图19以流程图的形式示出一种方法，其示出形成上覆在结合垫上的凸块结构的方法的一些实施例。
[符号的说明]
100、600：互补金属氧化物半导体(CMOS)芯片
102：衬底
103、624：源极/漏极区
104：半导体器件
105：栅极电介质
106：内连结构
107：内连介电结构
108、644b、644c、644d：导通孔
109、622：侧壁间隔件
110：导电配线
110a：最顶部导电配线
111：栅极电极
112：钝化结构
114：结合垫
114a：上部结合垫层
114b：下部结合垫层
114c：中心区
114p：外围区
114us、116us、302u：上表面
116：缓冲层
118：刻蚀停止层
118ls：下表面
120：凸块结构
120a：上部导电结构
120b：下部导电结构
120bp：基部部分
120cs：弯曲外侧壁/弯曲侧壁
120cs1：第一弯曲侧壁
120cs2：第二弯曲侧壁
120s1、120s2：侧壁
120ss1：第一倾斜侧壁
120ss2：第二倾斜侧壁
120ss3：第三倾斜侧壁
120u：上部部分
120vs：垂直外侧壁/垂直侧壁
200：立体图
300、400、500a、500b、700、800、900、1000、1100、1200、1300、1400、1500、1600、1700、1800：剖视图
302：下部介电层
304：上部介电层
306：介电结构
402：第一水平线
404：第二水平线
602：第一半导体器件区
604：第二半导体器件区
608：浅沟槽隔离(STI)区
610、611、612：晶体管
614：栅极电极
618：栅极介电层
626a、626b、626c、626d：金属间介电(IMD)层
626e：金属间介电(IMD)层/最顶部IMD层
638a：导电配线层/底部导电配线层
638b、638c：导电配线层
638d：导电配线层/最上部导电配线层
640：介电保护层
644a：导通孔/底部导通孔
650：深沟槽隔离结构
660：导电结合结构
702、906、1102、1404：掩蔽层
802：结合垫开口
902：导电层
904：金属保护层
1202：深沟槽隔离结构开口
1402：上部介电结构
1502：凸块结构开口
1900：方法
1902、1904、1906、1908、1910、1912、1914、1916：动作
α：第一角度
β：第二角度
ф：第三角度
d1：横向距离
h1：第一高度
h2：第二高度
h3：第三高度
hbs：高度
tbl、tbl’、tbp、tel：厚度
w1：第一宽度
w2：第二宽度
v1：非零垂直距离
具体实施方式
以下公开提供用于实施所提供主题的不同特征的许多不同实施例或实例。以下阐述组件及布置的具体实例以简化本揭露。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成在第二特征之上或第二特征上可包括其中第一特征与第二特征被形成为直接接触的实施例，且也还包括其中第一特征与第二特征之间可形成有附加特征从而使得所述第一特征与所述第二特征可不直接接触的实施例。另外，本揭露可能在各种实例中重复使用参考编号和/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身指示所论述的各种实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在...之下(beneath)”、“在...下方(below)”、“下部的(lower)”、“在...上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括器件在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)，且本文中所使用的空间相对性描述语可同样相应地进行解释。
典型的互补金属氧化物半导体(CMOS)管芯包括上覆在衬底上的内连结构。一个或多个半导体器件(例如，晶体管、变容器(varactor)、电阻器、电容器)布置在衬底中、衬底上或衬底之上且通过内连结构电耦合到一个或多个结合垫。凸块结构直接上覆在每一结合垫上且被配置成有利于通过例如金属结合工艺电耦合到印刷电路板(printed circuitboard，PCB)或另一CMOS管芯。
一种形成凸块结构的方法包括直接在内连结构中在最顶部导电层之上形成结合垫。在结合垫之上形成刻蚀停止层，且在刻蚀停止层之上形成氧化物层。根据掩蔽层(masking layer)执行第一刻蚀(例如，等离子体刻蚀)以移除刻蚀停止层的一部分及氧化物层的一部分，从而界定暴露出结合垫的上表面的凸块结构开口。为了确保第一刻蚀从结合垫的上表面清除刻蚀停止层，第一刻蚀会轻微地刻蚀到结合垫中。遗憾的是，如在本揭露的一些方面中所理解，当通过第一刻蚀移除此结合垫材料(例如，铝)时，结合垫材料和/或其副产物可再沉积到凸块结构开口中的刻蚀停止层的侧壁上及氧化物层的侧壁上。此外，在一些情况下，此第一刻蚀可包含氟自由基(fluorine free radical)。当氟自由基与结合垫的材料接触时，氟与结合垫材料可发生反应而在结合垫的上表面上形成副产物。这些副产物可随后与周围环境中的湿气发生反应而产生氢氟酸(hydrofluoric acid，HF)，氢氟酸将腐蚀结合垫的上表面，从而使得结合垫的上表面被损坏且变得粗糙。可执行氩轰击工艺(argon bombardment process)来移除这种腐蚀，但是这会增加制造工艺的时间及成本。
然后在结合垫的上表面上形成例如凸块结构(例如焊料凸块)。在形成凸块结构之后，通过第二刻蚀(例如，包括刻蚀剂(例如，氢氟酸)的蒸汽刻蚀(vapor etch))来移除剩余的氧化物层。在第二刻蚀期间，凸块结构的侧壁上的再沉积材料(例如，铝)可能从凸块结构掉落或剥落(peel off)到相邻的结构上。由于再沉积材料是导电的，因此这些材料可将相邻的导电结构和/或相邻的凸块结构电短路在一起，从而使得CMOS管芯上的器件不可操作。此外，即使再沉积材料留在适当的位置，结合垫的被损坏的/粗糙的上表面也会导致长期的可靠性问题，例如由于粘着问题和/或焊料凸块与结合垫之间的电阻增加而导致长期的可靠性问题。
在本揭露的一些实施例中，为了消除材料从结合垫再沉积到凸块结构的侧壁上且为了在结合垫与焊料凸块之间提供良好的界面，可在形成刻蚀停止层之前在结合垫之上形成缓冲层。因此，在形成缓冲层之后，可在缓冲层之上形成刻蚀停止层，且可在刻蚀停止层之上形成氧化物层。执行第一刻蚀(例如，包含氟自由基的等离子体刻蚀)以移除氧化物层的一部分及刻蚀停止层的一部分，从而界定暴露出缓冲层的上表面的凸块结构开口。由于第一刻蚀在缓冲层上停止，因此第一刻蚀不会与结合垫接触且将不会导致结合垫材料再沉积到凸块结构开口的侧壁上。然后执行第二刻蚀(例如，湿式刻蚀)以通过移除缓冲层的暴露部分来使凸块结构开口延伸从而暴露出结合垫的上表面。由于此第二刻蚀是湿式刻蚀，因此其可对刻蚀停止层进行底切(undercut)且留下具有干净侧壁的延伸的凸块结构开口(即，沿着凸块结构开口的侧壁不存在来自结合垫的再沉积材料)。另外，凭借湿式刻蚀工艺，上部结合垫表面是光滑的且为凸块结构提供良好的接触界面。因此，当随后在结合垫之上形成凸块结构且执行第三刻蚀工艺(例如，包含刻蚀剂(例如氢氟酸))以移除剩余的氧化物层时，结果会在结合垫与凸块结构之间实现良好的实体接触及电接触。
参照图1，提供互补金属氧化物半导体(CMOS)芯片100的一些实施例的剖视图，所述互补金属氧化物半导体芯片100具有上覆在结合垫114上的凸块结构120。
CMOS芯片100包括衬底102、内连结构106及通过结合垫114电耦合到内连结构106的凸块结构120。在衬底102上设置有半导体器件104。半导体器件104可例如为晶体管。在前述实例中，半导体器件104可包括：源极/漏极区103，设置在衬底102中；栅极电介质105，设置在源极/漏极区103之间；栅极电极111，上覆在栅极电介质105上；以及侧壁间隔件109，设置在栅极电极111的侧壁及栅极电介质105的侧壁周围。半导体器件104通过内连结构106电耦合到上覆的金属层、上覆的电子器件(例如，存储单元、金属-绝缘体-金属电容器、电阻器等)、和/或另一CMOS管芯。
内连结构106包括多个导通孔(conductive via)108、多个导电配线110及内连介电结构107。导通孔108及导电配线110设置在内连介电结构107内且被配置成将半导体器件104电耦合到上覆的导电结构。最顶部导电配线110a直接位于结合垫114之下。
在内连结构106上上覆有钝化结构112。结合垫114从钝化结构112的顶表面延伸到最顶部导电配线110a。在结合垫114的上表面114us上上覆有缓冲层116。刻蚀停止层118在钝化结构112、结合垫114及缓冲层116之上连续地延伸。在结合垫114上直接上覆有凸块结构120。凸块结构120被配置成将结合垫114电耦合到另一CMOS管芯(未示出)。在一些实施例中，结合垫114的上表面114us包括外围区114p及中心区114c；且结合垫114的外围区114p的上部部分悬在钝化结构112上。外围区114p的上表面具有从衬底102的上表面测量的第一高度h1，且中心区114c的上表面具有从衬底102的上表面测量的第二高度h2。第一高度h1大于第二高度h2。
凸块结构120包括基部部分120bp及上部部分120u，基部部分120b与结合垫114的上表面114us直接接触，上部部分120u向上延伸穿过刻蚀停止层118。在一些情形中，凸块结构120的基部部分120bp在第三高度h3处与凸块结构120的上部部分120u交会，所述第三高度h3小于第一高度h1且大于第二高度h2。基部部分120bp界定在弯曲外侧壁(也称为弯曲侧壁)120cs之间；且上部部分120u界定在垂直外侧壁(也称为垂直侧壁)120vs之间。弯曲侧壁120cs设置在缓冲层116内。垂直侧壁120vs从缓冲层116的顶表面延伸到与凸块结构120的顶表面对应的点。在一些实施例中，凸块结构120的相对的侧壁120s1、120s2是根据剖视图界定。举例来说，如果当从上方观察时凸块结构120是圆形的/椭圆形的，则当从上方观察时，相对的侧壁120s1、120s2是单个连续侧壁，因此当在剖视图中绘示时，相对的“侧壁”120s1、120s2指的是此单个连续侧壁自然会呈现出的两个侧壁。另外，如果当从上方观察时，凸块结构120是圆形的或椭圆形的，则与包括凸块结构120的结构和/或层的剖视图相关联的任何长度和/或宽度分别与圆的直径或在椭圆主轴上的两个顶点之间界定的长度对应。
通过在缓冲层116中设置弯曲侧壁120cs，在制作CMOS芯片100期间，导电材料从结合垫114到凸块结构120的相对的侧壁120s1、120s2的再沉积得到减轻。通过减轻来自结合垫114的导电材料的再沉积，凸块结构120与相邻的导电结构电隔离，且因此会提高CMOS芯片100的良率。此外，通过在刻蚀停止层118与结合垫114之间设置缓冲层116，用于制作CMOS芯片100的处理步骤的数目得到减少和/或消除。这在某种程度上减少与制作CMOS芯片100相关联的良率损失、时间及成本。
参照图2，提供图1的凸块结构120的一些实施例的立体图200。如图2中所示，凸块结构120具有圆柱形状。因此，凸块结构120的基部部分(图1：基部部分120bp)及凸块结构120的上部部分(图1：上部部分120u)二者为圆柱形，其中基部部分(图1：基部部分120bp)的宽度或直径大于上部部分(图1：上部部分120u)的宽度或直径。尽管在图2中不可见，但是结合垫(图1：结合垫114)具有矩形/正方形形状，使得凸块结构120布置在结合垫(图1：结合垫114)的内侧壁之间。凸块结构120的顶表面在垂直方向上位于结合垫(图1：结合垫114)的顶表面上方。
参照图3，提供图1的凸块结构120的一些实施例的剖视图300。
在刻蚀停止层118及凸块结构120之上设置有介电结构306。在一些实施例中，介电结构306可例如为或包含氧化物(例如，二氧化硅、氧化金、另一种合适的氧化物等)。在又一些实施例中，介电结构306被省略。结合垫114的下部部分设置在钝化结构112内。钝化结构112包括上部介电层304及下部介电层302。上部介电层304可例如为或包含二氧化硅、硅玻璃、未经掺杂的硅玻璃等，和/或可具有介于约5,500埃到6,500埃的范围内的厚度。下部介电层302可例如为或包含碳化硅、氮化硅等，和/或可具有介于约1,000埃到1,500埃的范围内的厚度。在钝化结构112上上覆有刻蚀停止层118。在一些实施例中，刻蚀停止层118可例如为或包含氧化铝、另一种合适的氧化物等。刻蚀停止层118具有厚度tel，厚度tel可例如介于约100埃到1,000埃的范围内。
在一些实施例中，结合垫114可例如为或包含铝、铜、铝铜、氮化钽等。在一些实施例中，结合垫114可具有在下部介电层302的底表面与凸块结构120的底表面之间界定的厚度tbp。厚度tbp可例如介于约1,000埃到8,000埃的范围内。在又一些实施例中，结合垫114可例如包括包含第一材料(例如，铝铜)的第一导电层以及包含与第一材料不同的第二材料(例如，氮化钽)的第二导电层。第一导电层直接上覆在第二导电层上，例如，参见图5B的上部结合垫层114a及下部结合垫层114b。
在刻蚀停止层118与结合垫114的上表面114us之间设置有缓冲层116。在一些实施例中，缓冲层116可例如为或包含氮化物(例如，氮化钛、氮化钽、氮化硅或氮氧化硅)、或氧化物(例如，氧化钛、二氧化硅或氮氧化硅)、钛等，和/或可具有介于约100埃到1,000埃的范围内的厚度tbl。在一些实施例中，如果厚度tbl为100埃或大于100埃，则可在凸块结构120的制作期间利用湿式刻蚀工艺来暴露出结合垫114的上表面114us。在再一些实施例中，如果厚度tbl为1,000埃或小于约1,000埃，则可在执行等离子体刻蚀(在凸块结构120的制作期间)以移除刻蚀停止层118的一部分的同时保护结合垫114的上表面114us。在一些实施例中，如果厚度tbl大于1,000埃，则在沉积工艺期间缓冲层116可能易于由于颗粒缺陷而损坏。这可继而导致缓冲层116与相邻的层之间的分层(delamination)。凭借缓冲层116的厚度tbl及材料，在凸块结构120的制作期间，从结合垫114到凸块结构120的相对的侧壁120s1、120s2的导电材料的再沉积得到减轻。此外，在等离子体刻蚀工艺期间对结合垫114的上表面114us进行保护的缓冲层116会减轻和/或消除结合垫114的上表面114us的腐蚀(例如，结合垫缺陷问题)。这会减轻和/或省略结合垫114的上表面114us上的处理工艺(例如，氩轰击工艺)的利用，从而减少与制作结合垫114和/或凸块结构120相关联的良率损失、时间及成本。在一些实施例中，相对的侧壁120s1、120s2的弯曲侧壁的高度等于厚度tbl。
在一些实施例中，凸块结构120可例如为或包含镍、金等，和/或可具有介于约3,000埃到10,000埃的范围内的高度hbs。凸块结构120具有在相对的侧壁120s1、120s2的垂直侧壁之间界定的第一宽度w1。在一些实施例中，第一宽度w1介于约1微米到5微米的范围内。凸块结构具有在相对的侧壁120s1、120s2的弯曲侧壁之间界定的第二宽度w2。在一些实施例中，第二宽度w2介于约1.01微米到5.06微米的范围内。在又一些实施例中，第二宽度w2大于第一宽度w1。
在一些实施例中，凸块结构120具有在相对的侧壁120s1、120s2的垂直侧壁与相对的侧壁120s1、120s2的弯曲侧壁的外侧点之间界定的横向距离d1。在一些实施例中，横向距离d1介于约50埃到300埃的范围内。在又一些实施例中，横向距离d1的值与缓冲层116的厚度tbl相关。举例来说，如果厚度tbl为相对薄的(例如，近似100埃)，则横向距离d1可为相对小的(例如，近似50埃)。在另一实例中，如果厚度tbl为相对厚的(例如，近似1,000埃)，则横向距离d1可为相对大的(例如，近似300埃)。
参照图4，提供图3的凸块结构120的一段(如图3中的虚线框所示)的放大视图的一些实施例的剖视图400。
如图4中所示，凸块结构120与缓冲层116的底切轮廓及刻蚀停止层118的底切轮廓共形。凸块结构120的侧壁120s2包括第一倾斜侧壁120ss1、第二倾斜侧壁120ss2、第一弯曲侧壁120cs1、第二弯曲侧壁120cs2及第三倾斜侧壁120ss3。第一倾斜侧壁120ss1具有在结合垫114的上表面114us与凸块结构120之间界定的第一角度α。在一些实施例中，第一角度α介于近似10度到60度的范围内。第二倾斜侧壁120ss2具有在凸块结构120与第一水平线402之间界定的第二角度β。在一些实施例中，第二角度β介于近似10度到80度的范围内。在又一些实施例中，第一角度α小于第二角度β。第一弯曲侧壁120cs1与缓冲层116的弯曲底切部分直接接触。第二弯曲侧壁120cs2直接上覆在第一弯曲侧壁120cs1上且与刻蚀停止层118的底切部分直接接触。第三倾斜侧壁120ss3具有在凸块结构120与第二水平线404之间界定的第三角度ф。在一些实施例中，第三角度ф介于近似10度到90度的范围内。凸块结构120的侧壁120s2的前述侧壁可由在凸块结构120的制作期间利用的一种或多种刻蚀工艺来界定。
参照图5A，提供图3的凸块结构120的替代实施例的剖视图500a。
凸块结构120包括上部导电结构120a及下部导电结构120b。在一些实施例中，上部导电结构120a包含第一材料且下部导电结构120b包含与第一材料不同的第二材料。举例来说，上部导电结构120a的第一材料可为或包含金且下部导电结构120b的第二材料可为或包含镍。上部导电结构120a的相对的侧壁分别包括连续的、直的垂直侧壁。下部导电结构120b的相对的侧壁分别包括直接上覆在弯曲侧壁上的连续的、直的垂直侧壁。
参照图5B，提供图3的凸块结构120的替代实施例的剖视图500b。
结合垫114包括上部结合垫层114a及位于上部结合垫层114a之下的下部结合垫层114b。上部结合垫层114a包含第一结合垫材料且下部结合垫层114b包含与第一结合垫材料不同的第二结合垫材料。在一些实施例中，第一结合垫材料可例如为或包含铝、铜、铝铜等。在一些实施例中，第二结合垫材料可例如为或包含钽、氮化物、氮化钽等。上部结合垫层114a直接接触缓冲层116及凸块结构120。
参照图6，提供互补金属氧化物半导体(CMOS)芯片600的剖视图，所述互补金属氧化物半导体芯片600包括上覆在内连结构106上的多个凸块结构120。
CMOS芯片600包括衬底102。衬底102可例如为块状衬底(例如，块状硅衬底)或绝缘体上硅(silicon-on-insulator，SOI)衬底。所示实施例绘示出可在衬底102内包括电介质填充沟槽的一个或多个浅沟槽隔离(shallow trench isolation，STI)区608。
在第一半导体器件区602中在STI区608之间设置有晶体管610、611。在第二半导体器件区604中相邻于STI区608设置有晶体管612。在一些实施例中，第一半导体器件区602可为存储器阵列区(包括设置在内连结构106中的存储单元)且第二半导体器件区604可为逻辑区。在又一些实施例中，第一半导体器件区602通过深沟槽隔离结构650而与第二半导体器件区604隔开。晶体管610、611、612分别包括栅极电极614、栅极介电层618、侧壁间隔件622及源极/漏极区624。源极/漏极区624在衬底102内设置于每一栅极电极614的任一侧上，且被掺杂成具有与每一栅极介电层618下面的沟道区的第二导电类型(例如，p型)相反的第一导电类型(例如，n型)。栅极电极614可例如分别为经掺杂的多晶硅或金属(例如钨)、硅化物、或其组合。栅极介电层618可例如各自为或包含氧化物(例如，二氧化硅)、或高介电常数介电材料。如本文中所用，高介电常数介电材料是介电常数大于3.9的介电材料。侧壁间隔件622可例如由氮化硅制成。
内连结构106布置在衬底102之上且包括多个金属间介电(inter-metaldielectric，IMD)层626a到626e、多个导电配线层638a到638d及多个导通孔644a到644d。IMD层626a到626e可例如分别由低介电常数介电材料(例如，未经掺杂的硅酸盐玻璃)或氧化物(例如，二氧化硅)制成。如本文中所用，低介电常数介电材料是介电常数小于3.9的介电材料。导电配线层638a到638d形成在沟槽内且可由金属(例如铜、铝等)制成。导通孔(也称为底部导通孔)644a从导电配线层(也称为底部导电配线层)638a延伸到源极/漏极区624和/或栅极电极614；且导通孔644b到644d在导电配线层638b到638d之间延伸。导通孔644a到644d延伸穿过介电保护层640(其可由介电材料制成和/或可在制造期间充当刻蚀停止层)。介电保护层640可例如由氮化物(例如，氮化硅)、碳化物(例如，碳化硅)、氧化物(例如，氮氧化硅)等制成。导通孔644a到644d可例如各自由金属(例如铜、钨等)制成。
在IMD层(也称为最顶部IMD层)626e上上覆有钝化结构112。结合垫114从钝化结构112的顶表面延伸到导电配线层(也称为最上部导电配线层)638d。在每一结合垫114上上覆有缓冲层116且在缓冲层116上上覆有刻蚀停止层118。刻蚀停止层118从钝化结构112连续地延伸到衬底102的顶表面下方。刻蚀停止层118以杯状包围深沟槽隔离结构650的下侧。在每一结合垫114上上覆有凸块结构120，使得凸块结构120通过内连结构106电耦合到晶体管610、611、612的源极/漏极区624。在一些实施例中，凸块结构120各自被配置成图5A的凸块结构120，其中每一凸块结构120具有上部导电结构120a及下部导电结构120b。凸块结构120被配置成有利于将晶体管610、611、612耦合到另一集成芯片(未示出)。在相邻的凸块结构120之间在横向上设置有导电结合结构660。导电结合结构660被配置成有利于将凸块结构120结合到另一集成芯片(未示出)。在一些实施例中，导电结合结构660可例如为或包含与结合垫114相同的材料。
图7到图18示出形成上覆在结合垫上的凸块结构的方法的一些实施例的剖视图700到剖视图1800。尽管参照方法来阐述图7到图18中所示的剖视图700到剖视图1800，然而应理解，图7到图18中所示的结构并不仅限于所述方法，而是可单独地独立于所述方法。此外，尽管图7到图18被阐述为一系列动作，然而应理解，这些动作并不是限制性的，这是因为在其他实施例中可改变所述动作的次序，且所公开的方法也可适用于其他结构。在其他实施例中，可全部或部分地省略所示出和/或所阐述的一些动作。
如图7的剖视图700中所示，提供上覆在衬底102上的内连介电结构107。在内连介电结构107内设置最顶部导电配线110a且最顶部导电配线110a上覆在衬底102上。在最顶部导电配线110a之上形成钝化结构112。在一些实施例中，钝化结构112包括上部介电层304及下部介电层302。在上部介电层304之上形成掩蔽层702，以使得上部介电层304的一部分暴露出来。上部介电层304可例如为或包含二氧化硅、硅玻璃、未经掺杂的硅玻璃等且被形成为介于约5,500埃到6,500埃的范围内的厚度。下部介电层302可例如为或包含碳化硅、氮化硅等且被形成为介于约1,000到1,500埃的范围内的厚度。上部介电层304和/或下部介电层302可例如通过化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积(physical vapor deposition，PVD)、原子层沉积(atomic layer deposition，ALD)、热氧化、或另一种合适的沉积工艺形成。掩蔽层702可例如为或包括硬掩模层、光刻胶等。
如图8的剖视图800中所示，根据掩蔽层(图7的掩蔽层702)将钝化结构112图案化，从而界定结合垫开口802且暴露出最顶部导电配线110a的上表面。在一些实施例中，图案化工艺包括将上部介电层304及下部介电层302的未被掩蔽的区暴露到一种或多种刻蚀剂。在再一些实施例中，在形成结合垫开口802之后，执行移除工艺以移除掩蔽层(图7的掩蔽层702)。
在一些实施例中，图案化工艺包括选择性刻蚀工艺，所述选择性刻蚀工艺包括对上部介电层304执行第一刻蚀(例如，干式刻蚀)直到暴露出下部介电层302的上表面302u。在一些实施例中，第一刻蚀可对下部介电层302的一部分进行过刻蚀(over etch)且移除下部介电层302的所述一部分，以使得下部介电层302的上表面302u设置在上部介电层304的底表面下方。此外，在执行第一刻蚀之后，对下部介电层302执行第二刻蚀(例如，湿式刻蚀)直到暴露出最顶部导电配线110a的上表面。
如图9的剖视图900中所示，在钝化结构112及最顶部导电配线110a之上形成导电层902及金属保护层904。导电层902及金属保护层904填充结合垫开口(图8的结合垫开口802)。在金属保护层904之上形成掩蔽层906。在一些实施例中，掩蔽层906可例如为光刻胶、硬掩模层等。导电层902可例如为或包含铝、铜、铝铜、氮化钽等且被形成为介于约1,000埃到8,000埃的范围内的厚度。在又一些实施例中，导电层902可例如包括包含第一材料(例如铝铜)的第一导电层及包含与第一材料(未示出)不同的第二材料(例如氮化钽)的第二导电层。在一些实施例中，金属保护层904可例如为或包含氮氧化硅、碳化硅、氮化硅等且被形成为介于约250埃到350埃的范围内的厚度。
如图10的剖视图1000中所示，根据掩蔽层(图9的掩蔽层906)将导电层(图9的导电层902)及金属保护层904图案化，从而界定结合垫114及导电结合结构660。导电结合结构660与结合垫114在横向上偏置开非零距离。在一些实施例中，在形成结合垫114及导电结合结构660之后，执行移除工艺以移除掩蔽层(图9的掩蔽层906)。
如图11的剖视图1100中所示，在钝化结构112及结合垫114之上形成掩蔽层1102。掩蔽层1102可例如为光刻胶、硬掩模等。
如图12的剖视图1200中所示，根据掩蔽层(图11的掩蔽层1102)将钝化结构112、内连介电结构107及衬底102图案化，从而界定深沟槽隔离结构开口1202。在一些实施例中，图案化工艺包括例如执行高功率等离子体刻蚀工艺，以移除位于上部介电层304的未被掩蔽的区下面以及设置在钝化结构112与衬底102之间的介电材料。在一些实施例中，深沟槽隔离结构开口1202界定在集成芯片(未示出)的存储器阵列区与逻辑区之间。在一些实施例中，在执行图案化工艺之后，执行移除工艺以移除掩蔽层(图11的掩蔽层1102)。
如图13的剖视图1300中所示，移除金属保护层(图12的金属保护层904)，从而暴露出结合垫114的上表面及导电结合结构660的上表面。
如图14的剖视图1400中所示，在结合垫114的上表面之上形成缓冲层116。在一些实施例中，缓冲层116可例如为或包含氮化物(例如，氮化钛、氮化钽、氮化硅或氮氧化硅)、或氧化物(例如，氧化钛、二氧化硅或氮氧化硅)、钛等，和/或可被形成有介于约100埃到1,000埃的范围内的厚度tbl。在一些实施例中，缓冲层116可通过CVD、PVD、ALD、热氧化、或另一种合适的沉积工艺来沉积和/或生长。在缓冲层116、钝化结构112及衬底102之上形成刻蚀停止层118。在一些实施例中，刻蚀停止层118可例如为或包含氧化铝、氮氧化硅、另一种合适的氧化物等且被形成为介于约100埃到1,000埃的范围内的厚度。在一些实施例中，刻蚀停止层118与缓冲层116具有相同的厚度。刻蚀停止层118对深沟槽隔离结构开口(图13的深沟槽隔离结构开口1202)进行衬垫，以使得刻蚀停止层118从结合垫114上方连续地延伸到衬底102的沟槽。在一些实施例中，刻蚀停止层118可通过CVD、PVD、ALD、热氧化、或另一种合适的沉积工艺来沉积和/或生长。
此外，如图14的剖视图1400中所示，在刻蚀停止层118之上形成上部介电结构1402。上部介电结构1402可例如为或包含氧化金、二氧化硅、另一种氧化物等。上部介电结构1402填充深沟槽隔离结构开口(图13的深沟槽隔离结构开口1202)。在一些实施例中，上部介电结构1402可通过CVD、PVD、ALD、热氧化、或另一种合适的沉积工艺来沉积和/或生长。在上部介电结构1402之上形成掩蔽层1404。在一些实施例中，掩蔽层1404可例如为硬掩模、光刻胶等。掩蔽层1404在结合垫114上方界定开口。
如图15的剖视图1500中所示，根据掩蔽层1404将图14的结构图案化，从而在缓冲层116之上界定凸块结构开口1502。图案化工艺可包括对上部介电结构1402的未被掩蔽的部分及刻蚀停止层118的未被掩蔽的部分执行干式刻蚀工艺(例如，等离子体刻蚀工艺)。在一些实施例中，干式刻蚀工艺包括将上部介电结构1402及刻蚀停止层118暴露到一种或多种刻蚀剂，例如四氟甲烷(tetrafluoromethane，CF4)、三氟甲烷(trifluoromethane，CHF3)、二氟甲烷(difluoromethane，CH2F2)、六氟化硫(sulfur hexafluoride，SF6)、六氟环丁烯(hexafluorocyclobutene，C4F6)、八氟环戊烯(octafluorocyclopentene，C5F8)、八氟环丁烷(octafluorocyclobutane，C4F8)等。在一些实施例中，干式刻蚀工艺可对缓冲层116的一部分进行过刻蚀且移除缓冲层116的所述一部分，以使得缓冲层116的上表面116us与刻蚀停止层118的下表面118ls在垂直方向上偏置开非零垂直距离v1。因此，干式刻蚀工艺可将缓冲层116在结合垫114的上表面正上方的厚度tbl减小到减小的厚度tbl’。减小的厚度tbl’可例如介于约50埃到900埃的范围内。在又一些实施例中，上部介电结构1402的侧壁及刻蚀停止层118的侧壁是倾斜的(未示出)。
在一些实施例中，凭借缓冲层116的厚度tbl及材料，结合垫114的上表面被保护免受干式刻蚀工艺。举例来说，如果厚度tbl为100埃或大于100埃，则在干式刻蚀工艺期间移除刻蚀停止层118的一部分之后，缓冲层116的至少一部分将保留在结合垫114的上表面之上。这在某种程度上防止导电材料(例如，铝)从结合垫114再沉积到刻蚀停止层118的侧壁及上部介电结构1402的侧壁，同时减少用于形成凸块结构开口1502的材料。这在某种程度上防止导电材料(例如，铝)从结合垫114再沉积到刻蚀停止层118的侧壁及上部介电结构1402的侧壁，同时有利于在干式刻蚀工艺期间使用高功率刻蚀(即，减少制作时间)。此外，在干式刻蚀工艺期间对结合垫114的上表面进行保护的缓冲层116会减轻和/或消除结合垫114的上表面上的处理工艺(例如，利用氩蒸汽(argon vapor))的利用。这在某种程度上减少与制作结合垫114及上覆的凸块结构(例如，图17的凸块结构120)相关联的时间、成本及良率损失。
如图16的剖视图1600中所示，对图15的结构执行刻蚀工艺，从而使凸块结构开口1502进一步扩大且暴露出结合垫114的上表面。在刻蚀工艺之后，缓冲层116包括直接上覆在结合垫114的上表面上的弯曲侧壁和/或倾斜侧壁(未示出)。刻蚀工艺可包括利用一种或多种刻蚀剂的湿式刻蚀工艺。在一些实施例中，所述一种或多种刻蚀剂可例如为或包含过氧化氢(hydrogen peroxide，H2O2)。湿式刻蚀工艺可例如达到70摄氏度的最大温度。在一些实施例中，刻蚀工艺对缓冲层116是选择性的，这意味着缓冲层116的材料被所述一种或多种刻蚀剂以第一移除速率刻蚀，且刻蚀停止层118的材料、上部介电结构1402的材料和/或结合垫114的材料被所述一种或多种刻蚀剂以第二移除速率刻蚀，第二移除速率远小于第一移除速率。在一些实施例中，在暴露出结合垫114的上表面的刻蚀工艺期间，来自结合垫114的导电材料(例如，铝)不会再沉积到界定凸块结构开口1502的缓冲层116的侧壁上、刻蚀停止层118的侧壁上和/或上部介电结构1402的侧壁上。在又一些实施例中，在执行刻蚀工艺之后，执行移除工艺以移除掩蔽层1404(未示出)。
如图17的剖视图1700中所示，在凸块结构开口(图16的凸块结构开口1502)中形成凸块结构120。在一些实施例中，用于形成凸块结构120的工艺可包括：直接在结合垫114之上形成下部导电结构120b，以使得下部导电结构120b与缓冲层116的弯曲侧壁和/或倾斜侧壁(未示出)共形和/或直接接触缓冲层116的弯曲侧壁和/或倾斜侧壁(未示出)；以及随后在下部导电结构120b之上形成上部导电结构120a。在又一些实施例中，上部导电结构120a包含与下部导电结构120b的第二材料(例如，镍)不同的第一材料(例如，金)。
如图18的剖视图1800中所示，执行刻蚀工艺以移除上部介电结构(图17的上部介电结构1402)。在一些实施例中，刻蚀工艺包括执行将图17的结构暴露到一种或多种刻蚀剂的蒸汽刻蚀和/或湿式刻蚀。所述一种或多种刻蚀剂可例如为或包含氢氟酸。在再一些实施例中，在以所述一种或多种刻蚀剂(例如氢氟酸)执行刻蚀工艺之后，沿着凸块结构120的相对的侧壁120s1、120s2的导电材料不会被剥落和/或与相邻的导电结构(例如，导电结合结构660)一起电短路。因此，由于缓冲层116保护结合垫114的上表面且由于使用湿式刻蚀工艺暴露出结合垫114的上表面，因而导电材料从相对的侧壁120s1、120s2的剥落得以减轻和/或不会发生。
图19示出形成上覆在结合垫上的凸块结构的方法1900。尽管方法1900被示出和/或阐述为一系列动作或事件，然而应理解，所述方法并非仅限于所示次序或动作。因此，在一些实施例中，这些动作可以与所示不同的次序施行，和/或可同时施行。此外，在一些实施例中，所示动作或事件可被细分为多个动作或事件，这些动作或事件可在单独的时间施行或者与其他动作或子动作同时施行。在一些实施例中，可省略一些所示动作或事件，且可包括其他未示出的动作或事件。
在动作1902处，提供包括上覆在衬底上的最顶部导电配线层的内连结构，且在最顶部导电配线层之上形成钝化结构。图7示出与动作1902的一些实施例对应的剖视图700。
在动作1904处，在最顶部导电配线层之上形成结合垫。结合垫悬在钝化结构上且直接接触最顶部导电配线。图8到图10示出与动作1904的一些实施例对应的剖视图800到剖视图1000。
在动作1906处，将内连结构及衬底图案化，从而界定深沟槽隔离结构开口。深沟槽隔离结构开口与结合垫在横向上偏置开非零距离。图11及图12示出与动作1906的一些实施例对应的剖视图1100及剖视图1200。
在动作1908处，在结合垫之上沉积缓冲层，在缓冲层之上沉积刻蚀停止层，且在刻蚀停止层之上沉积上部介电结构。刻蚀停止层对深沟槽隔离结构开口进行衬垫。图14示出与动作1908的一些实施例对应的剖视图1400。
在动作1910处，对缓冲层、刻蚀停止层及上部介电结构执行干式刻蚀，从而界定凸块结构开口。图15示出与动作1910的一些实施例对应的剖视图1500。
在动作1912处，对缓冲层执行湿式刻蚀，从而使凸块结构开口扩大且暴露出结合垫的上表面。图16示出与动作1912的一些实施例对应的剖视图1600。
在动作1914处，在凸块结构开口中形成凸块结构。图17示出与动作1914的一些实施例对应的剖视图1700。
在动作1916处，将上部介电结构图案化，从而暴露出凸块结构的侧壁。图18示出与动作1916的一些实施例对应的剖视图1800。
因此，在一些实施例中，本揭露涉及一种包括上覆在导电配线上的结合垫的半导体结构。所述结合垫以杯状包围缓冲层的下侧表面且凸块结构延伸穿过缓冲层以接触结合垫。凸块结构的侧壁包括上覆在弯曲侧壁区段上的垂直侧壁区段。
在一些实施例中，本揭露提供一种半导体器件结构，所述半导体器件结构包括：结合垫，设置在半导体衬底之上；刻蚀停止层，上覆在所述结合垫上；缓冲层，设置在所述结合垫之上且将所述刻蚀停止层与所述结合垫隔开；以及凸块结构，包括基部部分及上部部分，所述基部部分接触所述结合垫的上表面，所述上部部分延伸穿过所述刻蚀停止层及所述缓冲层，其中所述凸块结构的所述基部部分具有第一宽度或直径且所述凸块结构的所述上部部分具有第二宽度或直径，所述第一宽度或直径大于所述第二宽度或直径。
在上述半导体器件结构中，所述凸块结构的所述基部部分在弯曲侧壁处与所述缓冲层交会，且所述凸块结构的所述上部部分在垂直侧壁处与所述刻蚀停止层交会。
在上述半导体器件结构中，所述半导体器件结构还包括：内连结构，包括设置在所述半导体衬底之上的导电配线，其中所述结合垫设置在所述导电配线之上且耦合到所述导电配线；以及钝化层，上覆在所述内连结构上且沿着所述结合垫的侧壁设置。
在上述半导体器件结构中，所述刻蚀停止层是由第一材料构成且所述缓冲层是由与所述第一材料不同的第二材料构成。
在上述半导体器件结构中，所述第一材料是氧化铝且所述第二材料是氮化钛。
在上述半导体器件结构中，所述凸块结构的底表面与所述缓冲层的底表面对齐。
在上述半导体器件结构中，所述凸块结构的所述上部部分包括：下部导电结构，包含第一导电材料；以及上部导电结构，设置在所述下部导电结构之上，其中所述上部导电结构包含与所述第一导电材料不同的第二导电材料。
在上述半导体器件结构中，所述第一导电材料是镍且所述第二导电材料是金。
在上述半导体器件结构中，所述结合垫的所述上表面包括外围区及中心区，所述外围区在所述半导体衬底的上表面之上具有第一高度，所述中心区在所述半导体衬底的所述上表面之上具有第二高度，所述第一高度大于所述第二高度；且其中所述凸块结构的所述基部部分在第三高度处与所述凸块结构的所述上部部分交会，所述第三高度小于所述第一高度且大于所述第二高度。
在一些实施例中，本揭露提供一种半导体器件结构，所述半导体器件结构包括：内连结构，上覆在衬底上，所述内连结构包括最顶部导电配线；钝化结构，上覆在所述内连结构上；结合垫，上覆在所述最顶部导电配线上，其中所述结合垫延伸穿过所述钝化结构且直接接触所述最顶部导电配线的顶表面，其中所述结合垫具有在垂直方向上位于所述结合垫的顶表面下方的上表面，且其中所述结合垫的所述上表面在垂直方向上位于所述钝化结构的顶表面下方；刻蚀停止层，上覆在所述结合垫及所述钝化结构上；缓冲层，设置在所述刻蚀停止层与所述结合垫之间，其中所述结合垫沿着所述缓冲层的下侧连续地延伸并以杯状包围所述缓冲层的所述下侧；以及凸块结构，包括基部部分及上部部分，所述基部部分接触所述结合垫的所述上表面且设置在所述缓冲层内，所述上部部分从所述基部部分向上延伸且延伸穿过所述刻蚀停止层及所述缓冲层，其中所述基部部分具有在所述缓冲层内界定的第一宽度，且所述上部部分具有在所述缓冲层的所述顶表面上方界定的第二宽度，且其中所述第一宽度大于所述第二宽度。
在上述半导体器件结构中，所述凸块结构的所述基部部分是在所述缓冲层的底表面与所述缓冲层的上表面之间界定，所述缓冲层的所述底表面直接接触所述结合垫的所述上表面，且所述缓冲层的所述上表面直接接触所述刻蚀停止层，所述凸块结构的所述基部部分具有弯曲外侧壁。
在上述半导体器件结构中，所述凸块结构的所述上部部分是从所述缓冲层的所述上表面到位于所述结合垫的所述顶表面上方的点界定，其中所述凸块结构的所述上部部分具有垂直侧壁。
在上述半导体器件结构中，所述基部部分是由镍构成且所述上部部分包括上覆在镍层上的金层。
在上述半导体器件结构中，所述凸块结构在所述结合垫的内侧壁之间在横向上间隔开。
在上述半导体器件结构中，所述刻蚀停止层在所述缓冲层的外侧壁、所述顶表面、内侧壁及上表面之上连续地延伸。
在上述半导体器件结构中，所述结合垫包括上覆在氮化钽层上的铝铜层，其中所述凸块结构直接接触所述铝铜层。
在上述半导体器件结构中，所述结合垫及所述缓冲层二者包含氮化物。
在一些实施例中，本揭露提供一种形成半导体器件结构的方法，所述方法包括：在导电配线之上形成钝化结构；在所述导电配线之上形成结合垫，其中所述结合垫悬在所述钝化结构上；在所述结合垫之上沉积缓冲层；在所述缓冲层及所述钝化结构之上沉积刻蚀停止层；在所述刻蚀停止层之上沉积上部介电结构；对所述缓冲层、所述刻蚀停止层及所述上部介电结构执行干式刻蚀工艺，所述干式刻蚀工艺界定上覆在所述结合垫的上表面上的凸块结构开口，其中在所述干式刻蚀工艺之后，所述缓冲层的一部分上覆在所述结合垫的所述上表面上；对所述缓冲层执行湿式刻蚀工艺，所述湿式刻蚀工艺移除所述缓冲层的上覆在所述结合垫的所述上表面上的所述一部分，其中所述湿式刻蚀工艺使所述凸块结构开口扩大且暴露出所述结合垫的上表面；以及在所述凸块结构开口中形成凸块结构。
在上述形成半导体器件结构的方法中，所述湿式刻蚀工艺在直接上覆在所述结合垫的所述上表面上的所述缓冲层中界定弯曲内侧壁。
在上述形成半导体器件结构的方法中，形成所述凸块结构包括：直接在所述结合垫的所述上表面之上形成镍层，其中所述镍层与所述缓冲层的所述弯曲内侧壁共形，且其中所述镍层包括侧壁，所述侧壁具有直接上覆在弯曲侧壁上的垂直侧壁；以及直接在所述镍层之上形成金层，其中所述金层包括与所述镍层的所述垂直侧壁直接接触的垂直侧壁。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本揭露的各个方面。所属领域中的技术人员应理解，他们可容易地使用本揭露作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本揭露的精神及范围，而且他们可在不背离本揭露的精神及范围的条件下在本文中作出各种改变、代替及变更。

Claims (10)

1.一种半导体器件结构，包括：
结合垫，设置在半导体衬底之上；
刻蚀停止层，上覆在所述结合垫上；
缓冲层，设置在所述结合垫之上且将所述刻蚀停止层与所述结合垫隔开；以及
凸块结构，包括基部部分及上部部分，所述基部部分接触所述结合垫的上表面，所述上部部分延伸穿过所述刻蚀停止层及所述缓冲层，其中所述凸块结构的所述基部部分具有第一宽度或直径且所述凸块结构的所述上部部分具有第二宽度或直径，所述第一宽度或直径大于所述第二宽度或直径。
2.根据权利要求1所述的半导体器件结构，其中所述凸块结构的所述基部部分在弯曲侧壁处与所述缓冲层交会，且所述凸块结构的所述上部部分在垂直侧壁处与所述刻蚀停止层交会。
3.根据权利要求1所述的半导体器件结构，其中所述刻蚀停止层是由第一材料构成且所述缓冲层是由与所述第一材料不同的第二材料构成。
4.根据权利要求1所述的半导体器件结构，其中所述凸块结构的底表面与所述缓冲层的底表面对齐。
5.根据权利要求1所述的半导体器件结构，其中所述凸块结构的所述上部部分包括：
下部导电结构，包含第一导电材料；以及
上部导电结构，设置在所述下部导电结构之上，其中所述上部导电结构包含与所述第一导电材料不同的第二导电材料。
6.根据权利要求1所述的半导体器件结构，
其中所述结合垫的所述上表面包括外围区及中心区，所述外围区在所述半导体衬底的上表面之上具有第一高度，所述中心区在所述半导体衬底的所述上表面之上具有第二高度，所述第一高度大于所述第二高度；且
其中所述凸块结构的所述基部部分在第三高度处与所述凸块结构的所述上部部分交会，所述第三高度小于所述第一高度且大于所述第二高度。
7.一种半导体器件结构，包括：
内连结构，上覆在衬底上，所述内连结构包括最顶部导电配线；
钝化结构，上覆在所述内连结构上；
结合垫，上覆在所述最顶部导电配线上，其中所述结合垫延伸穿过所述钝化结构且直接接触所述最顶部导电配线的顶表面，其中所述结合垫具有在垂直方向上位于所述结合垫的顶表面下方的上表面，且其中所述结合垫的所述上表面在垂直方向上位于所述钝化结构的顶表面下方；
刻蚀停止层，上覆在所述结合垫及所述钝化结构上；
缓冲层，设置在所述刻蚀停止层与所述结合垫之间，其中所述结合垫沿着所述缓冲层的下侧连续地延伸并以杯状包围所述缓冲层的所述下侧；以及
凸块结构，包括基部部分及上部部分，所述基部部分接触所述结合垫的所述上表面且设置在所述缓冲层内，所述上部部分从所述基部部分向上延伸且延伸穿过所述刻蚀停止层及所述缓冲层，其中所述基部部分具有在所述缓冲层内界定的第一宽度，且所述上部部分具有在所述缓冲层的顶表面上方界定的第二宽度，且其中所述第一宽度大于所述第二宽度。
8.根据权利要求7所述的半导体器件结构，其中所述凸块结构的所述基部部分是在所述缓冲层的底表面与所述缓冲层的上表面之间界定，所述缓冲层的所述底表面直接接触所述结合垫的所述上表面，且所述缓冲层的所述上表面直接接触所述刻蚀停止层，所述凸块结构的所述基部部分具有弯曲外侧壁。
9.一种形成半导体器件结构的方法，包括：
在导电配线之上形成钝化结构；
在所述导电配线之上形成结合垫，其中所述结合垫悬在所述钝化结构上；
在所述结合垫之上沉积缓冲层；
在所述缓冲层及所述钝化结构之上沉积刻蚀停止层；
在所述刻蚀停止层之上沉积上部介电结构；
对所述缓冲层、所述刻蚀停止层及所述上部介电结构执行干式刻蚀工艺，所述干式刻蚀工艺界定上覆在所述结合垫的上表面上的凸块结构开口，其中在所述干式刻蚀工艺之后，所述缓冲层的一部分上覆在所述结合垫的所述上表面上；
对所述缓冲层执行湿式刻蚀工艺，所述湿式刻蚀工艺移除所述缓冲层的上覆在所述结合垫的所述上表面上的所述一部分，其中所述湿式刻蚀工艺使所述凸块结构开口扩大且暴露出所述结合垫的所述上表面；以及
在所述凸块结构开口中形成凸块结构。
10.根据权利要求9所述形成半导体器件结构的方法，其中所述湿式刻蚀工艺在直接上覆在所述结合垫的所述上表面上的所述缓冲层中界定弯曲内侧壁。
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