TWI772335B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI772335B
TWI772335B TW106138395A TW106138395A TWI772335B TW I772335 B TWI772335 B TW I772335B TW 106138395 A TW106138395 A TW 106138395A TW 106138395 A TW106138395 A TW 106138395A TW I772335 B TWI772335 B TW I772335B
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Taiwan
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layer
etch stop
bumps
dielectric
stop layer
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TW106138395A
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TW201909342A (zh
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古進譽
楊政龍
陳承先
黃宏麟
王肇儀
陳清暉
郭建鴻
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台灣積體電路製造股份有限公司
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Abstract

提供一種半導體裝置。所述半導體裝置包括第一介電層、 凸塊、刻蝕終止層以及間隔壁。所述第一介電層設置在導電結構之上並暴露出所述導電結構。所述凸塊局部地設置在所述第一介電層中以電連接所述導電結構。所述刻蝕終止層在所述凸塊旁邊設置在所述第一介電層之上。所述間隔壁環繞所述凸塊並設置在所述刻蝕終止層與所述凸塊之間。

Description

半導體裝置及其製造方法
本發明實施例是有關於一種半導體裝置。
一般來說，晶圓可通過黏合層接合到載板，然後可通過單體化製程從所述晶圓形成晶粒。之後，可從載板拾取晶粒並將所述晶粒放置在電子裝置上。然而，在單體化製程中使用的化學物質可損壞晶粒的元件或層。此外，如果在晶粒的凸塊與載板之間形成不恰當的黏合，那麼拾取及放置操作會受到影響。因此，可靠性及良率降低。
本發明實施例的一種半導體裝置包括第一介電層、凸塊、刻蝕終止層以及間隙壁。所述第一介電層設置在導電結構之上並暴露出所述導電結構。所述凸塊局部地設置在所述第一介電層中以電連接所述導電結構。所述刻蝕終止層在所述凸塊旁邊設置在所述第一介電層之上。所述間隙壁環繞所述凸塊並設置在所 述刻蝕終止層與所述凸塊之間。
100:晶圓
102:晶粒區
104:基底
106:主動裝置層
108:導電結構
110:導電層
112:介電層
112a:部分
114:溝槽
120:介電層
122:氧化物層
124:氮化物層
126:氧化物層
128:開口
130:刻蝕終止層
132:犧牲層
134:開口
134a:側壁
134b:底部
136:間隙壁層
138:凸塊
138a:導電柱
138b:焊料
139:凹槽
140:間隙壁
142:介電層
142a:部分
142b:部分
144:開口
150:黏合層
160:載板
200:晶粒
d:深度
t1:厚度
t2:厚度
t3:厚度
θ1:夾角
θ2:夾角
結合附圖閱讀以下詳細說明，會最好地理解本發明的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1A到圖1G是根據一些示例性實施例在半導體裝置的製造方法中的各種階段的示意性剖視圖。
圖2A到圖2D是根據一些示例性實施例，說明在圖1C中所繪示的凸塊及間隙壁的製造製程的剖視圖。
圖3A到圖3G是根據一些示例性實施例在半導體裝置的製造方法中的各種階段的示意性剖視圖。
圖4A是根據一些示例性實施例的圖3C的局部放大圖，且圖4B是圖4A的俯視圖。
以下公開內容提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及構造的具體實例以簡化本公開內容。當然，這些僅為實例且不旨在進行限制。例如，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且 也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對性描述語可同樣相應地進行解釋。
另外，為易於說明，本文中可能使用例如“第一(first)”、“第二(second)”、“第三(third)”、“第四(fourth)”等用語來闡述與圖中所示者相似或不同的一個或多個元件或特徵，且可根據呈現次序或本說明的上下文來可互換地使用所述用語。
還可包括其他特徵及製程。舉例來說，可包括測試結構以說明進行三維(3D)封裝或三維積體電路(3DIC)裝置的驗證測試。測試結構可包括例如形成於重佈線層中或基底上的測試墊，所述測試墊使得能夠測試3D封裝或3DIC、使用探針(probe) 及/或探針卡(probe card)等。可對中間結構及最終結構執行驗證測試。另外，本文中所公開的結構及方法可結合包含對已知良好晶粒的中間驗證的測試方法一起使用，以提高良率及降低成本。
圖1A到圖1G是根據一些示例性實施例在半導體裝置的製造方法中的各種階段的示意性剖視圖。在一些實施例中，為清晰起見，繪示了用於形成一個晶粒的一個晶粒區，然而，可通過半導體裝置的所述製造方法獲得更多個晶粒。
參照圖1A，在一些實施例中，提供晶圓100，且晶圓100包括基底104、主動裝置層106以及導電結構108。基底104可以是半導體基底(例如，矽基底)，但其也可由其他半導體材料形成，所述半導體材料包括但不限於矽鍺、矽碳、砷化鎵等。舉例來說，主動裝置層106是摻雜層。在一些實施例中，主動裝置層106包括電晶體、電阻器、電容器、電感器等。導電結構108可以是內連結構，且包括導電層110及通孔(圖中未示出)。為清晰起見，在圖1A中僅示出了最頂部的導電層110。導電層110及通孔電耦合到主動裝置層106。導電層110及通孔可包含銅或銅合金，且可使用鑲嵌製程(damascene process)形成。在替代實施例中，導電層110及通孔包含鋁、鈦、鎳、鎢、銀、及/或其合金。導電結構108可包括多個介電層(圖中未示出)，所述多個介電層可包括層間介電層(Inter-Layer Dielectric，ILD)及金屬間介電層(Inter-Metal Dielectric，IMD)，且導電層110及通孔設置在所述介電層中。
然後，在晶圓100之上形成介電層112。在一些實施例中， 介電層112是通過例如化學氣相沉積(chemical vapor deposition，CVD)製程等毯覆式沉積製程或任意適當的製程來形成。舉例來說，介電層112是氮化矽或任意適當的材料。此後，在介電層112的一部分之上形成介電層120。在一些實施例中，介電層120包括開口128，以暴露出介電層112的位於導電層110之上的一部分。舉例來說，在一些實施例中，介電層120是例如氧化物-氮化物-氧化物(oxide-nitride-oxide，O-N-O)層等複合層，且介電層120包括氧化物層122、氮化物層124以及氧化物層126。在替代實施例中，介電層120可以是單層並包含任意適當的材料。
參照圖1B，形成多個溝槽114以暴露出基底104，並在相鄰的溝槽114之間形成晶粒區102。在一些實施例中，溝槽114是通過移除主動裝置層106的一部分、導電結構108的一部分以及基底104的一部分來形成。在一些實施例中，還移除位於導電結構108之上的介電層112。因此，在形成溝槽114之後，介電層112在晶粒區102中設置在導電結構108的頂表面之上而不延伸到溝槽114中。
然後，在晶圓100之上共形地形成刻蝕終止層130。在一些實施例中，刻蝕終止層130形成在介電層112的、介電層120的、以及溝槽114的被暴露出的表面之上。在一些實施例中，介電層120設置在刻蝕終止層130與介電層112之間。在一些實施例中，刻蝕終止層130是通過例如原子層沉積(atomic layer deposition，ALD)製程等毯覆式沉積製程或任意適當的製程形成。 在一些實施例中，刻蝕終止層130包含例如氧化鋁(Al2O3)等金屬氧化物或任意適當的材料。之後，在刻蝕終止層130之上形成犧牲層132，並使犧牲層132填充溝槽114。在一些實施例中，犧牲層132是通過例如CVD製程等沉積製程或任意適當的製程形成。在一些實施例中，犧牲層132包含例如氧化矽等介電材料或任意適當的材料。刻蝕終止層130的材料相對於犧牲層132具有刻蝕選擇性，且因此刻蝕終止層130在對犧牲層132的移除期間保護其他結構。
參照圖1C，形成具有間隙壁140的凸塊138，以電連接導電層110。圖2A到圖2D是根據一些示例性實施例，說明在圖1C中所繪示的凸塊138及間隙壁140的製造製程的剖視圖。應注意，在圖2A到圖2D中所繪示的圖僅作為用於進行示範的實例。因此，在圖2A到圖2D中所說明的比例、尺寸及形狀可能不完全反映在圖1B中所說明的凸塊138及間隙壁140。然而，相同的元件是由相同的參考編號指示，以在圖2A到圖2D與圖1C之間建立相關性。
參照圖2A，移除刻蝕終止層130的一部分以及犧牲層132的一部分，以在導電層110之上形成開口134。開口134具有側壁134a及底部134b。舉例來說，在一些實施例中，刻蝕終止層130與犧牲層132被分別移除。然後，在晶圓100之上形成間隙壁層136，以覆蓋犧牲層132的頂表面、以及開口134的側壁134a及底部134b。在一些實施例中，間隙壁層136是通過例如CVD製程 等毯覆式沉積製程或任意適當的製程形成。在一些實施例中，間隙壁層136包括例如氮化鈦(TiN)等金屬氮化物或任意適當的材料。
參照圖2B，移除間隙壁層136的以及介電層112的位於導電層110之上的部分，以暴露出導電層110。在一些實施例中，執行例如乾刻蝕製程等各向異性刻蝕，以移除位於犧牲層132的頂表面及開口134的底部134b之上的間隙壁層136。應注意，由於介電層112的一部分112a被位於開口134的側壁134a上的間隙壁層136覆蓋，因此介電層112的所述部分112a不被移除。在一些實施例中，位於導電層110之上的介電層112與間隙壁層136可被同時移除或分別移除。在一些實施例中，還移除間隙壁層136的位於側壁134a的頂部部分上的一部分，且因此間隙壁層136可具有傾斜的頂表面。
參照圖2C，在開口134中形成凸塊138。在一些實施例中，凸塊138被間隙壁層136環繞且與間隙壁層136接觸，也就是說，凸塊138填充由間隙壁層136形成的空間的一部分。在一些實施例中，凸塊138的頂部低於間隙壁層136的頂部，且高於刻蝕終止層130的頂部。在一些實施例中，凸塊138包括導電柱138a及導電柱138a上的焊料138b，且焊料138b的頂部低於間隙壁層136的頂部。凸塊138是通過無電鍍覆製程或任意適當的製程形成。刻蝕終止層130的熱膨脹係數(coefficient of thermal expansion，CTE)及犧牲層132的熱膨脹係數不同於凸塊138的 熱膨脹係數。舉例來說，在一些實施例中，導電柱138a包含鎳(Ni)，且焊料138b包含金(Au)。在替代實施例中，凸塊138可具有Ni/Pd/Au材料或任意適當的金屬。舉例來說，在一些實施例中，凸塊138的大小小於3μm或2μm，且凸塊138的節距不小於2μm。舉例來說，焊料138b的厚度介於0.01μm至0.5μm範圍內，且導電柱138a的厚度介於0.1μm至2μm範圍內。然而，應理解，本發明的範圍並非僅限於以上所公開的材料及說明。
參照圖2D，移除間隙壁層136的一部分，以在凸塊138上形成間隙壁140。在一些實施例中，間隙壁層136的一部分是通過例如濕刻蝕製程等刻蝕製程來移除。間隙壁140環繞凸塊138，且間隙壁140與刻蝕終止層130及凸塊138接觸並密封刻蝕終止層130與凸塊138之間的間隙。在一些實施例中，間隙壁140在刻蝕終止層130與凸塊138之間安置在介電層112的所述部分112a上。刻蝕終止層130的一部分在間隙壁140與介電層120之間延伸於介電層112之上。在一些實施例中，間隙壁140的頂部低於凸塊138的頂部，且因此凸塊138的側壁的至少一部分不被間隙壁140覆蓋。在一些實施例中，焊料138b的頂部被暴露出，且焊料138b的側壁不被間隙壁140覆蓋。也就是說，介電層112的厚度與間隙壁140的高度的總和不大於導電柱138a的高度。在一些實施例中，間隙壁140的厚度小於或等於1000埃，例如介於約100埃至1000埃範圍內。
參照圖1D，將晶圓100上下倒置並通過黏合層150接合 到載板160，且黏合層150設置在載板160與晶圓100之間。在一些實施例中，黏合層150通過填充在犧牲層132、間隙壁140以及凸塊138之間形成的空間而與凸塊138接觸。因此，黏合層150的一部分延伸到所述空間中並形成為突出部。在一些實施例中，載板160可以是玻璃載板或用於承載半導體晶圓或再造晶圓的任意適當的載板。黏合層150包括由介電材料製成的介電層，所述介電材料包括苯並環丁烯(BCB)、聚苯並惡唑(PBO)、或任意適當的介電材料。
參照圖1E，移除基底104，以在溝槽114中暴露出犧牲層132。在一些實施例中，基底104是通過研磨製程或化學機械研磨(chemical mechanical polishing，CMP)製程來移除。在一些實施例中，還移除位於圖1C中的溝槽114的底部上的刻蝕終止層130，且因此暴露出犧牲層132。
參見圖1F，移除犧牲層132，並形成晶粒200。在一些實施例中，犧牲層132是通過被暴露出的溝槽114而進行移除。具體來說，犧牲層132是利用例如蒸氣氫氟酸(HF)等刻蝕劑或任意適當的化學物質來移除，且所述刻蝕劑通過被暴露出的溝槽114與犧牲層132接觸。在一些實施例中，在移除犧牲層132之後，形成在晶粒區102中包括主動裝置層106、導電結構108、介電層112及120、刻蝕終止層130、及具有間隙壁140的凸塊138的晶粒200，並使晶粒200與其他晶粒分離。因此，此製程也被稱為單體化製程。
參照圖1G，從載板160剝離晶粒200。在一些實施例中，凸塊138局部地設置在介電層112中，且間隙壁140設置在凸塊138的側壁上並位於刻蝕終止層130與凸塊138之間。在一些實施例中，刻蝕終止層130覆蓋晶粒200的除凸塊138的表面及間隙壁140的表面以外的側表面及頂表面。在一些實施例中，由於晶粒200的大小不大於150μm×30μm，因此晶粒200可以是微驅動器，晶粒200的大小顯著小於10mm×10mm的正常晶粒大小。在一些實施例中，晶粒200可以是數位晶片、類比晶片、或混合訊號晶片，例如應用專用積體電路(application-specific integrated circuit，ASIC)晶片、感測器晶片、無線與射頻晶片、記憶體晶片、邏輯晶片、或電壓調節器晶片。
一般來說，由於刻蝕終止層與凸塊的熱膨脹係數不同，因此在加熱之後刻蝕終止層與凸塊之間的黏合不良，且易於發生刻蝕終止層從凸塊的脫層或剝落。因此，在單體化製程中使用的例如蒸氣HF等刻蝕劑可通過在刻蝕終止層與凸塊之間形成的間隙而進入到介電層中，且介電層可受損且凸塊可產生裂隙。因此，半導體裝置的可靠性降低。然而，在一些實施例中，在刻蝕終止層與凸塊之間形成有間隙壁，且所述間隙壁作為膠層以提高介面黏合性。因此，消除了刻蝕終止層與凸塊之間的脫層或剝落，且由於刻蝕終止層可作為障壁層，因此可防止對介電層及導電層的損壞或防止凸塊產生裂隙。因此，提高了凸塊的可靠性及完整性。
圖3A到圖3G是根據一些示例性實施例在半導體裝置的 製造方法中的各種階段的示意性剖視圖。
參照圖3A，形成凸塊138以電連接晶圓100的導電層110。在一些實施例中，晶圓100包括基底104、主動裝置層106以及導電結構108。在一些實施例中，在導電結構108之上在穿過介電層112、刻蝕終止層130及犧牲層132的開口134中形成凸塊138，且刻蝕終止層130形成在介電層112與犧牲層132之間。在一些實施例中，在刻蝕終止層130與介電層112之間形成介電層120。凸塊138的頂部低於犧牲層132的頂部。在一些實施例中，如圖4B所示，凸塊138的頂表面是圓形。在替代實施例中，凸塊138的頂表面被成形為類似圓形或幾乎類似圓形，例如具有多於4個頂點的多邊形，包括五邊形、六邊形、七邊形、八邊形等。在替代實施例中，凸塊138的頂表面是其中長軸與垂直軸的角度是0度至90度的橢圓形或任意適當的形狀。在一些實施例中，凸塊138是通過無電鍍覆製程或任意適當的製程形成。在一些實施例中，凸塊138包括導電柱138a及導電柱138a上的焊料138b。舉例來說，在一些實施例中，導電柱138a包含鎳(Ni)，且焊料138b包含金(Au)。在替代實施例中，凸塊138可具有Ni/Pd/Au材料。晶圓100、介電層112、刻蝕終止層130以及犧牲層132各自的結構、形成方法及材料可參照以上實施例，且不再對其予以贅述。然而，應瞭解，本發明的範圍並不僅限於以上所公開的材料及說明。
參照圖3B，在犧牲層132之上共形地形成介電層142。 在一些實施例中，介電層142是通過例如CVD製程等毯覆式沉積製程或任意適當的製程形成，且介電層142可在低於400℃的溫度下形成。介電層142的厚度小於1μm，例如小於0.5μm。在一些實施例中，由於介電層142形成有小的厚度，因此可省略例如CPM製程等厚度減小製程。在一些實施例中，介電層142的材料與犧牲層132的材料相同或不同。在一些實施例中，介電層142的材料可以是氧化矽或任意適當的材料。
參照圖3C，移除介電層142的一部分以暴露出凸塊138的一部分。舉例來說，在一些實施例中，晶圓100上具有多個凸塊138，且至少一個凸塊138被介電層142暴露出，而至少一個凸塊138仍被介電層142覆蓋。換句話說，對凸塊138之上的介電層142的移除確定用於進行接合的凸塊138的數目。在一些實施例中，介電層142是通過刻蝕製程(例如，乾刻蝕製程或濕刻蝕製程)或過刻蝕製程(over-etching process)來進行移除。
圖4A是圖3C的局部放大圖，且圖4B是圖4A的俯視圖。參照圖4A，在一些實施例中，在介電層142中形成開口144，以暴露出凸塊138的一部分。在一些實施例中，剩餘的介電層142水準延伸到凸塊138的頂部的一部分上。詳細來說，剩餘的介電層142包括設置在開口134的側壁134a上的一部分142a、以及延伸到凸塊138的頂部上的一部分142b，其中部分142a與部分142b連續地連接。此外，還通過對介電層142的移除製程移除凸塊138的一部分，並因此在凸塊138的頂部中形成凹槽139。舉例來說， 在一些實施例中，凹槽139形成在焊料138b中。舉例來說，凹槽139的深度d小於焊料138b的厚度的10%，且小於500埃。凹槽139的切線與凸塊138的頂部的延伸線之間的夾角θ1小於45度。介電層142中的開口144的側壁與垂直軸之間的夾角θ2小於30度。舉例來說，介電層142的厚度t1小於0.5μm。舉例來說，焊料138b的厚度t2介於0.01μm至0.5μm範圍內，且導電柱138a的厚度t3介於0.1μm至2μm範圍內。舉例來說，在一些實施例中，凸塊138的大小小於3μm或2μm，且凸塊138的節距不小於2μm。在替代實施例中，在介電層142中形成開口144之後，凸塊138可實質上保持完整而不在其中形成凹槽。
參照圖4B，介電層142中的開口144的形狀與凸塊138的頂表面的形狀相同或類似。舉例來說，在一些實施例中，凸塊138的形狀是圓形，且開口144的形狀是圓形。凸塊138的被介電層142的開口144暴露出的區域(其為凸塊138的用於接觸圖3D中所示的黏合層150的區域)是晶粒區102的約0.01%至0.3%。
參照圖3D，將晶圓100上下倒置並通過黏合層150接合到載板160，且黏合層150設置在載板160與晶圓100之間。在一些實施例中，黏合層150通過填充在介電層142與凸塊138之間形成的空間而與凸塊138接觸。因此，黏合層150的一部分延伸到所述空間中並形成為突出部。載板160及黏合層150各自的材料可參照以上實施例，且不再對其予以贅述。
參照圖3E，移除基底104，以在溝槽114中暴露出犧牲 層132。在一些實施例中，基底104是通過研磨製程或CMP製程來移除。在一些實施例中，還移除位於圖3B中的溝槽114的底表面上的刻蝕終止層130，且因此暴露出犧牲層132。
參見圖3F，移除犧牲層132及介電層142，並形成晶粒200。犧牲層132與介電層142可被同時移除或分別移除。在一些實施例中，犧牲層132及介電層142是通過被暴露出的溝槽114而進行移除。具體來說，犧牲層132及介電層142是利用例如蒸氣氫氟酸(HF)等刻蝕劑或任意適當的化學物質來移除，且所述刻蝕劑通過被暴露出的溝槽114與犧牲層132及介電層142接觸。在一些實施例中，在移除犧牲層132及介電層142之後，形成在晶粒區102中包括主動裝置層106、導電結構108、介電層112及120、刻蝕終止層130、及凸塊138的晶粒200，並使晶粒200與其他晶粒分離。
參照圖3G，從載板160剝離晶粒200。在一些實施例中，凸塊138局部地設置在介電層112中，且刻蝕終止層130覆蓋晶粒200的除凸塊138的表面以外的側表面及頂表面。在一些實施例中，由於晶粒200的大小不大於150μm×30μm(即，顯著小於10mm×10mm的正常晶粒大小)，因此晶粒200可以是微驅動器。
在一些實施例中，暴露出凸塊的一部分的介電層(即，介電層142)是在低溫下形成的薄厚度層，且因此可顯著減小熱預算，且可省略用於介電層的厚度減小製程。此外，防止了因高溫 而由導電層引起的對凸塊的銅污染。由於介電層的移除厚度減小(也就是說，凹槽的深度減小)，因此凸塊的表面上的凹陷效果減小。因此，凸塊具有平滑的表面，且晶粒的拾取及放置良率極大提高。此外，在一些實施例中，凸塊具有圓形或類似圓形形狀，且因此防止了應力及電荷的累積(例如，電流效應)，且防止了在方形凸塊的隅角中形成結節(nodule)。因此，在一個晶粒中結節缺陷凸塊對總凸塊的比率可顯著改良而為低於2.5×10-5ppm。由於消除了在凸塊的隅角中的結節缺陷，因此在黏合層與凸塊之間的保持力(holding force)良好。因此，半導體裝置的製造方法具有降低的成本及提高的良率。
根據一些實施例，一種半導體裝置包括第一介電層、凸塊、刻蝕終止層以及間隙壁。所述第一介電層設置在導電結構之上並暴露出所述導電結構。所述凸塊局部地設置在所述第一介電層中以電連接所述導電結構。所述刻蝕終止層在所述凸塊旁邊設置在所述第一介電層之上。所述間隙壁環繞所述凸塊並設置在所述刻蝕終止層與所述凸塊之間。
在一些實施例中，所述間隙壁在所述刻蝕終止層與所述凸塊之間安置在所述第一介電層上。
在一些實施例中，所述間隙壁接觸所述刻蝕終止層及所述凸塊。
在一些實施例中，所述凸塊的側壁的一部分不被所述間隙壁覆蓋。
在一些實施例中，所述凸塊包括導電柱及所述導電柱上的焊料。
在一些實施例中，進一步包括位於所述刻蝕終止層與所述第一介電層之間的第二介電層，其中所述刻蝕終止層的一部分在所述間隙壁與所述第二介電層之間延伸於所述第一介電層之上。
在一些實施例中，所述間隙壁的厚度小於或等於1000埃。
根據一些實施例，提供一種半導體裝置的製造方法。在第一介電層之上形成刻蝕終止層，其中所述第一介電層形成在導電結構之上。在所述刻蝕終止層之上形成犧牲層，其中開口穿過所述犧牲層及所述刻蝕終止層以暴露出所述導電層的一部分。在所述開口中形成具有間隙壁的凸塊，以電連接所述導電結構，其中所述間隙壁形成在所述刻蝕終止層與所述凸塊之間。
在一些實施例中，所述間隙壁在所述刻蝕終止層與所述凸塊之間形成在所述第一介電層之上。
在一些實施例中，形成具有所述間隙壁的所述凸塊包括：在所述開口的側壁及底部上形成間隙壁層；移除所述開口的所述底部上的所述間隙壁層，以暴露出所述導電結構；在所述開口中形成所述凸塊，其中所述開口的所述側壁上的所述間隙壁層環繞所述凸塊；以及移除所述間隙壁層的一部分，以形成所述間隙壁。
在一些實施例中，進一步包括在所述第一介電層的一部 分之上、在所述刻蝕終止層與所述第一介電層之間形成第二介電層。
在一些實施例中，所述刻蝕終止層形成在所述第二介電層及所述間隙壁與所述第二介電層之間的所述第一介電層之上。
在一些實施例中，進一步包括將所述凸塊接合到載板，及在接合之後移除所述犧牲層。
根據一些實施例，提供一種半導體裝置的製造方法。在刻蝕終止層之上在穿過所述刻蝕終止層及犧牲層的開口中形成凸塊，其中所述凸塊的頂部低於所述犧牲層的頂部。在所述犧牲層及所述凸塊之上形成介電層。移除所述介電層的一部分，以暴露出所述凸塊的一部分。將所述凸塊通過黏合層接合到載板，其中所述黏合層設置在所述介電層與所述載板之間。
在一些實施例中，所述凸塊的形狀是圓形、具有多於4個頂點的多邊形、或橢圓形。
在一些實施例中，所述介電層的厚度小於1μm。
在一些實施例中，所述介電層是在低於400℃的溫度下形成。
在一些實施例中，在移除所述介電層的所述一部分的同時，在所述凸塊的所述一部分中形成凹槽。
在一些實施例中，在移除所述介電層的所述一部分之後，剩餘的所述介電層包括設置在所述開口的側壁上的第一部分及延伸到所述凸塊的所述頂部的一部分上的第二部分。
在一些實施例中，進一步包括：在接合之後移除所述犧牲層及所述介電層。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應理解，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。
110:導電層
112:介電層
112a:部分
120:介電層
122:氧化物層
124:氮化物層
126:氧化物層
130:刻蝕終止層
132:犧牲層
138:凸塊
138a:導電柱
138b:焊料
140:間隙壁

Claims (10)

  1. 一種半導體裝置，包括：第一介電層，設置在導電結構之上並暴露出所述導電結構；凸塊，局部地設置在所述第一介電層中以電連接所述導電結構；刻蝕終止層，在所述凸塊旁邊設置在所述第一介電層之上；以及間隙壁，環繞所述凸塊並設置在所述刻蝕終止層與所述凸塊之間，其中所述間隙壁在所述第一介電層的頂表面上的投影區域與所述刻蝕終止層在所述第一介電層的所述頂表面上的投影區域分離。
  2. 如申請專利範圍第1項所述的半導體裝置，其中所述間隙壁在所述刻蝕終止層與所述凸塊之間安置在所述第一介電層上。
  3. 一種半導體裝置，包括：多個介電圖案，設置在導電結構之上；凸塊，設置在所述介電圖案之間以電連接所述導電結構；以及刻蝕終止層，設置在所述介電圖案之上且設置在所述介電圖案與所述凸塊之間，其中所述刻蝕終止層與所述凸塊的外側壁實體接觸。
  4. 如申請專利範圍第3項所述的半導體裝置，其中所述刻蝕終止層接觸所述介電圖案。
  5. 如申請專利範圍第3項所述的半導體裝置，其中所述刻蝕終止層連續地設置在所述介電圖案與所述凸塊之間。
  6. 一種半導體裝置，包括：多個介電圖案，設置在導電結構之上且暴露所述導電結構；凸塊，設置在所述介電圖案之間以電連接所述導電結構；以及刻蝕終止層，設置在所述介電圖案的側壁與頂表面之上且設置在所述介電圖案與所述凸塊之間，其中所述刻蝕終止層在所述半導體裝置的底表面上的投影區域與所述凸塊在所述半導體裝置的所述底表面上的投影區域分離，且所述刻蝕終止層與所述凸塊的外側壁實體接觸。
  7. 如申請專利範圍第6項所述的半導體裝置，還包括設置在所述凸塊的頂表面處的凹槽，其中所述凹槽的底部高於位在所述介電圖案之上的所述刻蝕終止層的部分的頂表面。
  8. 一種半導體裝置的製造方法，包括：在第一介電層之上形成刻蝕終止層，其中所述第一介電層形成在導電結構之上；在所述刻蝕終止層之上形成犧牲層與開口，其中所述開口穿過所述犧牲層及所述刻蝕終止層以暴露出所述導電結構的部分；在所述開口的側壁上形成間隔壁； 在形成所述間隔壁之後，在所述開口中形成凸塊以電連接所述導電結構，其中所述間隔壁設置在所述刻蝕終止層與所述凸塊之間；以及在形成所述凸塊之後，移除位在所述開口的所述側壁上的所述間隔壁的部分。
  9. 一種半導體裝置的製造方法，包括：在穿過刻蝕終止層與所述刻蝕終止層上方的犧牲層的開口中形成凸塊，其中所述凸塊的頂部低於所述犧牲層的頂部；在所述犧牲層與所述凸塊上方形成介電層；移除所述介電層的部分，以暴露所述凸塊的部分；通過粘合層將所述凸塊結合至載板，其中所述粘合層位於所述介電層與所述載板之間；以及在將所述凸塊結合至所述載板之後，移除所述犧牲層與所述介電層。
  10. 一種半導體裝置的製造方法，包括：在導電結構之上形成第一介電層，所述第一介電層包括多個圖案與位於所述多個圖案之間的第一開口；在所述第一介電層之上形成刻蝕終止層，其中所述刻蝕終止層的部分形成在所述第一開口的側壁與底部上；形成犧牲層，以填滿所述第一開口且覆蓋所述多個圖案與所述刻蝕終止層；通過部分移除所述犧牲層與所述刻蝕終止層，以形成位於所述多個圖案之間的第二開口；以及 在所述第二開口中形成具有間隔壁的凸塊以電連接所述導電結構，其中所述間隔壁形成在所述刻蝕終止層與所述凸塊之間。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11322464B2 (en) * 2019-10-01 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Film structure for bond pad
GB2593698B (en) 2020-03-30 2022-12-07 Plessey Semiconductors Ltd Monolithic electronic device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060166402A1 (en) * 2005-01-27 2006-07-27 Chartered Semiconductor Manufacturing Ltd. Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures
US20140124922A1 (en) * 2012-08-30 2014-05-08 SK Hynix Inc. Bump structures in semiconductor packages and methods of fabricating the same
US20140346663A1 (en) * 2013-05-21 2014-11-27 Sheila F. Chopin Semiconductor structure with sacrificial anode and method for forming
US20150325546A1 (en) * 2010-03-24 2015-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same
TW201546980A (zh) * 2014-06-03 2015-12-16 Powertech Technology Inc 縮短支撐柱之金屬柱銲接晶片連接結構
TW201633414A (zh) * 2015-03-11 2016-09-16 飛立帕奇帕國際股份有限公司 用於在半導體晶圓上形成柱狀凸塊的方法
CN106486444A (zh) * 2015-08-31 2017-03-08 中芯长电半导体（江阴）有限公司 凸块结构、封装组件及其形成方法
TW201721811A (zh) * 2015-09-14 2017-06-16 美光科技公司 凸塊下金屬結構環及其相關之系統及方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627106A (en) * 1994-05-06 1997-05-06 United Microelectronics Corporation Trench method for three dimensional chip connecting during IC fabrication
US7015135B2 (en) * 2002-12-10 2006-03-21 Advanced Micro Devices, Inc. Method and system for reducing contact defects using non conventional contact formation method for semiconductor cells
US7485564B2 (en) * 2007-02-12 2009-02-03 International Business Machines Corporation Undercut-free BLM process for Pb-free and Pb-reduced C4
US20120018883A1 (en) * 2007-09-13 2012-01-26 Geng-Shin Shen Conductive structure for a semiconductor integrated circuit
US8501587B2 (en) * 2009-01-13 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated chips and methods of fabrication thereof
US8426938B2 (en) * 2009-02-16 2013-04-23 Samsung Electronics Co., Ltd. Image sensor and method of fabricating the same
IN2012DN00452A (zh) * 2009-07-30 2015-05-15 Megica Corp
US9024431B2 (en) * 2009-10-29 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die contact structure and method
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8502389B2 (en) * 2011-08-08 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS image sensor and method for forming the same
US8847388B2 (en) * 2011-10-06 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Bump with protection structure
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
KR101992352B1 (ko) * 2012-09-25 2019-06-24 삼성전자주식회사 반도체 장치
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9076715B2 (en) * 2013-03-12 2015-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for connecting dies and methods of forming the same
KR102142366B1 (ko) * 2013-11-14 2020-08-07 삼성전자 주식회사 반도체 집적 회로 소자 및 그 제조 방법, 반도체 패키지
US9412719B2 (en) * 2013-12-19 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9190375B2 (en) * 2014-04-09 2015-11-17 GlobalFoundries, Inc. Solder bump reflow by induction heating
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9653445B2 (en) * 2014-10-24 2017-05-16 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield
US9508858B2 (en) * 2014-11-18 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Contacts for highly scaled transistors
US9496169B2 (en) * 2015-02-12 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an interconnect structure having an air gap and structure thereof
WO2017100255A1 (en) * 2015-12-08 2017-06-15 Skyworks Solutions, Inc. Method of providing protective cavity and integrated passive components in wafer-level chip-scale package using a carrier wafer
US9875989B2 (en) * 2016-01-12 2018-01-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure
JP6615701B2 (ja) * 2016-06-24 2019-12-04 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060166402A1 (en) * 2005-01-27 2006-07-27 Chartered Semiconductor Manufacturing Ltd. Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures
US20150325546A1 (en) * 2010-03-24 2015-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same
US20140124922A1 (en) * 2012-08-30 2014-05-08 SK Hynix Inc. Bump structures in semiconductor packages and methods of fabricating the same
US20140346663A1 (en) * 2013-05-21 2014-11-27 Sheila F. Chopin Semiconductor structure with sacrificial anode and method for forming
TW201546980A (zh) * 2014-06-03 2015-12-16 Powertech Technology Inc 縮短支撐柱之金屬柱銲接晶片連接結構
TW201633414A (zh) * 2015-03-11 2016-09-16 飛立帕奇帕國際股份有限公司 用於在半導體晶圓上形成柱狀凸塊的方法
CN106486444A (zh) * 2015-08-31 2017-03-08 中芯长电半导体（江阴）有限公司 凸块结构、封装组件及其形成方法
TW201721811A (zh) * 2015-09-14 2017-06-16 美光科技公司 凸塊下金屬結構環及其相關之系統及方法

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