200937542 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體結構，且特別是有關於具有超 薄保護層之半導體結構及其製法。 【先前技術】 積體電路晶片封裝製程是整個製程中的重要步驟，其 0 影響整個成本、封裝晶片的性能、以及元件可靠度。由於 半導體元件與晶片的尺寸不斷縮小，使得封裝的接腳也曰 漸增多。 因應電子產品輕薄短小的趨勢，覆晶（flip chip)的技術 已成為晶片封裝中非常重要的一環。在覆晶技術中，晶片 不再以打線方式連接到封裝基板，而是將晶片反轉透過金 屬凸塊(Bump)電性及機械連接到封裝基板上。所以，覆晶 技術可減少封裝所需之空間而增加產品中元件的密度，提 ❹ 升其效能。 金屬凸塊係形成於半導體基板之頂部金屬層上，而由 頂部金屬層上之介電層及保護層所包圍。想要進一步增進 封裝密度與品質，金屬凸塊與頂部金屬層間的介電層及保 護層扮演重要的角色。 【發明内容】 本發明提供一種半導體結構，包括半導體基板，複數個 頂部金屬層在半導體基板上，高密度電漿沉積層，填入複 96007/0516-A41218-TW/£7YChen 200937542 數個頂部金屬層之間隙，且高密度電漿沉積層具有實質平 坦之上表面，以及保護層在高密度電漿沉積層上。 本發明另提供一種半導體結構的製造方法，包括提供半 導體基板’形成複數個頂部金屬層於半導體基板上，形成 局密度電漿沉積層填入複數個頂部金屬層之間隙，而在頂 部金屬層上之高密度電漿沉積層具有凸出之上表面，對高 密度電漿沉積層實施平坦化製程，以及在平坦化後之高密 度電漿沉積層上，形成保護層。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 第1A及1B圖顯示發明人所知的一種形成金屬凸塊前 的保護製程(passivation process)。但應注意的是，以下的 說明並非此技術領域之公知常識，僅用來顯示發明人所發 ❹現的問題。 如第1A圖所示，在一基板1〇〇上具有複數個頂部金 屬層104,然後形成氧化矽層1〇8，覆蓋頂部金屬層1〇4 並填入頂部金屬層間之間隙102。為了使氧化矽層1〇8能 充分填入間隙102,選擇使用高密度電漿沉積技術來沉積 氧化矽層108。之後，在氧化矽層108上形成氮化矽層112, 其厚度約5000人〜7〇〇〇A。接著形成一開口 116，穿過氧化 矽層108及氮化矽層112，露出頂部金屬層1〇4。最後，如 第1B圖所示，於露出之頂部金屬層1〇4中形成金屬凸塊 960〇7/〇5l6-A41218-TW/£Trcheii 200937542 120(例如金凸塊）’用以覆晶封裝。 e φ 然而，如第1Α圖所示，以高密度電漿沉積技術所形 的氧切層刚會在頂部金屬層1G4上形成突出部（或凸狀 物）’這是高密度電漿沉積技術本身的製程特質所致，此 分的高度Η約7000人。而隨後沉積之氮化矽層112，也^ 為其底下是凹凸不平的氧化石夕層，因此沉積的厚度不能太 薄。一般至少需沉積約7000Α，否則保護層表面起^太1， 無法對底下的元件提供均勻的保護。氮化矽是較為堅硬的 材質，太厚將使應力加大，易對基板100造成傷害。、 此外，如第1Β圖所示，金屬凸塊120形成於頂部金屬 層104上之開口 116時，金屬凸塊120需先填入深度τι 的開口 116’其中T1約14000人，由於頂部金屬層上 的氧化矽層108與氮化矽層Π2非常厚，增加了許多金屬 凸塊120的用料，而增加製作成本。 為解決上述問題，本發明在此提供一種具超薄保護層 之半導體結構，可增進保護層之平坦度並避免保護層龜裂 (crack )，還能有效節省保護層及金屬凸塊(Bump)之用 料。以下配合第2A-2F圖說明本發明之實施例的製造過程。 如第2A圖，提供半導體基板200。半導體基板例如矽 晶圓，其上可具有各種已完成之半導體元件，如電晶體、 電阻、邏輯元件等，在此處為了簡化圖示，僅以一平整的 基板表示。在半導體基板上形成有複數個頂部金屬層 204,複數個頂部金屬層204與半導體基板200間形成數個 間隙202。其中，頂部金屬層204可包括常用之金屬，例 96007/0516-A41218-TW/^JYChen 200937542 如銘 '銅、銀、金、或前述之組合。頂部金屬層204可例 如以氣相沉積或電鍍方式形成於半導體基板200上，再透 過例如微影與兹刻製程形成分離之複數個頂部金屬層 204，並留下多個間隙202於頂部金屬層204之間。隨後， 在以氧化層填入頂部金屬層204的間隙202之前，先沉積 終止層206於頂部金屬層204上’由以下說明可知，此終 止層將也後續作為氧化層平坦化時的終止層。在此實施例 中，終止層206順應性地沉積在頂部金屬層2〇4之上表面、 ❹侧壁、及半導體基板200之上表面。終止層206的材質例 如是氮氧化矽，厚度可介於約400人〜1500Λ。 第2B圖.顯不回雄、度電聚沉積層208之形成。高密度電 漿沉積層208通常是氧化物’例如氧化石夕。其具有優異的 填洞能力。在高密度電漿沉積層充分填入間隙2〇2後，會 在頂部金屬層204上形成突出部。這是由高密度電聚沉積 技術本身的製程特質所致。 ❹之後，如第2C圖所示，對具有突出部之高密度電漿 沉積層208實施平坦化製程，使成為具有實質平坦之上表 面的南密度電漿沉積層208a。在一實施例中，平坦化製程 例如是化學機械研磨，化學機械研磨可以終點偵測模式進 行’直到露出終止層206。或者亦:‘可以時間模式進行，使 化學機械研磨於露出終止層206之前停止。雖然第2(：圖 中，頂部金屬層204上仍有部分的殘餘高密度電漿沉積層 208a ’但應可了解的是，此技術人士亦可將頂部金屬層 上的高密度電漿沉積層208a完全去除，只留下在頂部胃金屬 96007/0516-A41218-TWMYChen 200937542 層204之間的高密度電漿沉積層2〇8a。 _第2D圖顯示保護層212之形成。保護層212例如是 氮化矽。在一實施例中，由於高密度電漿沉積層208a已= 有貫質平坦之上表面，保護層212是在平坦的下接面21孔 /儿積，所以可大幅縮減保護層212之厚度，即可得到具有 實質平坦之上表面212a之保護層。保護層212之厚度較佳 約5000A〜6500 A。在一實施例中，頂部金屬層2〇4上表200937542 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor structures, and more particularly to semiconductor structures having ultra-thin protective layers and methods of making same. [Prior Art] The integrated circuit chip packaging process is an important step in the entire process, which affects the overall cost, package wafer performance, and component reliability. As semiconductor components and wafers continue to shrink in size, the number of pins on the package has increased. In response to the trend of thin and light electronic products, flip chip technology has become a very important part of chip packaging. In flip chip technology, the wafer is no longer wire bonded to the package substrate, but the wafer is reversed through the metal bumps electrically and mechanically to the package substrate. Therefore, flip chip technology can reduce the space required for packaging and increase the density of components in the product, thereby improving its performance. The metal bumps are formed on the top metal layer of the semiconductor substrate and surrounded by the dielectric layer and the protective layer on the top metal layer. To further enhance package density and quality, the dielectric and protective layers between the metal bumps and the top metal layer play an important role. SUMMARY OF THE INVENTION The present invention provides a semiconductor structure including a semiconductor substrate, a plurality of top metal layers on a semiconductor substrate, a high-density plasma deposition layer, filled with a plurality of top metals of 96007/0516-A41218-TW/£7YChen 200937542 The gap between the layers, and the high density plasma deposited layer has a substantially flat upper surface, and the protective layer is on the high density plasma deposited layer. The present invention further provides a method of fabricating a semiconductor structure, comprising providing a semiconductor substrate 'forming a plurality of top metal layers on a semiconductor substrate, forming a local density plasma deposition layer filled in a gap between the plurality of top metal layers, and on the top metal layer The high-density plasma deposition layer has a convex upper surface, a planarization process is performed on the high-density plasma deposition layer, and a protective layer is formed on the planarized high-density plasma deposition layer. The above and other objects, features and advantages of the present invention will become more <RTIgt; A passivation process prior to forming the metal bumps known to the inventors is shown. It should be noted, however, that the following description is not a common general knowledge of this technical field and is merely intended to show the problems that the inventors have developed. As shown in Fig. 1A, a plurality of top metal layers 104 are formed on a substrate 1 and then a tantalum oxide layer 1 is formed, covering the top metal layer 1〇4 and filling the gaps 102 between the top metal layers. In order to allow the yttrium oxide layer 1 〇 8 to sufficiently fill the gap 102, a high density plasma deposition technique is used to deposit the yttrium oxide layer 108. Thereafter, a tantalum nitride layer 112 is formed on the tantalum oxide layer 108, and has a thickness of about 5,000 to 7 Å. An opening 116 is then formed through the beryllium oxide layer 108 and the tantalum nitride layer 112 to expose the top metal layer 1〇4. Finally, as shown in FIG. 1B, metal bumps 960〇7/〇5l6-A41218-TW/£Trcheii 200937542 120 (eg, gold bumps) are formed in the exposed top metal layer 1〇4 for flip chip packaging. . e φ However, as shown in Figure 1, the oxygen-cut layer formed by high-density plasma deposition technology will form a protrusion (or protrusion) on the top metal layer 1G4. This is a high-density plasma deposition technique. Due to its own process characteristics, the height of this point is about 7,000. The subsequently deposited tantalum nitride layer 112 is also an uneven layer of oxidized stone underneath, so that the thickness of the deposited layer should not be too thin. Generally, at least about 7000 Å is deposited, otherwise the surface of the protective layer is too large to provide uniform protection to the underlying components. Tantalum nitride is a relatively hard material. Too thick will increase the stress and cause damage to the substrate 100. In addition, as shown in FIG. 1 , when the metal bump 120 is formed on the opening 116 of the top metal layer 104 , the metal bump 120 needs to be filled into the opening 116 ′ of the depth τι, where T1 is about 14,000, due to the top metal layer. The upper yttrium oxide layer 108 and the tantalum nitride layer 非常2 are very thick, which increases the amount of material used for the metal bumps 120, and increases the manufacturing cost. In order to solve the above problems, the present invention provides a semiconductor structure having an ultra-thin protective layer, which can improve the flatness of the protective layer and avoid cracking of the protective layer, and can effectively save the protective layer and the metal bump (Bump). The material used. The manufacturing process of the embodiment of the present invention will be described below in conjunction with Figures 2A-2F. As shown in FIG. 2A, a semiconductor substrate 200 is provided. A semiconductor substrate, such as a germanium wafer, may have various completed semiconductor components, such as transistors, resistors, logic components, etc., which are shown here only as a flat substrate for simplicity of illustration. A plurality of top metal layers 204 are formed on the semiconductor substrate, and a plurality of gaps 202 are formed between the plurality of top metal layers 204 and the semiconductor substrate 200. Wherein, the top metal layer 204 may comprise a commonly used metal, for example, 96007/0516-A41218-TW/^JYChen 200937542 as described in 'Copper, Silver, Gold, or a combination thereof. The top metal layer 204 can be formed on the semiconductor substrate 200, for example, by vapor deposition or electroplating, and then form a plurality of top metal layers 204 separated by, for example, lithography and etching processes, and leaving a plurality of gaps 202 in the top metal layer. Between 204. Subsequently, a termination layer 206 is deposited over the top metal layer 204 prior to filling the gap 202 of the top metal layer 204 with an oxide layer. As will be understood from the following description, the termination layer will also be subsequently used as a termination layer when the oxide layer is planarized. In this embodiment, the termination layer 206 is conformally deposited on the upper surface of the top metal layer 2〇4, the sidewall of the crucible, and the upper surface of the semiconductor substrate 200. The material of the termination layer 206 is, for example, bismuth oxynitride, and may have a thickness of about 400 to 1,500 Å. Figure 2B. The formation of the opaque, electropolymerized layer 208. The high density plasma deposited layer 208 is typically an oxide such as oxidized stone. It has excellent hole filling ability. After the high-density plasma deposition layer is sufficiently filled with the gap 2〇2, a protrusion is formed on the top metal layer 204. This is due to the process characteristics of the high density electropolymer deposition technology itself. After that, as shown in Fig. 2C, the high-density plasma deposition layer 208 having the protrusions is subjected to a planarization process to form a south-density plasma deposition layer 208a having a substantially flat upper surface. In one embodiment, the planarization process is, for example, chemical mechanical polishing, which can be performed in the endpoint detection mode until the termination layer 206 is exposed. Or also: 'It can be done in time mode to stop the chemical mechanical polishing before exposing the termination layer 206. Although in the second (the figure, there is still a portion of the residual high-density plasma deposition layer 208a on the top metal layer 204), it should be understood that the skilled person can also deposit a high-density plasma deposition layer on the top metal layer. 208a is completely removed leaving only the high density plasma deposited layer 2〇8a between the top stomach metal 96007/0516-A41218-TWMYChen 200937542 layer 204. _2D shows the formation of the protective layer 212. The protective layer 212 is, for example, Tantalum nitride. In one embodiment, since the high-density plasma deposition layer 208a has a permeate flat upper surface, the protective layer 212 is on the flat lower joint surface 21, so the protective layer can be greatly reduced. The thickness of 212 provides a protective layer having a substantially flat upper surface 212a. The thickness of the protective layer 212 is preferably about 5000A to 6500 A. In one embodiment, the top metal layer 2〇4 is on the surface.
面至保護層212上表面212a之總厚度例如是小於約 7000A。不僅可節省保護層的用料也可獲得品質佳應力馬 響小之保護層。 .的 第2E及2F圖顯示一金屬凸塊(Bump)製程。首先，利 用微影與蝕刻在頂部金屬層2〇4上形成開口 216 (如第2 E圖），開口 216之深度T2相當於保護層212及終止層 2〇6之厚度，可在約700〇A。開口 216穿過保護層、高 密度電漿沉積層208a、及終止層206 ’露出至少部分頂部 金屬層204。之後，在開口 216中沉積金屬凸塊22〇 (如第 2F圖），可例如以氣相沉積或電鍍方式形成。金屬凸塊 220可略高於保護層212之上表面212a ’其厚度例如是小 於約8000人。金屬凸塊220可包括金、銀、鋼、锡、錯、 或前述之組合。:, 此外’在形成金屬凸塊22Q前，可先在開口表面形成 下凸塊金屬層（未顯示於圖中），這是為了改善金屬凸塊 220與頂部金屬層204之間的接面接合性，以及保護頂部 金屬層204’並可作為金屬凸塊220在可能之迴銲（refl〇w) 96007/0516-A41218-TW/f/JYChen 200937542 製程中的潤濕層。下凸塊金屬層可包括鈦、鎢、金或前述 之組合。 ❹與實質平坦的表面，對於半導體基板之應力傷害也能減到 最低，使得隨後可能之覆晶封裝的良率提高。本發明實施 例之優點之一是其具有超薄保護層特性之結構，除了可節 如第2 F圖所示，金屬凸塊220填入保護層212、高密 度電漿沉積層208a、及終止層206的厚度非常小，例如是 小於約7000人。因此，可節省金屬凸塊220之用料。尤其， 當選用金(gold)來作為金屬凸塊220的主要材質時，以本發 明之方法製造可大幅降低生產成本。除此之外，具較高應 力的保護層212 (例如是氮化矽層），因具有較薄的厚度 省用材以減少成本外，還可減少封裝所需之空間以及減小 應力傷害而增加產品中元件的密度及可靠度，提升其效能。 雖然本發月已以數個較佳實施例揭露如上，然其並非The total thickness of the surface to the upper surface 212a of the protective layer 212 is, for example, less than about 7000 Å. Not only can the material of the protective layer be saved, but also the protective layer with good quality and low stress. Figures 2E and 2F show a metal bump process. First, an opening 216 is formed on the top metal layer 2〇4 by lithography and etching (as shown in FIG. 2E), and the depth T2 of the opening 216 corresponds to the thickness of the protective layer 212 and the termination layer 2〇6, which may be about 700〇. A. The opening 216 extends through the protective layer, the high density plasma deposited layer 208a, and the termination layer 206' to expose at least a portion of the top metal layer 204. Thereafter, a metal bump 22 (as in Figure 2F) is deposited in opening 216, which may be formed, for example, by vapor deposition or electroplating. The metal bumps 220 may be slightly above the upper surface 212a' of the protective layer 212, for example, having a thickness of less than about 8,000. Metal bumps 220 may comprise gold, silver, steel, tin, aluminum, or a combination of the foregoing. In addition, before the metal bumps 22Q are formed, a lower bump metal layer (not shown) may be formed on the surface of the opening, in order to improve the joint between the metal bumps 220 and the top metal layer 204. And to protect the top metal layer 204' and as a wetting layer of the metal bump 220 in a possible reflow process (refl〇w) 96007/0516-A41218-TW/f/JYChen 200937542. The lower bump metal layer may comprise titanium, tungsten, gold or a combination of the foregoing. With a substantially flat surface, the stress damage to the semiconductor substrate can be minimized, resulting in an increased yield of the subsequent flip chip package. One of the advantages of the embodiments of the present invention is that it has a structure of ultra-thin protective layer characteristics, except that as shown in FIG. 2F, the metal bumps 220 are filled with the protective layer 212, the high-density plasma deposition layer 208a, and terminated. The thickness of layer 206 is very small, for example, less than about 7,000 people. Therefore, the material for the metal bumps 220 can be saved. In particular, when gold is used as the main material of the metal bump 220, the production by the method of the present invention can greatly reduce the production cost. In addition, the higher stress protective layer 212 (for example, a tantalum nitride layer) has a thinner thickness and materials to reduce the cost, and also reduces the space required for packaging and reduces stress damage. The density and reliability of components in the product enhances its performance. Although this month has been disclosed above in several preferred embodiments, it is not
【圖式簡單說明】 第1A-1B圖為〜系列剖 系歹】。彳面圖，用以說明發明人所知的[Simple description of the diagram] Figure 1A-1B is a series of sections 歹]. a map showing the inventor's knowledge
的半導體結構及製作流程。 ，用以說明本發明一實施例 96007/0516-A41218-TW/f7JYChen 200937542 【主要元件符號說明】 1〇〇~基板；104〜頂部金屬層；102〜間隙；108〜氧化矽 層；112〜氮化矽層；Η〜高度；116〜開口； 120〜金屬凸塊； Τ1〜深度；200〜半導體基板；204〜頂部金屬層；206〜終止 層；202~間隙；208、208a〜高密度電漿沉積層；212〜保護 層；212a〜上表面；212b〜下接面；216〜開口； T2〜深度； ❹ 220〜金屬凸塊。Semiconductor structure and manufacturing process. For the purpose of illustrating an embodiment of the present invention 96007/0516-A41218-TW/f7JYChen 200937542 [Description of main components] 1〇〇~substrate; 104~top metal layer; 102~gap; 108~ yttrium oxide layer; 112~nitrogen矽 矽 layer; Η ~ height; 116 ~ opening; 120 ~ metal bump; Τ 1 ~ depth; 200 ~ semiconductor substrate; 204 ~ top metal layer; 206 ~ termination layer; 202 ~ gap; 208, 208a ~ high density plasma Deposited layer; 212~ protective layer; 212a~ upper surface; 212b~ lower junction; 216~ opening; T2~depth; ❹ 220~ metal bump.
96007/0516-A41218-TW/f/JYChen 1196007/0516-A41218-TW/f/JYChen 11