CN112530491A - 静态随机存取存储器装置 - Google Patents
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Abstract
本发明公开一种静态随机存取存储器装置,包含两反相器和第一至第三晶体管。第一反相器的第一端耦接在第一数据节点,而第二端耦接在第二数据节点。第二反相器的第一端耦接在第二数据节点,而第二端耦接在第一数据节点。第一晶体管包含耦接在第一数据节点的第一端、第二端以及控制端。第二晶体管包含耦接在第一晶体管的第二端的第一端,耦接在第一位线的第二端,以及控制端。第三晶体管包含耦接在第一晶体管的第二端和第二晶体管的第一端之间的第一端、第二端以及耦接在第一数据节点的控制端。
Description
技术领域
本发明涉及一种静态随机存取存储器装置,尤其涉及一种具保持电路的静态随机存取存储器装置。
背景技术
在一嵌入式静态随机存取存储器(embedded static random access memory,embedded SRAM)中,包含有逻辑电路(logic circuit)和与逻辑电路连接的静态随机存取存储器。静态随机存取存储器本身属于一种易失性(volatile)的存储器单元(memorycell),亦即当供给静态随机存取存储器的电力消失之后,所存储的数据会同时抹除。静态随机存取存储器存储数据的方式是利用存储器单元内晶体管的导电状态来达成,静态随机存取存储器的设计是采用互耦合晶体管为基础,没有电容器放电的问题,不需要不断充电以保持数据不流失,也就是不需作存储器更新的动作,这与同属易失性存储器的动态随机存取存储器(Dynamic Random Access Memory,DRAM)利用电容器带电状态存储数据的方式并不相同。静态随机存取存储器的存取速度相当快,因此有在计算机系统中当作快取存储器(cache memory)等的应用。
现有技术的静态随机存取存储器常使用六晶体管six-transistor,6T)的架构,其中两对晶体管分别组成两个反相器,此两反相器的输入和输出交叉连接以形成一锁存(latch)电路以将数据锁存在两个存储结点,再由两个存取晶体管来分别控制两存储结点的读写。传统的6T-SRAM存储器单元使用同一存取晶体管来控制同一存储结点的读取,在低电压操作时由于读取静态噪声边界(read static noise margin,SNM)与写入边界(writemargin)双双降低,再加上制程的漂移,因此容易出现半选择干扰,(half-selectdisturb)、读取干扰(read disturb)和写入失败(write failure)等问题。
发明内容
本发明提供一种静态随机存取存储器单元,其包含一第一反相器、一第二反相器,以及第一至第三晶体管。该第一反相器的第一端耦接在一第一数据节点,而第二端耦接在一第二数据节点。该第二反相器的第一端耦接在该第二数据节点,而第二端耦接在该第一数据节点。该第一晶体管其包含耦接在该第一数据节点的一第一端,一第二端,以及一控制端。该第二晶体管包含耦接在该第一晶体管的该第二端的一第一端,耦接在一第一位线的一第二端,以及一控制端。该第三晶体管包含耦接在该第一晶体管的该第二端和该第二晶体管的该第一端之间的一第一端,一第二端,以及耦接在该第一数据节点的一控制端。
附图说明
图1为本发明一实施例中一种10T-SRAM存储器单元的示意图。
图2为本发明另一实施例中一种10T-SRAM存储器单元的示意图。
图3为本发明另一实施例中一种10T-SRAM存储器单元的示意图。
【主要元件符号说明】
10、20、30 十晶体管静态随机存取存储器单元
T1~T6 存取晶体管
T7、T9 上拉晶体管
T8、T10 下拉晶体管
INV1、INV2 反相器
VDD 电压源
GND1、GND2 接地电位
Q1、Q2 存储结点
BL、BLB 位线
WWL、RWL 字线
具体实施方式
图1为本发明一实施例中一种十晶体管静态随机存取(ten-transistor SRAM,10T-SRAM)存储器单元10的示意图。10T-SRAM存储器单元10包含晶体管T1~T10,每一晶体管可依据其控制端的电位来控制其第一端和第二端之间的信号导通路径。在本发明实施例中,晶体管T1~T10可由金属氧化物半导体场效应晶体管(metal-oxide-semiconductorfield-effect transistor,MOSFET)或双载子接面晶体管(bipolar junctiontransistor,BJT)来实作,然而晶体管T1~T10的实作方式并不限定本发明的范围。
存取晶体管T1的第一端耦接在存储节点Q1,而控制端耦接至字线WWL。存取晶体管T2的第一端耦接在存取晶体管T1的第二端,第二端耦接在位线BL,而控制端耦接至字线RWL。存取晶体管T3的第一端耦接在存取晶体管T1的第二端和存取晶体管T2的第一端之间,第二端耦接至接地电位GND2,而控制端耦接在存储节点Q1。存取晶体管T4的第一端耦接在存储节点Q2,而控制端耦接至字线WWL。存取晶体管T5的第一端耦接在存取晶体管T4的第二端,第二端耦接在位线BLB,而控制端耦接至字线RWL。存取晶体管T6的第一端耦接在存取晶体管T4的第二端和存取晶体管T5的第一端之间,第二端耦接至接地电位GND2,而控制端耦接在存储节点Q2。
上拉晶体管T7和下拉晶体管T8构成一反相器INV1,其两端点分别耦接在电压源VDD与接地电位GND1。同样地,上拉晶体管T9与下拉晶体管T10构成一反相器INV2,其两端点亦分别耦接在电压源VDD与接地电位GND1。反相器INV1和反相器INV2构成一锁存电路,使数据可以锁存在存储结点Q1或Q2。更详细地说,存储结点Q1耦接至上拉晶体管T9和下拉晶体管T10的控制端,以及耦接至下拉晶体管T8、上拉晶体管T7和存取晶体管T1的第一端。同样地,存储结点Q2耦接至下拉晶体管T8和上拉晶体管T7的控制端,以及耦接至下拉晶体管T10、上拉晶体管T9和存取晶体管T4的第一端。
10T-SRAM存储器单元10的数据写入动作是利用外部电压源通过相对应位线BL和BLB去改变存储节点Q1和Q2的内容,其中存取晶体管T1和T2可控制位线BL和存储结点Q1之间的数据写入路径,而存取晶体管T4和T5可控制位线BL和存储结点Q1之间的数据写入路径。10T-SRAM存储器单元10的数据读取动作则是将相对应位线BL和BLB先均衡至同一电位,然后让存储节点Q1和Q2的内容去影响位线BL和BLB的电位,再由外部感应放大器来放大位线BL和BLB之间的电位差,其中存取晶体管T2和T3可控制位线BL放电至接地电位GND2的路径,而存取晶体管T5和T6可控制位线BLB放电至接地电位GND2的路径。
在写入运作时,外部电压源会将相关写入数据的电压施加至位线BL和BLB,施加开启电压至位线RWL和WWL以导通存取晶体管T1、T2、T4和T5,使得位线BL和BLB的电位能改变存储节点Q1和Q2的内容。
在读取运作时,外部电压源会将位线BL和BLB先均衡至同一电位,施加开启电压至位线RWL以导通存取晶体管T2和T5,以及施加关闭电压至位线WWL以关闭存取晶体管T1和T4。当存储节点Q1的电位能开启存取晶体管T3时,存储节点Q2的电位会关闭存取晶体管T6,此时位线BL会通过导通的存取晶体管T2和T3放电至接地电位GND2,而位线BLB会因为关闭的存取晶体管T6而不会被存储节点Q2的电位所影响。同理,当存储节点Q1的电位能关闭存取晶体管T3时,存储节点Q2的电位会导通存取晶体管T6,此时位线BLB会通过导通的存取晶体管T5和T6放电至接地电位GND2,而位线BL会因为关闭的存取晶体管T3而不会被存储节点Q1的电位所影响。
本发明实施例10T-SRAM存储器单元10的写入路径包含两颗堆迭晶体管(T1和T2、T4和T5)。相较于单颗晶体管的单层栅极介电层,采用多颗堆迭晶体管可提升载子迁移率,因此可提升驱动电流和降低漏电电流。此外,字线RWL的设置方向垂直于字线WWL的设置方向,可分别控制10T-SRAM存储器单元10中每一写入路径上的两个晶体管,因此可降低半选择干扰。
图2为本发明另一实施例中一种10T-SRAM存储器单元20的示意图。10T-SRAM存储器单元20包含晶体管T1~T10,其耦接方式和10T-SRAM存储器单元10相同。在图2所示的实施例中,晶体管T1~T2、T4~T5、T7和T9为P型晶体管,而晶体管T3、T6、T8和T10为N型晶体管。对P型晶体管来说,开启电压为逻辑0,而关闭电压为逻辑1;对N型晶体管来说,开启电压为逻辑1,而关闭电压为逻辑0。由于具有相同掺杂类型存取晶体管T1、T2、T4和T5可提供相同偏移速度的载流子,因此可提高数据写入路径的写入边界。此外,存取晶体管T2的导通与否取决于位线BL和RWL的电位,存取晶体管T5的导通与否直接取决于位线BLB和RWL的电位,因此不会限制读取电流的值。
图3为本发明另一实施例中一种10T-SRAM存储器单元30的示意图。10T-SRAM存储器单元30包含晶体管T1~T10,其耦接方式和10T-SRAM存储器单元10相同。在图3所示的实施例中,晶体管T1~T2、T4~T5、T8和T10为N型晶体管,而晶体管T3、T6、T7和T9为P型晶体管。对P型晶体管来说,开启电压为逻辑0,而关闭电压为逻辑1;对N型晶体管来说,开启电压为逻辑1,而关闭电压为逻辑0。由于具有相同掺杂类型存取晶体管T1、T2、T4和T5可提供相同偏移速度的载流子,因此可提高数据写入路径的写入边界。
综上所述,本发明提供一种10T-SRAM存储器单元,其可降低半选择干扰和漏电电流,同时提升数据读取和写入的效率。
以上所述仅为本发明的优选实施例,凡依本发明权利要求书所做的均等变化与修饰,皆应属本发明的涵盖范围。
Claims (10)
1.一种静态随机存取存储器单元,其包含:
第一反相器,其包含:
第一端,耦接在第一数据节点;以及
第二端,耦接在第二数据节点;
第二反相器,其包含:
第一端,耦接在该第二数据节点;以及
第二端,耦接在该第一数据节点;
第一晶体管,其包含:
第一端,耦接在该第一数据节点;
第二端;以及
控制端;
第二晶体管,其包含:
第一端,耦接在该第一晶体管的该第二端;
第二端,耦接在第一位线;以及
控制端;以及
第三晶体管,其包含:
第一端,耦接在该第一晶体管的该第二端和该第二晶体管的该第一端之间;
第二端;以及
控制端,耦接在该第一数据节点。
2.如权利要求1所述的静态随机存取存储器单元,其中该第二晶体管的掺杂类型相异于该第三晶体管的掺杂类型。
3.如权利要求1所述的静态随机存取存储器单元,其中该第一晶体管的掺杂类型相同于该第二晶体管的掺杂类型。
4.如权利要求1所述的静态随机存取存储器单元,其中:
该第一晶体管和该第二晶体管具有第一掺杂类型;
该第三晶体管具有第二掺杂类型;且
该第一掺杂类型相异于该第二掺杂类型。
5.如权利要求1所述的静态随机存取存储器单元,其中:
该第二晶体管的该控制端耦接至第一字线;
该第一晶体管的该控制端耦接至第二字线;而
该第一字线垂直于该第二字线。
6.如权利要求1所述的静态随机存取存储器单元,其还包含:
第四晶体管,其包含:
第一端,耦接在该第二数据节点;
第二端;以及
控制端,耦接在该第一晶体管的该控制端;
第五晶体管,其包含:
第一端,耦接在该第四晶体管的该第二端;
第二端,耦接在第二位线;以及
控制端,耦接在该第二晶体管的该控制端;以及
第六晶体管,其包含:
第一端,耦接在该第四晶体管的该第二端和该第五晶体管的该第一端之间;
第二端,耦接在该第三晶体管的该第二端;以及
控制端,耦接在该第二数据节点。
7.如权利要求6所述的静态随机存取存储器单元,其中该第二晶体管的掺杂类型相异于该第三晶体管的掺杂类型,且该第五晶体管的掺杂类型相异于该第六晶体管的掺杂类型。
8.如权利要求6所述的静态随机存取存储器单元,其中该第一晶体管的掺杂类型相同于该第二晶体管的掺杂类型,且该第四晶体管的掺杂类型相同于该第五晶体管的掺杂类型。
9.如权利要求6所述的静态随机存取存储器单元,其中:
该第一晶体管、该第二晶体管、该第四晶体管和该第五晶体管具有第一掺杂类型;
该第三晶体管和该第六晶体管具有第二掺杂类型;且
该第一掺杂类型相异于该第二掺杂类型。
10.如权利要求6所述的静态随机存取存储器单元,其中:
该第二晶体管的该控制端和该第五晶体管的该控制端耦接至第一字线;
该第一晶体管的该控制端和该第四晶体管的该控制端耦接至第二字线;而
该第一字线垂直于该第二字线。
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US20230120936A1 (en) * | 2021-01-17 | 2023-04-20 | Metis Microsystems, Llc | Fast, Energy Efficient CMOS 2P1R1W Register File Array using Harvested Data |
US20230042652A1 (en) * | 2021-05-27 | 2023-02-09 | Metis Microsystems | Fast, Energy Efficient 6T SRAM Arrays using Harvested Data |
CN114822637B (zh) * | 2022-06-08 | 2022-10-14 | 安徽大学 | 一种基于10t-sram单元的电路结构、芯片及模块 |
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