CN112400237B - 具有金刚石集电极和电流隧穿层的p-n二极管和p-n-p异质结双极晶体管 - Google Patents

具有金刚石集电极和电流隧穿层的p-n二极管和p-n-p异质结双极晶体管 Download PDF

Info

Publication number
CN112400237B
CN112400237B CN201980044286.4A CN201980044286A CN112400237B CN 112400237 B CN112400237 B CN 112400237B CN 201980044286 A CN201980044286 A CN 201980044286A CN 112400237 B CN112400237 B CN 112400237B
Authority
CN
China
Prior art keywords
diamond
layer
diode
semiconductor material
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201980044286.4A
Other languages
English (en)
Other versions
CN112400237A (zh
Inventor
马振强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wisconsin Alumni Research Foundation
Original Assignee
Wisconsin Alumni Research Foundation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wisconsin Alumni Research Foundation filed Critical Wisconsin Alumni Research Foundation
Publication of CN112400237A publication Critical patent/CN112400237A/zh
Application granted granted Critical
Publication of CN112400237B publication Critical patent/CN112400237B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/88—Tunnel-effect diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66022—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6603—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02527—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1602—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10336—Aluminium gallium arsenide [AlGaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10337—Indium gallium arsenide [InGaAs]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提供了包含p型掺杂的金刚石的P‑N二极管和包括p‑n二极管的器件如p‑n‑p异质结双极晶体管。在p‑n二极管中，在p‑n结处的金刚石具有正电子亲和力，并被无机材料薄层钝化，该无机材料薄层提供了使结合界面态钝化的隧穿层，而不会阻碍跨界面的载流子传输。

Description

具有金刚石集电极和电流隧穿层的P-N二极管和P-N-P异质结 双极晶体管
引用政府权利
本发明是在NAVY/ONR授予的N00014-18-1-2032以及DARPA授予的N00014-12-1-0884和N00014-12-1-0077的政府支持下完成的。政府拥有本发明的某些权利。
相关申请的交叉引用
本申请要求于2018年7月9日提交的美国专利申请号16/029,811的优先权，其全部内容通过引用合并于此。
背景技术
金刚石是下一代高功率开关器件最需要的宽带隙材料之一，因为它具有优异的物理和电气特性，包括高击穿电场、高导热率和高载流子迁移率。随着通过高生长速率化学气相沉积(CVD)生长大面积单晶金刚石衬底的发展，金刚石器件的研究一直在稳步前进。然而，由于深的施主能级，在金刚石中使用氮或磷来实现n型掺杂非常困难。结果，基于金刚石的电子设备主要基于p型掺杂的金刚石。
已经实现了用磷对(001)金刚石衬底进行N型掺杂。然而，由于深的磷施主水平，n型层的电阻率仍高。因此，尽管基于金刚石的p-n结二极管(PND)显示出高击穿电压，但它们也具有高导通电阻，因为非欧姆金属/n型金刚石接触和n型掺杂的金刚石层产生高电阻，这不利于获得高功率、低损耗的二极管。另一方面，尽管p型金刚石能够为基于p型金刚石的肖特基(Schottky)二极管提供高击穿电压，但仍在导通电阻和击穿电压之间存在权衡。为了减小p型耗尽层的电阻，需要增加受主浓度，并且所得耗尽区变窄，导致击穿电压降低。(参见例如A.Traore等人，Zr/oxidized diamond interface for high power Schottkydiodes，Appl.Phys.Lett.104，052105(2014)。)
发明内容
提供了包括p型掺杂金刚石(“p型金刚石”)的P-N二极管和结合了该p-n二极管的器件(例如p-n-p HBT)。
p-n二极管的一个实施方案包括：(a)具有上表面的p型金刚石层，该上表面具有正的电子亲和力；(b)单晶n型半导体材料层，该单晶半导体材料具有与金刚石不同的晶格常数；(c)设置在金刚石的上表面和单晶n型半导体材料层的下表面之间并与之接触的电流隧穿层。电流隧穿层包含无机材料，该无机材料具有的带隙比金刚石和单晶n型半导体材料的带隙宽，并且该无机材料不是单晶n型半导体材料的天然氧化物。
异质结双极晶体管的一个实施方案包括：(a)集电极，其包括具有上表面的p型金刚石层，该上表面具有正电子亲和力；(b)基极，其包括单晶n型半导体材料层，所述单晶n型半导体材料具有与所述金刚石不同的晶格常数；(c)设置在金刚石层的上表面和单晶n型半导体材料层的下表面之间并与之接触的电流隧穿层；(d)包括单晶p型半导体材料层的发射极。电流隧穿层包含无机材料，该无机材料具有的带隙比金刚石和单晶n型半导体材料的带隙宽，并且该无机材料不是单晶n型半导体材料的天然氧化物。
通过阅读以下附图、详细描述和所附权利要求，本发明的其他主要特征和优点对于本领域技术人员将变得清楚。
附图说明
以下将参考附图描述本发明的说明性实施方案，其中相似标号表示相似元件。
图1A是金刚石-集电极异质结双极晶体管(HBT)的一个实施方案的示意图。图1B示出了图1A的HBT的能级和能带图，其具有负电子亲和力(χ)金刚石集电极。图1C示出了图1A的HBT的能级和能带图，其具有正电子亲和力金刚石集电极。
图2A是金刚石-集电极HBT的另一实施方案的示意图。图2B示出了图2A的HBT的能级和能带图，其具有正电子亲和力金刚石集电极。
图3是示出使用纳米膜转移和结合工艺制造金刚石-集电极HBT的方法的示意图。
图4A示出了将n型掺杂的GaAs纳米膜转移到原子层沉积法(ALD)沉积的电流隧穿层上以形成p-n二极管。图4B示出了二极管结构的示意性截面图。
图5A的子图(i)示出了具有负电子亲和力的p-金刚石层的p-n二极管的能带对齐。图5A的子图(ii)示出了具有正电子亲和力的p-金刚石层的p-n二极管的能带对齐。图5B的子图(i)示出了图5A子图(i)的p-n二极管在反向偏压下耗尽区延伸到n-GaAs中的能带对齐。图5B的子图(ii)示出了图5A子图(ii)的p-n二极管在反向偏压下耗尽区延伸到p-金刚石中的能带对齐。图5C的子图(i)示出了图5A子图(i)的p-n二极管的I-V特性。图5C的子图(ii)示出了图5A子图(ii)的p-n二极管的I-V特性。
图6A显示了在室温下在空气中具有负电子亲和力的金刚石p-n二极管的电流密度-电压(J-V)特性。图6B示出了在室温下在空气中具有正电子亲和力金刚石的金刚石p-n二极管的J-V特性。
图7A以半对数标示出图5A子图(ii)的GaAs/金刚石n-p二极管在室温下在空气中在反向电压条件下的电流密度-电压特性，该二极管的电极面积为60μm×60μm。图7B示出了图5A子图(ii)的GaAs/金刚石n-p二极管的击穿电压的线性比例图。图7C示出了使用dV/dJ估计的金刚石的差分电阻。
图8示出了实施例2的p-n-p HBT的层在彼此接触之前的能带对齐，其中记录了带隙值。
图9A-9C描绘了p-n-p金刚石HBT的DC特性。图9A示出了p-Si NM发射极和n-Ge NM基极异质结二极管(E-B结)的电流密度-电压特性。图9B示出了n-GeNM基极和p-金刚石集电极异质结二极管(C-B结)的电流密度-电压特性。图9C显示了具有0.5μA台阶(step)的HBT的共发射极(common emitter)IC–VCE特性。图9D描绘了Gummel图，该图显示了在2.8V的VEB下49的最大电流增益(βmax)。
图10A-10C示出了p-n-p金刚石HBT的电流增益和射频(RF)特性。图10A示出了电流增益和差分β作为集电极电流密度的函数，不同的VCB从0V至2V。图10B描绘了在0.06μA的偏置点IB和-5V的VCB处的单向功率增益(U)和最大稳定增益(MSG)/最大可用增益(MAG)与频率的关系。图9C示出fT和fmax作为集电极电流密度的函数。
图11A是使用具有1nm Al2O3 ALD中间层的Ti/Pt/Au金属叠层的Al2O3辅助的欧姆金属化至金刚石衬底的示意图。图11B示出了退火之后两个集电极金属触点之间的I-V特性。
具体实施方式
提供了包括p型掺杂金刚石(“p型金刚石”)的P-N二极管和结合了该p-n二极管的器件(例如p-n-p HBT)。在p-n二极管中，p-n结处的金刚石在二极管的工作温度下具有正电子亲和力，并被无机材料薄层钝化，该薄层充当电流隧穿层并钝化结合界面态，而不阻碍载流子跨界面传输。
p-n二极管的特征在于高击穿电压、低导通电阻和高Baliga功率品质因数(BFOM)。作为说明，p-n二极管的各种实施方案在室温(25℃)下具有至少10V的击穿电压。这包括在25℃下击穿电压为至少100V的p-n二极管，还包括在25℃下击穿电压为至少1000V的p-n二极管。另外，p-n二极管的各种实施方案具有1GW/cm2或更高的BFOM。在实施例中提供了测量p-n二极管的击穿电压和BFOM的方法。
在p-n二极管中，金刚石的电子表面特性在二极管及结合了其的器件的性能中起着重要作用，因为表面特性影响p-n结的能带弯曲、导电率和表面态分布。为了获得高性能p-n二极管的适当能带对齐，金刚石表面在p-n二极管的工作温度下应具有正电子亲和力。
通常，未经任何表面处理的化学气相沉积(CVD)生长的金刚石衬底具有氢和氧混合的封端(terminated)表面，其具有负电子亲和力。然而，对于器件如HBT，负电子亲和力是不利的，因为在金刚石表面处的空穴积累可缩短进入金刚石的耗尽距离，因此降低p-n二极管的击穿电压。为了避免在金刚石表面积累空穴，可以对该表面进行氧处理以对金刚石提供氧封端为主的表面条件和正电子亲和力。此外，主要的氧封端有利于均匀沉积基于氧化物的电流隧穿层(例如Al2O3)，这对于随后转移和结合n型半导体纳米膜以完成具有高品质异质结界面的p-n二极管是重要的。
通过在氧化条件下将金刚石暴露于含氧环境中，可以为p-n二极管中的金刚石提供主要的氧表面封端以表现出正电子亲和力。例如，可以将金刚石暴露于氧等离子体中，或在臭氧环境中暴露于UV中，或在例如200℃的温度下将样品在H2SO4和HNO3中浸泡10分钟进行氧化化学处理。
在HBT中，正电子亲和力金刚石与表面钝化的组合提供了高的基极-集电极二极管击穿电压。为了使HBT获得高电流增益，发射极材料应具有比基极材料大的带隙。满足此标准的发射极/基极材料组合的示例包括Si/Ge、Si/SiGe、SiGe/Ge和III-V半导体对，例如AlGaAs/GaAs、GaInP/GaAs、InAlAs/InP、InAlAs/InGaAs和InP/InGaAs。
在图1A-1C中示出了表面性质对GaAs基极金刚石集电极HBT的能带图的影响。在图1A中示出了HBT的截面图。HBT包括无意掺杂的金刚石衬底，在其上形成有p型金刚石集电极和重度p型掺杂(P+)的子集电极。子集电极用于提供与集电极接触金属的良好欧姆接触，并提供连接中度p型掺杂(P-)金刚石层的低电阻电流路径。单晶n型GaAs的n型层(GaAs NM)用作基极，并通过薄的电流隧穿层与金刚石集电极隔开。发射极包括下方中等p型掺杂的AlGaAs层和上方重度p型掺杂的GaAs层(即发射极接触层)，其用于提供与发射极接触金属的良好欧姆接触。
图1B示出了图1A的异质结构叠层中的各层(左)和异质结构(右)的能级和能带结构，其中P-金刚石(C)具有负电子亲和力。如能带结构图所示，负电子亲和力导致在GaAs/金刚石界面处在金刚石中的空穴积累以及在反向偏压下耗尽层区域延伸到n型GaAs基极层中。这限制了基极-集电极二极管的击穿电压，并可导致大量的漏电流。
图1C示出了图1A的异质结构叠层中的各层(左)和异质结构(右)的能级和能带结构图，其中P-金刚石具有正电子亲和力。如带结构图所示，正电子亲和力导致耗尽区在反向偏压下延伸到p型金刚石集电极层。这增加了基极-集电极二极管的击穿电压，并减小了漏电流。正电子亲和力的大小可以随表面封端条件而变化。在金刚石表面上，与朝向氢封端相比，越朝向氧封端，正电子亲和力值越大。正电子亲和力的值也影响基极和集电极之间的价带对齐。对于约25℃至约300℃范围内的工作温度，约0.02eV至0.05eV范围内的电子亲和力就足够了。
图2A和2B分别示出了具有正电子亲和力的金刚石集电极HBT的另一实施方案的结构和能带图。该HBT包括无意掺杂的金刚石衬底，在其上形成有p型金刚石集电极和重度p型掺杂(P+)金刚石子集电极。子集电极用于提供与集电极接触金属的良好欧姆接触以及连接中等p型掺杂(P-)金刚石层的低电阻电流路径。单晶n型InGaAs的n型层(InGaAs NM)用作基极，并通过薄电流隧穿层与金刚石集电极分开。发射极包括下方中等p型掺杂的InAlAs层和上方重度p型掺杂的InGaAs层(发射极接触)，其用于提供与发射极接触金属的良好欧姆接触。
可以使用膜转移和结合工艺来制造p-n二极管，该膜转移和结合工艺允许独立于p型层的材料来选择n型层的材料。因此，转移和结合工艺使得能够将多种不同的半导体材料集成到p-n二极管和结合了p-n二极管的器件中。
在图3中示意性地示出了用于形成HBT的方法的一个实施方案。该结构建立在具有上表面的p型金刚石集电极301(子图(i))上，该上表面已被处理以在基极-集电极二极管的预期工作温度下为金刚石提供正电子亲和力。如实施例所示，这可以使用氧处理从而为金刚石集电极301的上表面提供主要的氧表面封端来完成。在氧封端的集电极301的上表面上，沉积该电流隧穿层302。电流隧穿层的厚度通常仅需要大约为与其结合的半导体材料层的表面的均方根(rms)粗糙度。作为说明，在一些实施方案中，电流隧穿层的厚度在约0.5nm至约10nm的范围内。这包括其厚度为约0.5nm至约5nm或约0.5nm至约3nm的实施方案。由于电流隧穿层的厚度在原子尺度上可不均匀，因此该层的厚度对应于跨异质结构的结合界面的层的平均厚度。
一旦沉积了电流隧穿层302，就可以将预形成的单晶n型掺杂半导体材料薄层(称为半导体纳米膜；缩写为“NM”)转移到其上表面以提供HBT的基极303，如图3的子图(i)所示。如实施例中所示，这可以使用NM转移和结合工艺来实现。如图3所示，基极层303可以任选地具有沉积在其上表面上的第二电流隧穿层304。接下来，将p型掺杂半导体NM转移并结合到基极层303上，以提供HBT发射极305。在图3的实施方案中，发射极305包括中等p型掺杂半导体材料306的下层和重度p型掺杂半导体材料307的上层。可以通过退火来增强转移的半导体NM的结合(子图(ii))。然后，可以将发射极金属叠层308沉积在发射极305上(子图(iii))。
接下来，通过异质结构向下刻蚀基极台面直至基极层303(子图(iv))，并使用例如金属化工艺沉积基极金属叠层309(子图(v)。然后将集电极台面(mesa)刻蚀至金刚石集电极301，并使用例如金属化(子图(vii))沉积集电极金属叠层310。
将预形成的单晶半导体层(即NM)转移到异质结构上的方法可以从绝缘体衬底上的半导体开始进行，其包括操作晶片、牺牲层(例如包埋氧化物层)和单晶半导体的薄层(例如单晶Ge、Si、SiGe或III-V的薄层)。III-V NM的转移也可以从生长在适当牺牲外延层上的外延层如AlGaAs/GaAs、GaInP/GaAs、InAlAs/InP、InAlAs/InGaAs和InP/InGaAs开始进行。然后，从该结构中选择性地去除牺牲层。这可以例如通过形成穿过单晶半导体薄层的孔洞(孔隙)阵列，然后选择性地化学刻蚀掉通过孔隙暴露的牺牲层来进行。这些孔隙可以规则地间隔开或随机地间隔开。结果，单晶半导体的薄层沉降在下面的操作晶片上。然后将主体材料如橡胶压头(rubber stamp)压到单晶半导体释放(release)层的上表面上，其粘附到主体材料上并从操作晶片提拉。在随后的步骤中，使单晶半导体的释放层与电流隧穿层接触并转移到电流隧穿层上。可以在转移和结合之前或之后掺杂该单晶层。然后去除主体材料。可以在美国专利公开号2016/0204306找到这种类型的转移和结合过程的更详细的描述。
用于释放给定的半导体NM的刻蚀化学将取决于从其释放该半导体NM的牺牲层。然而，对于多种半导体材料，半导体选择性刻蚀剂是已知的。例如，可以使用氢氟酸(HF)刻蚀从包埋的SiO2或GeO2层释放Si、Ge或SiGe的层；可以使用HF从包埋的AlGaAs牺牲层释放GaAs和AlGaAs的层。(在AlGaAs器件层的情况下，AlGaAs牺牲层将具有较高的铝含量。)可以使用水性NaOH从牺牲GaAsN层释放GaAs层，并且可以使用HF：H2O2：H2O刻蚀从牺牲InGaAs层释放InGaAsP层。可以使用柠檬酸：H2O2：H2O刻蚀从GaAs中释放具有高铝含量的AlGaAs。然而，可以使用其他已知的选择性刻蚀化学。
将单晶半导体层转移到异质结构上的替代性方法使用晶片结合，然后进行氢注入，以在半导体材料中产生分裂平面-这种技术有时称为Smart Cut。可以在Bruel等人，Proceedings 1995IEEE International SOI Conference，178(1995)中找到对Smart Cut过程的描述。在该技术中，在半导体衬底如半导体晶片中形成包埋的氢注入层。氢注入层的深度将确定要转移的单晶半导体层(即NM)的厚度。一旦通过氢注入形成分裂平面，衬底的表面就与异质结构接触。然后在氢注入层处分裂衬底，并去除衬底的主体。任选地，可以使用转移后化学机械抛光来使单晶半导体层减薄。
电流隧穿层是设置在构成二极管的p-n结的p型金刚石和n型半导体层之间的超薄但高度导电的层。任选地，可以在构成器件中的其他结的半导体层之间设置额外的电流隧穿层。例如，可以在p-n-p HBT的n型基极和p型发射极之间沉积额外的电流隧穿层。
电流隧穿层由带隙比构成p-n二极管的p型材料和n型材料的带隙宽的无机材料形成。电流隧穿层的特征在于它们由合适的材料制成并且足够薄以使得它们能够充当电子和/或空穴的隧穿层。也就是说，与典型的介电介质不同，它们允许电子和空穴都通过量子隧道从半导体材料的第一层穿到第二层。因此，由于金属会阻塞空穴的通过，金属不是用于电流隧穿层的合适材料。但是，各种各样的非金属无机材料都可以满足这些标准。电流隧穿层的无机材料可以是将以其整体形式充当电介质但足够薄以使其不再充当电绝缘体的材料。该无机材料的中间层使与之接触的p-n二极管的p型和n型层的表面钝化，从而使悬空键和界面态最小化或显著降低。该性质是有用的，因为当直接结合两种非晶格匹配的单晶材料时，两种材料之间形成的化学结合会产生大量的界面态。这些界面态会阻止两种材料形成理想的整流结。但是，当插入无机材料时，两种材料在物理上是分开的。如果该层足够薄并且具有化学钝化该材料的能力，则可以将界面态的数量减少到使得电子和空穴都可有效地隧穿该层的水平。无机层还在p-n二极管层或HBT中的其他层之间提供某种“胶水”。另外，无机层可以防止半导体材料在p-n二极管的层之间相互扩散。这避免了形成不需要的、中间的、交叉污染的半导体界面层。
在一些实施方案中，电流隧穿层的无机材料是氧化物。在这样的实施方案中，氧化物可以包含金属氧化物、半导体元素的氧化物和/或准金属元素的氧化物，由其组成或基本由其组成。可用于金属氧化物量子隧穿层中的氧化物的实例包括但不限于可经由ALD沉积的那些。这种氧化物的实例包括氧化铝(Al2O3)、氧化钛(TiO2)、氧化铪(HfO2)、氧化钽(Ta2O5)和二氧化硅(SiO2)。在一些实施方案中，以氧化物存在的金属、半导体或准金属元素不同于与它们接触并置于其间的其他半导体层中的任何金属、半导体或准金属元素。在电流隧穿层的实施方案中，无机氧化物不是单晶n型半导体材料或p-n二极管的p型半导体的天然氧化物。(如本文所用，术语天然氧化物是指在含氧环境中由于材料氧化而在半导体材料上一体形成的氧化物。例如，SiO2是Si的天然氧化物。)
在其他实施方案中，电流隧穿层的无机材料是氮化物。在这样的实施方案中，氮化物可以包括金属氮化物、半导体元素的氮化物和/或准金属元素的氮化物，由其组成或基本由其组成。可以用于氮化物电流隧穿层中的氮化物的例子包括但不限于可以通过ALD沉积的那些。这种氮化物的例子包括氮化铝、氮化硅和氮化钛。在一些实施方案中，以氮化物存在的金属、半导体或准金属元素不同于与它们接触并且置于其间的半导体层中的任何金属、半导体或准金属元素。
在一些实施方案中，电流隧穿层包括两个或更多个子层，其每个包括无机材料，但是，前提是子层的总组合厚度仍然足够低以允许电子和空穴隧穿穿过该层。例如，在包括多个无机氧化物子层的电流隧穿层中，可以选择无机氧化物，以使一种氧化物钝化p-n二极管的两种相邻半导体材料中的一种，而另一种氧化物钝化两种相邻半导体材料中的另一种。
实施例
实施例1：GaAs/金刚石二极管
该实施例示出了通过采用与p-/p+型金刚石衬底异质集成的重掺杂n型GaAs层实现的p-n二极管。将通过纳米膜(NM)剥离技术实现的GaAs NM转移到叠层的主要被氧化的(100)取向的表面上，该叠层包含在重硼掺杂金刚石层上的优化的轻度硼掺杂的金刚石层。在单向分离的顶部n-GaAs层和底部p+金刚石层上均形成欧姆接触。为了防止反向漏电流和降低击穿电压，在异质结构中抑制耗尽区以及金刚石和GaAs之间的界面中的缺陷对于器件性能是重要的。已知Al2O3可以有效地钝化表面的悬空键，从而显著降低IV族和III-V族材料上的漏电流。由ALD形成的高品质Al2O3层在两种单晶半导体材料之间提供了超薄但高导电性的层。在这里，Al2O3层用于获得具有钝化表面态的高品质、良好导电的界面。还显示出金刚石的主要氧封端影响击穿电压。进行了对照实验研究，比较了由主要氢封端和主要氧封端的金刚石形成的二极管的电性能。结果，对于具有主要氧封端的金刚石的p-n二极管，实现了2800A/cm2(在6V时)的高正向电流密度和约1K的击穿电压(场达到大于7.7MV/cm)。功率品质因数(BFOM)高于1.25GW/cm2。
图4A示出了将n型掺杂的GaAs纳米膜转移到原子层沉积法(ALD)沉积的电流隧穿层上以形成p-n二极管。图4B示出了GaAs/金刚石二极管的示意性结构，其包含n+/n-GaAsNM的顶层、p-/p+金刚石衬底以及其间的超薄(0.5nm)Al2O3层。分别在具有p(Pd/Ge/Au)和n(Ti/Pt/Au)触点阵列的金刚石衬底上制造二极管。使用ARIOS Inc.的MPECVD系统，在高压和高温(HPHT)合成IIb(111)单晶金刚石衬底(2×2×0.28mm3)上使用CH4和H2气体混合物沉积p掺杂的金刚石，所述金刚石衬底具有约8°的偏向角。使用以下工艺参数用于沉积：输入微波功率400W，总气压20kPa(150Torr)，300sccm H2气流，0.1％CH4/H2比率，960℃至970℃的衬底温度以及30分钟的沉积时间。为了降低杂质浓度，使用O2(O/C比率：2)沉积轻度p掺杂层。沉积后，将样品在200℃下在H2SO4和HNO3的混合物中保持10分钟，以去除任何表面污染并用氧封端表面。将接触角测量用来检查表面处理之前和之后的氧封端。随着金刚石表面封端从主要的碳氢结合变为主要的碳氧结合，表面可润湿性得到增强，导致减小的接触角。氧处理之前和之后的接触角的相应值为θ＝65.7°和17.7°，它们分别是氢封端和氧封端的典型角度值。(参见例如J.O.Hansen等人，J.Colloid.Interface Sci.，130(1989)，第347页。)为了能够研究对二极管性能的影响，随后在金刚石样品上采取二极管形成步骤用于两种表面封端。
NM转移过程
通过MOCVD，在GaAs衬底上的牺牲Al0.95Ga0.05As层的顶部上生长GaAs NM，该GaAsNM在顶部具有n+GaAs接触层和在底部具有n-GaAs层。然后，通过感应耦合等离子体(ICP)刻蚀使晶片图案化为有孔洞，以暴露Al0.95Ga0.05As层。通过用氢氟酸(HF)对牺牲层进行底切来剥离n+/n-GaAs结构。然后，使用无任何粘合剂或结合剂的转印方法将GaAs NM转移到金刚石衬底上。为了进一步加强结合，将二极管在氮氛围中于200℃至500℃的温度范围内进行退火。退火后，GaAs NM保持与金刚石表面共形。结合的GaAs/金刚石异质结的横截面的透射电子显微镜图像显示，在单晶GaAs和金刚石之间存在氧化物层，该氧化物层有效地对二极管两侧钝化了表面态。
二极管制造
对于二极管的制造，通过向下刻蚀GaAs NM和p-金刚石层并在p+金刚石衬底处停止而使各个器件进行台面隔离。从使用电子束蒸发沉积的Ti/Pt/Au(50nm/50nm/150nm)在p+衬底上形成阳极接触，并采用Pd/Ge/Au金属叠层用于与n+GaAs层的阴极接触。为了确保p+金刚石的良好欧姆接触，对暴露的p+区域进行了氢等离子体处理，以提高表面导电率。对于方形二极管，制造的器件面积为60μm×60μm。一旦完成二极管器件，就将氧等离子体(50W和30秒)施加到整个样品上，在此期间，所有暴露的金刚石区域都得到了处理，从而将表面结合从碳氢(由于对p+触点的氢等离子体处理)改变到封端碳氧。
金刚石表面封端对二极管电特性影响的模拟
为了说明主要氧封端的金刚石表面的作用以实现高击穿电压p-n二极管，对于具有不同电子亲和力(通过不同表面处理得到)的GaAs/金刚石二极管的能带对齐和电特性进行模拟。主要氢封端的金刚石可以诱导对向空气中的自由电子发射的负电子亲和力，并在表面处得到空穴积累层。另一方面，主要氧封端将电子亲和力改变为正值，这取决于氧碳结合的覆盖率而变化。在模拟中，对主要氢和主要氧封端的金刚石表面分别采用-0.5和0.2的电子亲和力。GaAs和金刚石层的掺杂浓度分别为1E19和1E17/cm3。如图5A(i)所示，由于负电子亲和力，在金刚石表面附近存在空穴积累区域，使所得金刚石的能带向上弯曲。此外，内置电场位于GaAs侧而不是金刚石侧，尽管金刚石的掺杂浓度降低了两个数量级。相比之下，对于具有正电子亲和力的GaAs/金刚石二极管，内置电压主要在金刚石中下降，如图5A(ii)所示。此外，当施加-2V的反向偏压时，如图5B(i)和5B(ii)所示，对于具有负电子亲和力的金刚石二极管，耗尽区在GaAs内延伸(图5B(i))；而对于具有正电子亲和力的金刚石(图5B(ii))，所施加的电场主要分布在金刚石中，由于较低的掺杂浓度而导致宽得多的耗尽宽度。为了实现高击穿电压，在金刚石中出现耗尽和高电场是必要的。否则，如图5C(i)所示，如果金刚石的价带高于GaAs的导带时耗尽区主要位于GaAs区(这归因于带间隧穿)，与图5C(ii)中所示的相比，漏电流将是显著的。
结果与讨论
电流密度-电压曲线比较
图6A和6B显示了两种类型的金刚石二极管的典型电流密度-电压(J-V)特性，这些二极管在空气中室温(RT)时具有不同的表面封端。如所预测的，与具有主要氧封端表面的J-V曲线相比(图6B)，具有主要氢封端的金刚石的二极管的J-V曲线(在图6A中为对数刻度和插图的线性刻度)显示出显著更高的反向漏电流。相比之下，具有正电子亲和力的GaAs/金刚石异质结显示出清晰的二极管特性，在±8V时的整流比大于1011，在约8V的正向DC电压下的正向电流密度大于2800A/cm2。对于60μmx60μm的电极，相应的总电流为106mA。此外，理想因数η低至1.27，表明扩散占主导的电流。这表明1)：良好结晶品质，具有低的作为非放射性复合中心的缺陷浓度；(2)抑制了GaAs NM和金刚石之间的界面缺陷状态，这也将有助于非放射性复合感应电流(η＝2)；和3)低寄生泄漏路径和相对小的串联电阻。
击穿特征和机理
图7A显示了反向电压下，在室温下空气中，GaAs/金刚石异质结(具有60μmx60μm电极)的半对数标度的典型漏电流密度-电压特性。漏电流对于800V左右的偏置电压呈线性关系，这表明在高反向偏置下通过p-n二极管的Fowler-Nordheim主导的隧穿过程可能是造成漏电流的原因。线性比例图(图7B)显示了击穿电压达到高达1kV。在测量过程中，使用钨微探针进行多次电测量后，电极上既没有凹痕也没有断裂。通过将击穿电压除以估计的3μm的p型金刚石层厚度，计算出金刚石p-n二极管的击穿电场达到约3.3MV/cm。在二极管上测量与温度有关的反向偏置I-V。在较高的偏置区域中，当偏置电压增加时，反向漏电流将从温度相关变为温度无关。BV随着温度的升高而增加。BV对温度的正系数是雪崩击穿的标志，雪崩击穿是高功率应用中可靠器件运行所需要的。
串联电阻源和BFOM估算
图7C示出了使用dV/dJ估计的金刚石的微分电阻。在大约8V的正向电压下，差分电阻为0.08mΩcm2，对应于12.5Ω的电阻。电阻主要来自四个因素：1)p金刚石金属接触；2)p和n接触之间的单向电阻；3)未耗尽(如果有)的p-金刚石体电阻；4)耗尽的p区的漂移电阻。使用CTLM图案并基于9.75x10-6ohm·cm2的提取值研究了p+金刚石金属的接触电阻率，接触电阻约为0.1Ω，这对于总串联电阻而言可以忽略。对于单向电流扩展电阻，假设掺杂浓度为1x1019/cm3的金刚石的电阻率(ρp+)为1x10-1ohm·cm，则在13.5μm厚p+金刚石、60μmx60μm电极、两个触点之间20μm距离的条件下，单向电阻估计为20Ω。此计算值高于12.5Ω的总串联电阻，并且被认为是由于空穴积累而低估了金刚石表面附近的导电率引起的。这表明单向电流扩展电阻是造成总电阻的主要部分的原因。另一方面，这也表示p-金刚石区域已完全耗尽，无助于二极管链路的串联电阻。此外，即使仅剩下1nm的未耗尽p金刚石区域，通过从p金刚石层的体电阻率(约105Ωcm)估计，p金刚石层的电阻计算为10mΩcm2，证实了这一说法，这比总电阻高两个数量级。因此，可以得出结论，导通电阻主要源自p和n金属触点之间的单向电流扩散电阻，并且p-金刚石层已完全耗尽，否则对于该掺杂浓度水平本会诱导大的电阻。对于GaAs/金刚石p-n二极管，在室温下Baliga功率品质因数BFOM为1.25GW/cm2。该值已超过金刚石肖特基二极管的理论极限(1000MW/cm2)。(参见，例如，Hitoshi Umezawa等人，High temperature application of diamond power device,Diamond and RelatedMaterials 24,201-205,(2012)。)鉴于导通电阻的主要部分是由触点之间的单向电阻引起的，如果重新设计了器件布局以最小化单向距离，则可以容易地获得至少高一阶的BFOM。
能带对齐和电场强度
为了进一步研究异质GaAs/金刚石二极管的高击穿电压特性，进行了在反向偏压下击穿附近跨二极管结构的能带对齐和电场强度的数值模拟。金刚石电子亲和力设置为0.1eV，其他参数(例如尺寸和掺杂)与实际二极管结构匹配。已经发现，在-800V的反向偏压下，p金刚石层中的能带弯曲极度陡峭，这表明该区域承担了大部分电压。此外，电场分布证实电场主要位于p-金刚石中，由于大的掺杂浓度(与p-金刚石对比)，该电场成指数地下降到GaAs和p+金刚石区域中。p-金刚石区域内的电场从p+侧的5MV/cm增加到GaAs侧的5MV/cm。另外，进入GaAs层的耗尽深度小于20nm。GaAs表面处的峰值电强度约为1.5MV/cm，这超过了GaAs体材料的典型击穿场值(<1MV/cm)。表面附近的GaAs承受了该强电场而没有与雪崩相关的击穿，这归因于电场长度的非常受限的长度。基于碰撞电离引发的雪崩过程，这些载流子需要足够的动能来激发结合的电子；因此，强电场和加速距离都是该过程发生的前提。电场高于1MV/cm的距离的范围小于5nm，通过该距离，载流子的积累能量不足以使其他结合的电子电离。
实施方案2：Si/Ge/金刚石p-n-p HBT。
在该实施例中，已经实现了由可转移的单晶Si和Ge NM形成的基于金刚石的混合p-n-p异质结双极晶体管(HBT)。这些HBT包括p-Si NM发射极，n-Ge NM基极和p金刚石集电极，它们在界面处通过由ALD形成的超薄Al2O3量子隧穿层结合并钝化。在金刚石上使用氧表面处理并通过Al2O3原子薄层进行钝化，由于发射极(Si NM)与基极(Ge NM)之间的尖锐和大的能带偏移(band offset)，HBT获得了显著的收益。此外，基极-集电极(B-C)二极管的高击穿电压证明了金刚石的优越电性能，以及其在高功率和高频HBT器件中的有用性。
结果与讨论
混合金刚石集电极HBT装置的制造始于对中等硼掺杂的p型高压高温(HPHT)金刚石衬底进行化学清洁工艺的性能。将金刚石衬底加载到ALD系统中，并通过五个ALD循环沉积Al2O3层(约0.5nm厚)。p+/p-Si NM和n+Ge NM由分别用作发射极和基极层的绝缘体上硅(SOI)晶片和绝缘体上锗(GeOI)晶片制成。在不使用粘合剂层的情况下，转印方法的详细信息可以在其他地方找到。(例如参见，M.A.Meitl,Z.T.Zhu,V.Kumar,K.J.Lee,X.Feng,等人,Transfer printing by kinetic control of adhesion to an elastomericstamp.Nature Mater.5,33-38(2006))。对于基极层的形成，首先将n+Ge NM结合在Al2O3涂覆的金刚石衬底上，并通过快速热退火(RTA)进行退火，然后沉积另一薄Al2O3钝化层。最后，将发射极层的p+/p-Si NM结合在Ge/金刚石的顶部。首先沉积Ti/Au叠层发射极，然后通过反应离子刻蚀机(RIE)进行台面刻蚀。将Ti/Au叠层基极电极沉积在基极台面上，然后通过RIE暴露金刚石层。在将欧姆金属Ti/Pt/Au沉积在金刚石衬底上并进行退火之前，刻蚀约50nm的金刚石层。为了与金刚石形成欧姆接触，在金属沉积之前，通过ALD沉积薄的Al2O3层。所有HBT器件均通过等离子增强化学气相沉积(PECVD)用SiO2进行钝化，并通过互连金属沉积完成。HBT的发射极、基极和集电极指的宽度分别为4μm、3μm和3μm。在350℃下退火100秒钟可获得最佳的欧姆行为。发射极总面积为160μm2。
使用原子力显微镜(AFM)测量裸金刚石衬底和转移的NM的表面粗糙度。裸金刚石衬底和转移的Ge NM的表面粗糙度为约0.715nm和0.385nm的均方根(RMS)。NM和金刚石的光滑表面(类似于抛光晶片)使得在转印后产生高品质的结合界面成为可能。此外，还进行了X射线衍射(XRD)和拉曼光谱分析，以评估裸露金刚石衬底的晶体品质，这对于其在HBT中的高频和高功率操作是重要的。衬底在1332cm-1处明显显示出良好的sp3结合。XRD还证实了半峰全宽(FWHM)值为0.018°的(4，0，0)晶体取向，表明金刚石衬底的高结晶度。通过霍尔测量检查硼浓度，显示出载流子浓度为约5×1017cm-3。
在表面处理过程中，首先通过快速热加工机在两个不同的温度下(在220℃下4分钟和450℃下1分钟)烧结金刚石衬底，然后通过反应离子刻蚀机进行氧等离子体处理30秒钟(50sccm O2,100毫托，10瓦)。在表面工程处理之前和之后拍摄的X射线光电子能谱(XPS)光谱显示，氧峰出现在534eV处，且在氧等离子体处理后变得显著更强。此外，通过与对应于金刚石sp3 C–C和C–O的去卷积峰的峰拟合显示，碳氧结合峰的明显增加表明在用氧等离子体处理后的金刚石表面上形成的碳氧结合比例更大。观察到，典型的体金刚石sp3 C–C发射偏移了0.24eV，这可以用由电子亲和力变化实现的金刚石表面附近的能带弯曲差异解释。处理前C-O峰的存在表明所接收的金刚石未完全氢化，并包含一定比例的氧化的碳。还通过表面处理之前和之后的接触角测量确认了氧结合封端变化。随着金刚石表面封端从碳氢占优的结合变为碳氧占优的结合，表面润湿性增强，导致减小的接触角。氧处理前后的接触角的对应值为θ＝65.7°和17.7°，这证实了氧等离子体处理使C-O结合的比率增加。在图8中示出了基于金刚石表面条件检查，在接触之前，pnp Si/Ge/C HBT的能带对齐，其对金刚石采用正电子亲和力。
图9A和9B分别示出了来自发射极-基极(E-B)结二极管和基极-集电极(C-B)结二极管的典型I-V特性。E-B结二极管明显显示出良好的整流特性，在±3V时开/关比为107倍；C-B结二极管显示出稳定的反向电流特性，具有大于-17V的击穿电压。在室温下对HBT进行电流-电压测量(IC-VEC)以表征器件性能。图9C示出了具有4×40μm2的发射极台面面积的HBT的输出特性。在施加至集电极时，在不击穿的情况下，HBT工作良好直至6V。在图9D中，Gummel曲线表明，在2.8V的VEB和约50μA的输出电流下出现的最大电流增益(βmax)为49。通过优化集电极掺杂浓度和厚度，或采用下面的重度掺杂p型金刚石作为触点，可以进一步改善小输出电流。图10A示了电流增益随集电极电流密度的变化，而VCB从0V变化至2V。峰值电流增益出现在25A/cm2的集电极电流密度下。在2V的VCB下，测得的最高电流增益为150，这与基极(Ge NM)和发射极(Si NM)之间的高带隙偏差有关。如在图10A所示，将电流增益的导数的最高点用作RF测量的偏置点。测量了HBT，且射频(RF)特性显示了在-5V的VCB和0.06μA的偏置点(IB)处，单向功率增益(U)和最大稳定增益(MSG)/最大可用增益(MAG)与频率的关系(图10B)。在40GHz下的单向功率增益测量为12dB，并且可以通过优化集电极掺杂水平、基极厚度和发射极指宽在工作频率下获得更高的功率增益值。而且，如图10C所示，外推的fmax和fT分别为140GHz和40GHz，两者在11A/cm2的集电极电流密度下均表现出最高值。
方法
通用HBT制造工艺：器件制造始于中等硼掺杂的p型高压高温(HPHT)金刚石衬底(4mm×4mm)，该衬底在完成NM结合后用作集电极层。将金刚石衬底加载到ALD系统中，并在其上沉积非常薄(约0.5nm厚)的Al2O3层。p+/p-Si NM和n+Ge NM由分别用作发射极层和基极层的绝缘体上硅(SOI)晶片和绝缘体上锗(GeOI)晶片制成。对于基极层的形成，将n+Ge NM结合在Al2O3涂覆的金刚石衬底上，并通过RTA进行退火，然后沉积另一非常薄(约0.5nm)的Al2O3层。然后，将用于发射极层的p+/p-Si NM结合到完成的p-n-p Si/Ge/金刚石异质结构的结构。沉积Ti/Au叠层发射极电极并通过反应离子刻蚀机(RIE)进行台面刻蚀。沉积Ti/Au叠层基极电极，并继续通过RIE台面刻蚀至金刚石层。通过氧等离子体刻蚀约50nm的金刚石层。将欧姆金属Ti/Pt/Au沉积在金刚石衬底上，并通过RTA进行退火。通过等离子体增强化学气相沉积(PECVD)将所有HBT器件都用SiO2钝化，并通过互连沉积完成。
进行能量色散X射线(EDX)光谱法以验证在三甲基铝(TMA)和H2O步骤10次循环后金刚石衬底上Al2O3 ALD层的存在，这相当于在金刚石衬底上0.5nm厚的Al2O3层。从不同斑点处获得的EDX光谱以及在金刚石衬底上的放大倍数证实均匀沉积了0.5nm厚的Al2O3ALD层。
与金刚石集电极层的欧姆接触：在金刚石上形成欧姆接触需要高温退火工艺。但是，金刚石/Ge/Si异质结构中金刚石集电极层的欧姆退火工艺受到具有最低耐热性的层(在这种情况下为Ge NM)的限制。因此，不可能在450℃-600℃的常规退火温度范围内执行高温欧姆退火工艺来实现与金刚石的欧姆接触。为了适应NM热容限，开发了Al2O3辅助的Ti/Pt/Au欧姆金属叠层，以通过插入超薄Al2O3层有效降低所需的退火温度以形成欧姆金属。如图11A所示，具有1nm Al2O3 ALD层的Ti/Pt/Au金属叠层在N2氛围中在350℃下退火100秒后显示出非常好的欧姆IV特性(图11B)，这比传统金刚石-金属接触所需的退火温度低100℃-200℃。
单词“说明性”在本文中用来表示用作实施例、例子或说明。本文中被描述为“说明性”的任何方面或设计不必被解释为相对于其他方面或设计是优选的或有利的。此外，出于本公开的目的，除非另有说明，否则“一”表示“一或多”。
为了说明和描述的目的，已经给出了本发明的说明性实施方案的前述说明。并不旨在穷举本发明或将本发明限制为所公开的精确形式，并且鉴于以上教导，修改和变化是可能的，或者可以从本发明的实践中获得所述修改和变化。选择和描述实施方案是为了解释本发明的原理以及作为本发明的实际应用，以使本领域技术人员能够在各种实施方案中以适合预期的特定用途的各种修改来利用本发明。本发明的范围旨在由所附的权利要求书及其等同物来限定。

Claims (12)

1.一种p-n二极管，包含：
具有上表面的p型金刚石层，该上表面具有氧封端为主的表面条件和正电子亲和力；
单晶n型半导体材料层，该单晶n型半导体材料的晶格常数与金刚石不同；和
设置在金刚石的上表面和单晶n型半导体材料层的下表面之间并与之接触的电流隧穿层，其中电流隧穿层包含无机材料，该无机材料具有的带隙比单晶n型半导体材料和金刚石的带隙宽，并且其中该无机材料不是单晶n型半导体材料的天然氧化物。
2.根据权利要求1所述的二极管，其中所述n型半导体材料是n型GaAs。
3.根据权利要求2所述的二极管，其中所述无机材料是氧化铝。
4.根据权利要求2所述的二极管，在25℃的温度下具有至少1kV的击穿电压。
5.根据权利要求1所述的二极管，其中所述n型半导体材料是n型Ge。
6.根据权利要求5所述的二极管，其中所述无机材料是氧化铝。
7.一种异质结双极晶体管，包含：
集电极，包含具有上表面的p型金刚石层，该上表面具有氧封端为主的表面条件和正电子亲和力；
基极，包含单晶n型半导体材料层，所述单晶n型半导体材料的晶格常数与金刚石不同；
设置在金刚石层的上表面和单晶n型半导体材料层的下表面之间并与之接触的电流隧穿层，其中电流隧穿层包含无机材料，该无机材料具有的带隙比单晶n型半导体材料和金刚石的带隙宽，并且其中该无机材料不是单晶n型半导体材料的天然氧化物；和
发射极，包含单晶p型半导体材料层。
8.根据权利要求7所述的晶体管，其中所述单晶n型半导体材料是n型GaAs，并且所述单晶p型半导体材料是p型AlGaAs。
9.根据权利要求7所述的晶体管，其中所述单晶n型半导体材料是n型InGaAs，并且所述单晶p型半导体材料是p型InAlAs。
10.根据权利要求7所述的晶体管，其中所述单晶n型半导体材料是n型Ge，并且所述单晶p型半导体材料是p型Si。
11.根据权利要求10所述的晶体管，其中所述基极-集电极二极管在25℃的温度下具有至少15V的击穿电压。
12.根据权利要求7所述的晶体管，其进一步包含第二电流隧穿层，所述第二电流隧穿层设置在单晶n型半导体材料层的上表面与单晶p型半导体材料层的下表面之间并与之接触。
CN201980044286.4A 2018-07-09 2019-05-29 具有金刚石集电极和电流隧穿层的p-n二极管和p-n-p异质结双极晶体管 Active CN112400237B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/029,811 US10497817B1 (en) 2018-07-09 2018-07-09 P-n diodes and p-n-p heterojunction bipolar transistors with diamond collectors and current tunneling layers
US16/029,811 2018-07-09
PCT/US2019/034265 WO2020013924A1 (en) 2018-07-09 2019-05-29 P-n diodes and p-n-p heterojunction bipolar transistors with diamond collectors and current tunneling layers

Publications (2)

Publication Number Publication Date
CN112400237A CN112400237A (zh) 2021-02-23
CN112400237B true CN112400237B (zh) 2024-01-26

Family

ID=68695794

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980044286.4A Active CN112400237B (zh) 2018-07-09 2019-05-29 具有金刚石集电极和电流隧穿层的p-n二极管和p-n-p异质结双极晶体管

Country Status (4)

Country Link
US (1) US10497817B1 (zh)
KR (1) KR102434521B1 (zh)
CN (1) CN112400237B (zh)
WO (1) WO2020013924A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1574155A (zh) * 2003-06-11 2005-02-02 佳能株式会社 具有偶极子层的电子发射器件、电子源和图像显示器
CN101361154A (zh) * 2006-09-19 2009-02-04 住友电气工业株式会社 金刚石电子源及制造其的方法
CN104851920A (zh) * 2014-02-17 2015-08-19 株式会社东芝 半导体装置以及其制造方法
CN105074872A (zh) * 2013-03-14 2015-11-18 威斯康星州男校友研究基金会 晶格失配的异质结结构和由其制备的器件
CN107331602A (zh) * 2017-06-27 2017-11-07 中国科学院微电子研究所 一种金刚石材料表面空穴浓度提高方法
CN107369720A (zh) * 2017-07-05 2017-11-21 西安交通大学 一种p型金刚石高低势垒肖特基二极管及其制备方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371378A (en) * 1992-06-08 1994-12-06 Kobe Steel Usa, Inc. Diamond metal base/permeable base transistor and method of making same
US5285089A (en) * 1992-12-02 1994-02-08 Kobe Steel U.S.A., Inc. Diamond and silicon carbide heterojunction bipolar transistor
US6482711B1 (en) 1999-10-28 2002-11-19 Hrl Laboratories, Llc InPSb/InAs BJT device and method of making
JP5068402B2 (ja) 2000-12-28 2012-11-07 公益財団法人国際科学振興財団 誘電体膜およびその形成方法、半導体装置、不揮発性半導体メモリ装置、および半導体装置の製造方法
US7030428B2 (en) 2001-12-03 2006-04-18 Cree, Inc. Strain balanced nitride heterojunction transistors
JP3573737B2 (ja) 2002-01-18 2004-10-06 Ｎｅｃ化合物デバイス株式会社 ヘテロ接合バイポーラ・トランジスタおよび半導体集積回路
US7019383B2 (en) 2003-02-26 2006-03-28 Skyworks Solutions, Inc. Gallium arsenide HBT having increased performance and method for its fabrication
US6992337B2 (en) 2004-04-02 2006-01-31 Agilent Technologies, Inc. Gallium arsenide antimonide (GaAsSB)/indium phosphide (InP) heterojunction bipolar transistor (HBT) having reduced tunneling probability
US7354809B2 (en) 2006-02-13 2008-04-08 Wisconsin Alumi Research Foundation Method for double-sided processing of thin film transistors
US7777290B2 (en) 2006-06-13 2010-08-17 Wisconsin Alumni Research Foundation PIN diodes for photodetection and high-speed, high-resolution image sensing
US8217410B2 (en) 2009-03-27 2012-07-10 Wisconsin Alumni Research Foundation Hybrid vertical cavity light emitting sources
US8232617B2 (en) 2009-06-04 2012-07-31 Wisconsin Alumni Research Foundation Flexible lateral pin diodes and three-dimensional arrays and imaging devices made therefrom
JP5537525B2 (ja) * 2011-09-26 2014-07-02 株式会社東芝 半導体装置および半導体装置の製造方法
JP6104575B2 (ja) * 2012-11-28 2017-03-29 株式会社東芝 半導体装置
FR3004853B1 (fr) * 2013-04-22 2016-10-21 Centre Nat Rech Scient Procede de fabrication d'une diode schottky sur un substrat en diamant
US9425351B2 (en) * 2014-10-06 2016-08-23 Wisconsin Alumni Research Foundation Hybrid heterostructure light emitting devices
JP6444718B2 (ja) * 2014-12-15 2018-12-26 株式会社東芝 半導体装置
CN107112205B (zh) * 2015-01-16 2020-12-22 住友电气工业株式会社 半导体衬底及其制造方法，组合半导体衬底及其制造方法
KR102531224B1 (ko) * 2015-12-25 2023-05-10 이데미쓰 고산 가부시키가이샤 적층체
US10418475B2 (en) * 2016-11-28 2019-09-17 Arizona Board Of Regents On Behalf Of Arizona State University Diamond based current aperture vertical transistor and methods of making and using the same
US10686084B2 (en) * 2017-03-01 2020-06-16 Phase Sensitive Innovations, Inc. Diamond-backed photodiodes, diamond-sandwiched photodiodes, photodiode systems and related methods of manufacture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1574155A (zh) * 2003-06-11 2005-02-02 佳能株式会社 具有偶极子层的电子发射器件、电子源和图像显示器
CN101361154A (zh) * 2006-09-19 2009-02-04 住友电气工业株式会社 金刚石电子源及制造其的方法
CN105074872A (zh) * 2013-03-14 2015-11-18 威斯康星州男校友研究基金会 晶格失配的异质结结构和由其制备的器件
CN104851920A (zh) * 2014-02-17 2015-08-19 株式会社东芝 半导体装置以及其制造方法
CN107331602A (zh) * 2017-06-27 2017-11-07 中国科学院微电子研究所 一种金刚石材料表面空穴浓度提高方法
CN107369720A (zh) * 2017-07-05 2017-11-21 西安交通大学 一种p型金刚石高低势垒肖特基二极管及其制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
氢、氧终端掺硼金刚石薄膜的电子结构;刘峰斌等;物理学报;第57卷(第02期);第1171-1176页 *

Also Published As

Publication number Publication date
WO2020013924A1 (en) 2020-01-16
KR20210018939A (ko) 2021-02-18
CN112400237A (zh) 2021-02-23
KR102434521B1 (ko) 2022-08-19
US10497817B1 (en) 2019-12-03

Similar Documents

Publication Publication Date Title
US11355594B2 (en) Diode
US10158009B2 (en) Method of making a graphene base transistor with reduced collector area
US7960198B2 (en) Method of making a semiconductor device with surge current protection
US9136400B2 (en) Semiconductor device
US20150041762A1 (en) Transistor Having Graphene Base
US9564491B2 (en) Semiconductor device
US8823140B2 (en) GaN vertical bipolar transistor
US20120025169A1 (en) Nanostructure array transistor
JP5140998B2 (ja) ワイドバンドギャップ半導体装置およびその製造方法
JP2006352028A (ja) 整流素子およびその製造方法
JP2002541682A (ja) パンチスルーダイオード及び同ダイオードを製造する方法
US11322593B2 (en) Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
CN112400237B (zh) 具有金刚石集电极和电流隧穿层的p-n二极管和p-n-p异质结双极晶体管
US10181515B2 (en) Semiconductor device
CN111029410A (zh) 一种结势垒肖特基结构的二极管及其制造方法
KR20190140603A (ko) 헤테로 접합 바이폴라 트랜지스터
WO2024122610A1 (ja) ジャンクションバリアショットキーダイオード及びその製造方法
CN118435360A (zh) 结势垒肖特基二极管及其制造方法
CN116053305A (zh) 一种具有双层异质结构的混合阳极GaN整流芯片及制备方法
CN118380477A (zh) 一种极化结和双阳极结构的肖特基二极管及制备方法和应用
CN111081543A (zh) 一种基于二维材料/氮化镓的双极型三极管及其制备方法
CN115985777A (zh) GaN基HEMT器件的制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 40040326

Country of ref document: HK

GR01 Patent grant
GR01 Patent grant