CN112309857A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN112309857A
CN112309857A CN201910676160.0A CN201910676160A CN112309857A CN 112309857 A CN112309857 A CN 112309857A CN 201910676160 A CN201910676160 A CN 201910676160A CN 112309857 A CN112309857 A CN 112309857A
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region
forming
fin
substrate
mask layer
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陈德艳
李茂�
郑大燮
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201910676160.0A priority Critical patent/CN112309857A/zh
Priority to US16/938,269 priority patent/US11545396B2/en
Publication of CN112309857A publication Critical patent/CN112309857A/zh
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Abstract

一种半导体结构及其形成方法，其中，形成方法包括：提供衬底，所述衬底包括第一区域和第二区域；在所述衬底上形成若干鳍部；在相邻所述鳍部之间形成隔离结构；在所述衬底及所述鳍部上形成掩膜层；去除所述第一区域的所述掩膜层，形成开口；沿所述开口去除所述第一区域的所述隔离结构；去除所述掩膜层；形成横跨所述鳍部的栅极结构，所述栅极结构覆盖所述第一区域。采用本发明方法形成的半导体结构，可以降低半导体器件的导通电阻，提高击穿电压，从而提高半导体器件的性能。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
随着半导体技术的发展，功率集成电路(Power Integrated Circuit，PIC)不断在多个领域中使用，横向双扩散金属氧化物半导体晶体管(Laterally Double-diffusedMetal Oxide Semiconductor，LDMOS)具有工作电压高、工艺简单、易于同互补金属氧化物半导体(Complementary Metal Oxide Semiconductors，CMOS)在工艺上兼容等特点而作为功率器件被广泛应用于功率集成电路中。
功率器件的源漏击穿电压(BVdss)和导通电阻(Ron)特性对于高效功率电路设计至关重要，一般而言，LDMOS器件在使用上需要较高的源漏击穿电压和低的导通电阻，以提高器件的效能。但是，LDMOS器件的导通电阻和击穿电压是矛盾的指标，如果导通电阻减小，击穿电压可能降低，反之亦然。
因此，如何通过合理的设计，在满足一定击穿电压的条件下，获得尽可能低的导通电阻以降低导通损耗是目前亟待解决的问题。
发明内容
本发明解决的技术问题是提供一种半导体结构及其形成方法，使半导体器件具有较高的击穿电压和较低的导通电阻。
为解决上述技术问题，本发明实施例提供一种半导体结构的形成方法，包括：提供衬底，所述衬底包括第一区域和第二区域；在所述衬底上形成若干鳍部；在相邻所述鳍部之间形成隔离结构；在所述衬底及所述鳍部上形成掩膜层；去除所述第一区域的所述掩膜层，形成开口；沿所述开口去除所述第一区域的所述隔离结构；去除所述掩膜层；形成横跨所述鳍部的栅极结构，所述栅极结构覆盖所述第一区域。
可选的，所述掩膜层为氮化硅层或光阻层。
可选的，形成所述掩膜层的方法为化学气相沉积法。
可选的，形成所述开口的步骤包括：在所述掩膜层上形成光刻胶层；对所述光刻胶层进行光刻，形成图形化的光刻胶层；以所述图形化的光刻胶层为掩膜，刻蚀去除所述第一区域的所述掩膜层；去除所述图形化的光刻胶层，形成开口。
可选的，刻蚀所述掩膜层的方法为干法刻蚀。
可选的，去除所述第一区域的所述隔离结构的工艺为干法刻蚀。
可选的，所述干法刻蚀的刻蚀气体包括CF4、C4F8或CHF3的其中一种或多种。
可选的，在形成隔离结构过程中，还包括：向所述鳍部及所述鳍部下的所述衬底内注入第一导电离子，形成漂移区；向所述漂移区一侧的所述鳍部及所述鳍部下的所述衬底内注入第二导电离子，形成第一掺杂区。
可选的，形成所述栅极结构后，还包括：在所述栅极结构一侧的所述鳍部内注入第二导电离子，形成第二掺杂区，所述第二掺杂区位于所述漂移区上；在所述栅极结构两侧的所述鳍部内形成源区和漏区，所述第二掺杂区位于所述栅极结构和所述漏区之间。
可选的，所述第一导电离子和所述第二导电离子类型相反。
可选的，所述第一导电离子为N型离子，所述第二导电离子为P型离子。
利用上述方法形成的一种半导体结构，包括：衬底，所述衬底包括第一区域和第二区域；鳍部，位于所述衬底上；隔离结构，位于所述第二区域内的相邻所述鳍部之间；栅极结构，横跨所述鳍部，且所述栅极结构覆盖所述第一区域。
与现有技术相比，本发明实施例的技术方案具有以下有益效果：
去除了所述第一区域的所述隔离结构，在后续形成栅极结构时，用栅极材料填补去除了所述隔离结构的所述第一区域，增加栅极与所述鳍部的接触面积，即增加了沟道的有效宽度，沟道宽度的增加使电流路径更宽，可以提高电流通过的能力，降低半导体器件的导通电阻，还可以避免发生电流拥挤效应，提高器件的可靠性。
进一步，在所述漂移区上方的所述鳍部内注入第二导电离子形成第二掺杂区，且第二导电离子与所述漂移区内的掺杂离子类型相反。一般来说，耗尽区越宽需要越高的击穿电压，所述第一掺杂区和所述漂移区形成耗尽区外，增加一次离子注入形成所述第二掺杂区，所述第二掺杂区也与所述漂移区形成耗尽区，使所述漂移区形成的耗尽区变宽，可以提高半导体器件的击穿电压。
附图说明
图1是现有鳍式半导体结构的结构示意图；
图2至图9是本发明半导体结构的形成方法第一实施例中各步骤对应的结构示意图，其中，图4是图3所示立体结构未表示隔离结构的侧视图；
图10是本发明半导体结构的形成方法第二实施例的结构示意图，是图8沿AA方向的剖面结构示意图；
图11是本发明半导体结构一实施例的立体结构示意图；
图12是图11沿BB方向的剖面结构示意图。
具体实施方式
由背景技术可知，LDMOS器件在使用上需要较高的源漏击穿电压和低的导通电阻，以提高器件的效能。但是，LDMOS器件的导通电阻和击穿电压是矛盾的指标，如果导通电阻减小，击穿电压可能降低，反之亦然。
如图1所示，现有的鳍式LDMOS，在所述衬底1上形成鳍部2后，在相邻所述鳍部2之间形成隔离结构3，以此来隔离有源器件。形成所述隔离结构3后，形成横跨所述鳍部2的栅极结构4，且所述栅极结构覆盖所述隔离结构3。
上述结构的半导体器件，所述鳍部2的一部分被隔离材料所覆盖，后续形成的栅极结构4与所述鳍部2的接触面积较小，沟道的有效宽度较小，在后续工作过程中，电子从源极流向漏极时能通过的沟道宽度较窄，使导通电阻较大，电流的通过能力较弱，并且容易发生电流拥挤效应，影响半导体器件的可靠性。
为了能使半导体器件既有较高的击穿电压，又有较小的导通电阻，发明人经过研究，提供了一种半导体结构的形成方法，在相邻所述鳍部之间形成隔离结构之后，去除第一区域的所述隔离结构，后续形成的栅极结构覆盖所述第一区域，栅极材料填充所述第一区域，增加了栅极结构与所述鳍部的接触面积，即沟道的有效宽度增加，可以提高电流的通过能力，降低导通电阻。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
第一实施例
图2至图9是本发明半导体结构的形成方法第一实施例中各步骤对应的结构示意图，其中，图4是图3所示立体结构未表示隔离结构的侧视图。
参考图2，提供衬底10，所述衬底10包括第一区域和第二区域。
本实施例中，所述衬底10为硅衬底；其他实施例中，所述衬底10还可以是以下所提到的材料中的至少一种：锗(Ge)、硅锗(GeSi)、碳化硅(SiC)、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等等。
继续参考图2，在所述衬底10上形成若干鳍部20。
本实施例中，形成所述鳍部20的方法是在所述衬底10上形成图形化的掩膜层(图未示)，所述图形化的掩膜层对应需要形成所述鳍部20的位置，以所述图形化的掩膜层为掩膜刻蚀部分厚度的所述衬底10，在所述衬底10上形成若干分立排列的所述鳍部20。
参考图3，在相邻所述鳍部20之间形成隔离结构30。
本实施例中，所述隔离结构30为浅沟槽隔离结构；其他实施例中，所述隔离结构30也可以是本领域技术人员所熟知的其他隔离结构。
本实施例中，形成所述隔离结构30的方法包括：在相邻所述鳍部20之间沉积隔离层(图未示)，所述隔离层顶部高于所述鳍部20顶部；对所述隔离层进行化学机械研磨至所述隔离层顶部与所述鳍部20顶部齐平；刻蚀所述隔离层形成隔离结构30，所述隔离结构30顶部低于所述鳍部20顶部。
本实施例中，所述隔离层材料为二氧化硅。
需要说明的是，在对所述隔离层进行化学机械研磨至所述隔离层顶部与所述鳍部20顶部齐平的步骤后，对所述鳍部20及所述鳍部20下的所述衬底10进行离子注入。
参考图4，向所述鳍部20及其下的所述衬底10内注入第一导电离子，形成漂移区11。
形成漂移区11后，向所述漂移区11一侧的所述鳍部20及其下的所述衬底10内注入第二导电离子，形成第一掺杂区12。
所述第一导电离子和所述第二导电离子的类型相反。
本实施例中，所述第一导电离子为N型离子，所述N型离子可以是磷离子、砷离子、锑离子中的一种或几种；所述第二导电离子为P型离子，所述P型离子可以是硼离子、铟离子、镓离子中的一种或几种。
其他实施例中，也可以是所述第一导电离子为P型离子，所述第二导电离子为N型离子。
本实施例中，所述第一导电离子为磷离子，离子注入剂量为3E12atoms/cm2至7E12atoms/cm2，离子注入能量为50-150keV；所述第二导电离子为硼离子，离子注入剂量为2E12atoms/cm2至4E12atoms/cm2，离子注入能量为5-50keV。
参考图5，形成所述隔离结构30后，在所述衬底10及所述鳍部20上形成掩膜层40，所述掩膜层覆盖所述隔离结构30和所述鳍部20。
本实施例中，所述掩膜层40的材料为氮化硅；其他实施例中，所述掩膜层40还可以是光阻层，所述光阻层主要由树脂、感光剂、溶剂混合组成。
本实施例中，形成所述掩膜层40的方法为化学气相沉积法。
参考图6，形成所述掩膜层40后，去除所述第一区域的所述掩膜层40，形成开口。
本实施例中，形成开口的步骤包括：在所述掩膜层上形成光刻胶层(图未示)；对所述光刻胶层进行光刻，形成图形化的所述光刻胶层；以所述图形化的所述光刻胶层为掩膜，刻蚀去除所述第一区域的所述掩膜层40；去除所述图形化的光刻胶层，形成开口。
本实施例中，刻蚀所述掩膜层40的方法为干法刻蚀。
参考图7，沿所述开口去除所述第一区域的所述隔离结构30。
本实施例中，去除所述隔离结构30的方法为干法刻蚀。
本实施例中，所述干法刻蚀的刻蚀气体包括CF4、C4F8或CHF3的其中一种或多种。
去除所述第一区域的所述隔离结构30，在后续形成栅极结构时，栅极材料沉积的深度更深，使栅极结构与所述鳍部20的接触面积变大，从而增加半导体器件的有效沟道宽度。有效沟道宽度的增加可以降低器件的导通电阻，提高电流的通过能力，并且电子从源极流向漏极的过程中，由于可通过的沟道面积增加，不会发生电流拥挤效应，从而提高半导体器件的可靠性。
参考图8，去除所述掩膜层40后，形成横跨所述鳍部20的栅极结构50，所述栅极结构50覆盖所述第一区域。
本实施例中，形成所述栅极结构50的步骤包括：在所述鳍部20表面形成栅氧化层(图未示)；在所述栅氧化层表面沉积栅极材料层；对所述栅极材料层进行化学机械研磨，形成栅极结构50。
本实施例中，所述栅极结构50为金属栅极结构。
所述第一区域去除了所述隔离结构30，所述栅极材料层填补所述第一区域内所述隔离结构30去除后的沟槽，所述栅极结构50覆盖所述鳍部20的侧面的深度变深，增加了所述栅极结构50与所述鳍部20的接触面积，增加了沟道的有效宽度，降低了导通电阻。
参考图9，形成所述栅极结构50后，在所述栅极结构50两侧的所述鳍部20内形成源区21和漏区22。
本实施例中，所述源区21位于所述第一掺杂区12内，所述漏区22位于所述漂移区11内。
第二实施例
图10是图8沿AA方向的剖面结构示意图。
本实施例中，提供所述衬底10、形成所述鳍部20、形成隔离结构30、去除所述第一区域的所述隔离结构30以及形成所述栅极结构50的过程与第一实施例相同，在此不再赘述。
本实施例中，向所述鳍部20及其下的所述衬底10内注入离子，形成所述漂移区11和所述第一掺杂区12的过程也与第一实施例相同，在此不在赘述。
参考图10，形成所述栅极结构50后，在所述栅极结构50一侧的所述鳍部20内注入第二导电离子，形成第二掺杂区13，所述第二掺杂区13位于所述漂移区11上。
本实施例中，所述第二掺杂区13与所述第一掺杂区12的掺杂类型相同，与所述漂移区11的掺杂类型相反。
本实施例中，所述第二掺杂区13注入离子为硼离子，为低浓度掺杂，离子注入剂量为1E12atoms/cm2至5E12atoms/cm2。
所述第一掺杂区12位于所述漂移区11的一侧，与所述漂移区11接触的部分形成第一耗尽区。一般，耗尽区越宽，所能承受的击穿电压越高，提高半导体器件的击穿电压可以通过扩大耗尽区来实现。因此，在所述漂移区11上增加一次反型离子注入，形成所述第二掺杂区13，所述第二掺杂区13与所述漂移区11接触形成第二耗尽区，扩大了所述漂移区11形成的耗尽区宽度，从而提高半导体器件的击穿电压。
参考图11，示出了本发明半导体结构一实施例的立体结构示意图。相应的，本发明还提供一种半导体结构。所述半导体包括：
衬底100，所述衬底100包括第一区域和第二区域；鳍部200，位于所述衬底100上；隔离结构300，位于所述第二区域内的相邻所述鳍部200之间；栅极结构400，横跨所述鳍部200，且所述栅极结构覆盖所述第一区域。
本实施例中，所述半导体结构还具有源区201和漏区202，所述源区201和所述漏区202位于所述栅极结构400两侧的所述鳍部200内。
参考图12，为图11沿BB方向的剖面结构示意图。
本实施例中，所述半导体结构还包括：漂移区101，位于所述鳍部200及其下的所述衬底100内；第一掺杂区102，位于所述漂移区101一侧的所述鳍部200及其下的所述衬底100内；第二掺杂区103，位于所述栅极结构400一侧，且位于所述漂移区101上。
所述漂移区101和所述第一掺杂区102、所述第二掺杂区103的掺杂离子类型相反。本实施例中，所述漂移区101中掺杂的离子为N型离子，所述第一掺杂区102和所述第二掺杂区103中掺杂的离子为P型离子。
通过本发明实施例方法形成的半导体结构，一方面，拓宽了所述漂移区101的耗尽区，从而提高了半导体器件的击穿电压；另一方面，去除了所述第一区域的所述隔离结构300，使后续形成的栅极结构400与所述鳍部200接触面积增大，增加了沟道的有效宽度，使电流通过的面积更大，从而减小了导通电阻，使半导体器件既有较高的击穿电压，又有较低的导通电阻。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (12)

1.一种半导体结构的形成方法，其特征在于，包括：
提供衬底，所述衬底包括第一区域和第二区域；
在所述衬底上形成若干鳍部；
在相邻所述鳍部之间形成隔离结构；
在所述衬底及所述鳍部上形成掩膜层；
去除所述第一区域的所述掩膜层，形成开口；
沿所述开口去除所述第一区域的所述隔离结构；
去除所述掩膜层；
形成横跨所述鳍部的栅极结构，所述栅极结构覆盖所述第一区域。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，所述掩膜层为氮化硅层或光阻层。
3.如权利要求2所述的半导体结构的形成方法，其特征在于，形成所述掩膜层的方法为化学气相沉积法。
4.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述开口的步骤包括：
在所述掩膜层上形成光刻胶层；
对所述光刻胶层进行光刻，形成图形化的光刻胶层；
以所述图形化的光刻胶层为掩膜，刻蚀去除所述第一区域的所述掩膜层；
去除所述图形化的光刻胶层，形成开口。
5.如权利要求4所述的半导体结构的形成方法，其特征在于，刻蚀所述掩膜层的方法为干法刻蚀。
6.如权利要求1所述的半导体结构的形成方法，其特征在于，去除所述第一区域的所述隔离结构的工艺为干法刻蚀。
7.如权利要求6所述的半导体结构的形成方法，其特征在于，所述干法刻蚀的刻蚀气体包括CF4、C4F8或CHF3的其中一种或多种。
8.如权利要求1所述的半导体结构的形成方法，其特征在于，在形成隔离结构过程中，还包括：
向所述鳍部及所述鳍部下的所述衬底内注入第一导电离子，形成漂移区；
向所述漂移区一侧的所述鳍部及所述鳍部下的所述衬底内注入第二导电离子，形成第一掺杂区。
9.如权利要求8所述的半导体结构的形成方法，其特征在于，形成所述栅极结构后，还包括：
在所述栅极结构一侧的所述鳍部内注入第二导电离子，形成第二掺杂区，所述第二掺杂区位于所述漂移区上；
在所述栅极结构两侧的所述鳍部内形成源区和漏区，所述第二掺杂区位于所述栅极结构和所述漏区之间。
10.如权利要求8或9所述的半导体结构的形成方法，其特征在于，所述第一导电离子和所述第二导电离子类型相反。
11.如权利要求10所述的半导体结构的形成方法，其特征在于，所述第一导电离子为N型离子，所述第二导电离子为P型离子。
12.一种半导体结构，其特征在于，包括：
衬底，所述衬底包括第一区域和第二区域；
鳍部，位于所述衬底上；
隔离结构，位于所述第二区域内的相邻所述鳍部之间；
栅极结构，横跨所述鳍部，且所述栅极结构覆盖所述第一区域。
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