CN112106195B - 包含垂直电容器的集成电路 - Google Patents

包含垂直电容器的集成电路 Download PDF

Info

Publication number
CN112106195B
CN112106195B CN201980031257.4A CN201980031257A CN112106195B CN 112106195 B CN112106195 B CN 112106195B CN 201980031257 A CN201980031257 A CN 201980031257A CN 112106195 B CN112106195 B CN 112106195B
Authority
CN
China
Prior art keywords
layer
dielectric layer
plate
integrated circuit
vertical capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201980031257.4A
Other languages
English (en)
Chinese (zh)
Other versions
CN112106195A (zh
Inventor
X-Z·薄
P·R·史密斯
D·T·格里德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN112106195A publication Critical patent/CN112106195A/zh
Application granted granted Critical
Publication of CN112106195B publication Critical patent/CN112106195B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/813—Combinations of field-effect devices and capacitor only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/909—Microarchitecture
    • H10D84/929—Isolations
    • H10D84/931—FET isolation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CN201980031257.4A 2018-05-11 2019-05-09 包含垂直电容器的集成电路 Active CN112106195B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/977,712 US10622073B2 (en) 2018-05-11 2018-05-11 Integrated circuit including vertical capacitors
US15/977,712 2018-05-11
PCT/US2019/031417 WO2019217611A1 (en) 2018-05-11 2019-05-09 Integrated circuit including vertical capacitors

Publications (2)

Publication Number Publication Date
CN112106195A CN112106195A (zh) 2020-12-18
CN112106195B true CN112106195B (zh) 2025-01-21

Family

ID=68465262

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980031257.4A Active CN112106195B (zh) 2018-05-11 2019-05-09 包含垂直电容器的集成电路

Country Status (5)

Country Link
US (2) US10622073B2 (https=)
EP (1) EP3791428A4 (https=)
JP (2) JP2021524998A (https=)
CN (1) CN112106195B (https=)
WO (1) WO2019217611A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102765313B1 (ko) * 2019-04-02 2025-02-07 삼성전자주식회사 수직 커패시터 구조 및 이를 포함하는 비휘발성 메모리 장치
CN111968983B (zh) * 2019-05-20 2023-10-17 联华电子股份有限公司 存储器元件的结构及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6479341B1 (en) * 1998-03-02 2002-11-12 Vanguard International Semiconductor Corporation Capacitor over metal DRAM structure
US7232717B1 (en) * 2002-05-28 2007-06-19 O2Ic, Inc. Method of manufacturing non-volatile DRAM

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5495441A (en) * 1994-05-18 1996-02-27 United Microelectronics Corporation Split-gate flash memory cell
US6448615B1 (en) 1998-02-26 2002-09-10 Micron Technology, Inc. Methods, structures, and circuits for transistors with gate-to-body capacitive coupling
KR100297712B1 (ko) * 1998-07-23 2001-08-07 윤종용 고집적화를위한불휘발성메모리및그제조방법
US6083790A (en) * 1999-02-11 2000-07-04 Taiwan Semiconductor Manufacturing Company Ltd. Method for making y-shaped multi-fin stacked capacitors for dynamic random access memory cells
US6518618B1 (en) * 1999-12-03 2003-02-11 Intel Corporation Integrated memory cell and method of fabrication
US6524926B1 (en) 2000-11-27 2003-02-25 Lsi Logic Corporation Metal-insulator-metal capacitor formed by damascene processes between metal interconnect layers and method of forming same
US6888755B2 (en) * 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
ITTO20020997A1 (it) 2002-11-15 2004-05-16 St Microelectronics Srl Procedimento autoalllineato per la fabbricazione di
US20070231970A1 (en) * 2006-03-31 2007-10-04 Tsuyoshi Fukuo Cured mold compound spacer for stacked-die package
JP5129541B2 (ja) * 2007-10-15 2013-01-30 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
EP2555241A1 (en) 2011-08-02 2013-02-06 Nxp B.V. IC die, semiconductor package, printed circuit board and IC die manufacturing method
US8780628B2 (en) * 2011-09-23 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including a voltage divider and methods of operating the same
US8692306B2 (en) * 2012-01-05 2014-04-08 Taiwan Semiconductor Manufacturing Co., Ltd. Decoupling capacitor and method of making same
JP5936959B2 (ja) * 2012-09-04 2016-06-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8889484B2 (en) * 2012-10-02 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for a component package
JP6133688B2 (ja) * 2013-05-27 2017-05-24 ルネサスエレクトロニクス株式会社 半導体装置
US9508702B2 (en) * 2013-09-27 2016-11-29 Freescale Semiconductor, Inc. 3D device packaging using through-substrate posts
US9508701B2 (en) * 2013-09-27 2016-11-29 Freescale Semiconductor, Inc. 3D device packaging using through-substrate pillars
JP2016051822A (ja) * 2014-08-29 2016-04-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9728510B2 (en) * 2015-04-10 2017-08-08 Analog Devices, Inc. Cavity package with composite substrate
US9502397B1 (en) * 2015-04-29 2016-11-22 Deca Technologies, Inc. 3D interconnect component for fully molded packages
US9570456B1 (en) * 2015-07-22 2017-02-14 United Microelectronics Corp. Semiconductor integrated device including capacitor and memory cell and method of forming the same
US9984998B2 (en) * 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
JP2017157772A (ja) * 2016-03-04 2017-09-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20170278825A1 (en) * 2016-03-24 2017-09-28 Freescale Semiconductor, Inc. Apparatus and Methods for Multi-Die Packaging
JP6232464B2 (ja) * 2016-04-20 2017-11-15 株式会社フローディア 不揮発性半導体記憶装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6479341B1 (en) * 1998-03-02 2002-11-12 Vanguard International Semiconductor Corporation Capacitor over metal DRAM structure
US7232717B1 (en) * 2002-05-28 2007-06-19 O2Ic, Inc. Method of manufacturing non-volatile DRAM

Also Published As

Publication number Publication date
US20200219566A1 (en) 2020-07-09
JP2021524998A (ja) 2021-09-16
CN112106195A (zh) 2020-12-18
EP3791428A4 (en) 2021-06-16
JP2025123554A (ja) 2025-08-22
US11152068B2 (en) 2021-10-19
EP3791428A1 (en) 2021-03-17
US10622073B2 (en) 2020-04-14
WO2019217611A1 (en) 2019-11-14
US20190348119A1 (en) 2019-11-14

Similar Documents

Publication Publication Date Title
US8492224B2 (en) Metal control gate structures and air gap isolation in non-volatile memory
US8546239B2 (en) Methods of fabricating non-volatile memory with air gaps
US9123577B2 (en) Air gap isolation in non-volatile memory using sacrificial films
KR101873080B1 (ko) 고-밀도 비-휘발성 메모리 내의 에어 갭 격리를 제조하는 방법
TWI701853B (zh) 半導體裝置及其形成方法
US7773403B2 (en) Spacer patterns using assist layer for high density semiconductor devices
JP2007500949A (ja) 電荷蓄積場所を有するメモリ
JP2025123554A (ja) 垂直コンデンサを含む集積回路
US7592225B2 (en) Methods of forming spacer patterns using assist layer for high density semiconductor devices
TWI843366B (zh) 半導體器件、記憶體器件及半導體器件的形成方法
US20130307044A1 (en) Selective Air Gap Isolation In Non-Volatile Memory
US9543139B2 (en) In-situ support structure for line collapse robustness in memory arrays
CN115084136A (zh) 栅极介电层保护
US7429503B2 (en) Method of manufacturing well pick-up structure of non-volatile memory
US20160284798A1 (en) Shallow trench isolation trenches and methods for nand memory
CN107293547B (zh) 存储器装置及其形成方法
US10002768B2 (en) Semiconductor device and manufacturing method thereof
US9779983B2 (en) Methods for forming air gaps in shallow trench isolation trenches for NAND memory
KR20090070340A (ko) 플래시 메모리 소자 및 그의 제조 방법
JP4994437B2 (ja) 半導体集積回路装置及びその製造方法
JP2005294392A (ja) 不揮発性半導体記憶装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant